CN116136814A - Method, device, processor and computer readable storage medium for realizing chip test for integrated circuit with few packaging ports - Google Patents

Method, device, processor and computer readable storage medium for realizing chip test for integrated circuit with few packaging ports Download PDF

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Publication number
CN116136814A
CN116136814A CN202111366423.1A CN202111366423A CN116136814A CN 116136814 A CN116136814 A CN 116136814A CN 202111366423 A CN202111366423 A CN 202111366423A CN 116136814 A CN116136814 A CN 116136814A
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port
communication port
state
preset communication
test
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郭佳敏
刘欣洁
沈天平
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CRM ICBG Wuxi Co Ltd
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CRM ICBG Wuxi Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G06F11/2733—Test interface between tester and unit under test
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/3013—Organisation of register space, e.g. banked or distributed register file according to data content, e.g. floating-point registers, address registers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The invention relates to a method for realizing chip test for an integrated circuit with few packaging ports, which comprises the following steps: (1) Performing instruction command operation through a preset communication port of the chip, and entering a test mode; (2) In the test mode, accessing a register under normal functions through the configuration of the preset communication port, and switching the current preset communication port into a common IO port to output a corresponding test signal; (3) When the test signal is output, the common IO port is switched to a preset communication port to perform the instruction command operation of the next test signal; (4) Repeating the steps (2) to (3) until all the signals to be tested are tested. The invention also relates to a corresponding device, a processor and a storage medium thereof. The method, the device, the processor and the storage medium thereof of the invention are adopted to realize the switching between the communication port and the common IO port completely through hardware, and the CPU occupies less resources.

Description

Method, device, processor and computer readable storage medium for realizing chip test for integrated circuit with few packaging ports
Technical Field
The invention relates to the technical field of packaging test, in particular to the technical field of chip test with few packaging ports, and specifically relates to a method, a device, a processor and a computer readable storage medium for realizing chip test for an integrated circuit with few packaging ports.
Background
The existing chip test technology is mainly characterized in that after entering a test mode, a register fixed in the test mode is firstly configured, then whether a chip can work normally is judged by observing output signals of different pins, and when the packaged pins are very few, the existing technology cannot be used for chip test due to lack of an observation port; in addition, in the prior art, the test items are relatively fixed due to the fixed register setting, so that the function test is incomplete.
Testing must be performed before the chip is delivered to the customer for use. The current testing method is that through other forms of communication ports such as an I2C communication port or an SPI communication port, according to a corresponding communication protocol, a command is given to enable a test_EN to enter a testing mode, the command is continued to enable each TEST item in the testing mode, then the function of a chip is tested through a corresponding register arranged in the testing mode, the function is output from a corresponding fixed pin, and whether the function of the chip is normal is judged through an output result.
The area requirement of the chip is as small as possible on the premise of ensuring the performance, so that the cost of the chip can be saved, and the cost brought by chip application can be reduced. Then, the pins of the chip package must be as few as possible, and even some custom-made asic's require that only the I2C communication port be reserved, except for the power ground pins. And the shorter the test time of the chip, the lower the cost, the more comprehensive the test and the higher the reliability. Therefore, it is important to quickly and comprehensively test the functions of chips with few package openings.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a method, a device, a processor and a computer readable storage medium thereof for realizing chip testing of an integrated circuit with a small package opening, wherein the method, the device and the processor have comprehensive and rapid testing functions.
In order to achieve the above object, a method, an apparatus, a processor and a computer readable storage medium thereof for implementing a chip test for an integrated circuit with a small package port according to the present invention are as follows:
the method for realizing chip test of the integrated circuit with few packaging ports is mainly characterized by comprising the following steps of:
(1) Inputting instruction command operation through a preset communication port of the chip, and entering a test mode;
(2) In the test mode, accessing a register under normal functions through the configuration of the preset communication port, and switching the current preset communication port into a common IO port to output a corresponding test signal;
(3) When the test signal is output, the common IO port is switched to a preset communication port to perform the operation of inputting the instruction command of the next test signal;
(4) Repeating the steps (2) to (3) until all the signals to be tested are tested.
Preferably, the step (1) specifically includes the following steps:
(1.1) taking the zeroth PAD port PA0 of the chip as a clock input port of the preset communication port, and taking the first PAD port PA1 of the chip as a data input and output port of the preset communication port;
the zeroth PAD port PA0 and the first PAD port PA1 described in (1.2) input a first command enabling command test_en into a TEST mode according to a preset communication protocol.
Preferably, the step (2) specifically includes the following steps:
(2.1) enabling the command to enter a corresponding test item for testing according to the currently input instruction;
(2.2) accessing registers under normal functions through the preset communication port configuration in the current test mode;
(2.3) switching the zeroth PAD port PA0 and the first PAD port PA1 into common IO ports so as to output corresponding test signals.
Preferably, the step (3) specifically includes the following steps:
(3.1) when the test signals output by the zeroth PAD port PA0 and the first PAD port PA1 are output, switching the zeroth PAD port PA0 and the first PAD port PA1 into the preset communication port again;
(3.2) the chip described currently performs the next configuration of registers or instructs the next test item.
Preferably, the preset communication port specifically includes the following state transition processing procedures:
IDLE state: after entering a test mode by making an instruction command through the preset communication port, continuing to input a second instruction enabling command xram_test_en, and configuring all registers in the test mode;
in this state, if the preset communication port sends a write instruction, the address one ADDR1 state is entered, and the high eight-bit address of the register is configured; if the preset communication port is in the preset communication port switching mode i2c_mode, the preset communication port sends a stop signal in the state, the zeroth PAD port PA0 and the first PAD port PA1 are switched from the preset communication port to a test signal output port, the state machine enters a CMD state, and otherwise, the state machine continues to keep the IDLE state.
Preferably, the preset communication port further comprises the following state transition processing procedures:
CMD state: when the preset communication port is in the preset communication port exit mode i2c_mode_exit, the zeroth PAD port PA0 and the first PAD port PA1 are switched to the preset communication port, otherwise, the CMD state is kept, and the zeroth PAD port PA0 and the first PAD port PA1 are used as common IO ports to output test results.
Preferably, the preset communication port further comprises the following state transition processing procedures:
ADDR1 state: when the second instruction enabling command xram_test_en is in a trigger state, if the preset communication port continues to send a writing instruction, the writing instruction enters an ADDR2 state, a low eight-bit address of a register is configured, and otherwise, the ADDR1 state is continuously maintained.
Preferably, the ADDR2 state specifically performs the following state transition process:
when the second instruction enabling command xram_test_en is in a trigger state, if the preset communication port continues to send a write instruction, the WDAT state is entered, if the preset communication port sends a read instruction, the RDAT state is entered, and otherwise, the ADDR2 state is continuously maintained.
Preferably, the WDAT state specifically performs the following state transition process:
and according to the received writing instruction, performing data writing operation on the corresponding address register through the preset communication port, and returning to the IDLE state.
Preferably, the RDAT status specifically performs the following state transition processes:
and according to the received reading instruction, performing data reading operation on the corresponding address register through the preset communication port, and returning to the IDLE state.
The device for realizing chip test on the integrated circuit with few packaging ports is mainly characterized by comprising the following components:
a processor configured to execute computer-executable instructions;
and a memory storing one or more computer-executable instructions which, when executed by the processor, perform the steps of the method for performing chip testing for a package-port-less integrated circuit described above.
The processor for realizing the chip test for the integrated circuit with few packaging openings is mainly characterized in that the processor is configured to execute computer executable instructions, and when the computer executable instructions are executed by the processor, the steps of the method for realizing the chip test for the integrated circuit with few packaging openings are realized.
The computer readable storage medium is characterized in that the computer program is stored thereon, and the computer program can be executed by a processor to implement the steps of the method for implementing chip testing for the integrated circuit with less packaging ports.
By adopting the method, the device, the processor and the computer readable storage medium for realizing chip test for the integrated circuit with few packaging ports, all registers under normal functions can be accessed, a special register is not required to be arranged in a test module, and the area of the test module is reduced; and because all registers with normal functions can be flexibly configured, comprehensive functional tests can be performed, and the reliability of the chip is improved; in addition, as the registers can be matched, the items which need to be tested by programming normal functional programs are not existed in the prior art because the test module is not fully designed, the test time is shortened, the efficiency is improved, and the cost is saved. Meanwhile, the invention outputs the test output signal completely through the preset communication port (the I2C communication port is selected as the preset communication port in practical application), so that the dependence of chip test on the number of pins is reduced to the minimum, and the test of the whole chip can be realized only through the I2C communication port. Compared with the prior art, the chip has the advantages that pins required for testing are fewer, and the chip area is small; the switching between the communication port and the common IO port is realized completely through hardware, a complex software program is not needed, the CPU occupies less resources, and the requirements on software personnel and chip testers are not high; and the test time is short, the test function is comprehensive and the flexibility is high.
Drawings
Fig. 1 is a schematic diagram of a chip package according to the present invention.
FIG. 2 is a schematic diagram showing the function and state switching of the preset communication port and the test output port according to the present invention.
Reference numerals
VDD chip operating voltage
VSS ground
PAD port with PA0/SCL zeroth
First PAD port of PA1/SDA
IDLE state
ADDR1 Address 1
ADDR2 address 2
RDAT reads data
WDAT write data
CMD command
reg_wr write
reg_rd read
i2c_mode I2C communication port switching mode
i2c_mode_exit I2C communication port exit mode
Detailed Description
In order to more clearly describe the technical contents of the present invention, a further description will be made below in connection with specific embodiments.
Before describing in detail embodiments that are in accordance with the present invention, it should be observed that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
The method for realizing chip test on the integrated circuit with few packaging ports comprises the following steps:
(1) Inputting instruction command operation through a preset communication port of the chip, and entering a test mode;
(2) In the test mode, accessing a register under normal functions through the configuration of the preset communication port, and switching the current preset communication port into a common IO port to output a corresponding test signal;
(3) When the test signal is output, the common IO port is switched to a preset communication port to perform the operation of inputting the instruction command of the next test signal;
(4) Repeating the steps (2) to (3) until all the signals to be tested are tested.
Referring to fig. 1, as a preferred embodiment of the present invention, the step (1) specifically includes the following steps:
(1.1) taking the zeroth PAD port PA0 of the chip as a clock input port of the preset communication port, and taking the first PAD port PA1 of the chip as a data input and output port of the preset communication port;
the zeroth PAD port PA0 and the first PAD port PA1 described in (1.2) input a first command enabling command test_en into a TEST mode according to a preset communication protocol.
In practical application, the preferred I2C communication port is selected as the preset communication port for chip test, but the actual selection of the preset communication port is not limited, and after random selection can be performed according to the actual setting condition of the current chip interface, the subsequent chip test work can be completed according to the inventive idea of the present invention.
Similarly, the selection of the preset communication protocol is not limited, and in practical application, the I2C communication protocol is selected for inputting the instruction enabling command, so that the user can select the corresponding communication protocol for subsequent chip test according to the actual selection of the preset communication port.
In the chip package structure shown in fig. 1, the test_en is enabled to enter a TEST mode by the I2C communication port, that is, the PA0 and PA1 ports shown in fig. 1, according to the I2C communication protocol, and then the instruction is continued to enter a specific item to be tested.
As a preferred embodiment of the present invention, the step (2) specifically includes the following steps:
(2.1) enabling the command to enter a corresponding test item for testing according to the currently input instruction;
(2.2) accessing registers under normal functions through the I2C communication port configuration in the current test mode;
(2.3) switching the zeroth PAD port PA0 and the first PAD port PA1 into common IO ports so as to output corresponding test signals.
As a preferred embodiment of the present invention, the step (3) specifically includes the following steps:
(3.1) when the test signals output by the zeroth PAD port PA0 and the first PAD port PA1 are output, switching the zeroth PAD port PA0 and the first PAD port PA1 into the I2C communication port again;
(3.2) the chip described currently performs the next configuration of registers or instructs the next test item.
Accessing a register under normal functions through I2C configuration in a test mode, switching a PA0 port and a PA1 port into common IO ports, and outputting corresponding test signals; when the test signal is output, the PA0 and PA1 ports are switched back to the I2C communication port again, and the configuration of the next register is carried out or an instruction is given to enter another test item.
Referring to fig. 2, as a preferred embodiment of the present invention, the I2C communication port specifically includes the following state transition processing procedures:
IDLE state: after entering a test mode by making an instruction command through the I2C communication port, continuously inputting a second instruction enabling command xram_test_en, and configuring all registers in the test mode;
in this state, if the I2C communication port sends a write instruction, the address one ADDR1 state is entered, and the high eight-bit address of the register is configured; if the I2C communication port is in the I2C communication port switching mode i2c_mode, the I2C communication port sends a stop signal in the state, the zeroth PAD port PA0 and the first PAD port PA1 are switched from the I2C communication port to a test signal output port, the state machine enters the CMD state, and otherwise the IDLE state is continuously maintained.
As a preferred embodiment of the present invention, the I2C communication port further includes the following state transition processing procedures:
CMD state: when the I2C communication port is in the I2C communication port exit mode i2c_mode_exit, the zeroth PAD port PA0 and the first PAD port PA1 are switched to the I2C communication port, otherwise, the CMD state is kept, and the zeroth PAD port PA0 and the first PAD port PA1 are used as common IO ports to output test results.
As a preferred embodiment of the present invention, the I2C communication port further includes the following state transition processing procedures:
ADDR1 state: when the second instruction enabling command xram_test_en is in a trigger state, if the I2C communication port continues to send a writing instruction, the writing instruction enters an ADDR2 state, a low-eight-bit address of a register is configured, and otherwise, the ADDR1 state is continuously maintained.
As a preferred embodiment of the present invention, the ADDR2 state specifically performs the following state transition process:
when the second instruction enabling command xram_test_en is in a trigger state, if the I2C communication port continues to send a write instruction, the WDAT state is entered, if the I2C communication port sends a read instruction, the RDAT state is entered, and otherwise, the ADDR2 state is continuously maintained.
In practical applications, the above-mentioned command enable command is in the active high state, and the second command enable command xram_test_en is 1.
As a preferred embodiment of the present invention, the WDAT state specifically performs the following state transition processing:
and according to the received writing instruction, performing data writing operation on the corresponding address register through the I2C communication port, and returning to the IDLE state.
As a preferred embodiment of the present invention, the state of the RDAT specifically performs the following state transition processing:
and according to the received reading instruction, performing data reading operation on the corresponding address register through the I2C communication port, and returning to the IDLE state.
In practical application, the state transition of the register for reading and writing and switching between the I2C communication port and the test output port is described as follows:
1. IDLE state: after the I2C communication port is instructed to enter a test mode, continuing to instruct to enable the xram_test_en, and configuring all registers in the mode. In this state, if the I2C issues a write instruction, then the ADDR1 state is entered, and the high eight-bit address of the register is configured; if i2c_mode is pulled high, i.e. in this state, I2C sends out a stop signal, PA0 and PA1 are switched from the communication port to the test signal output port, the state machine enters CMD state, otherwise, the IDLE state is maintained.
2. CMD state: when i2c_mode_exit is pulled high, the PA0 and PA1 ports are switched back to the I2C communication port, otherwise, the CMD state is kept, and the PA0 and PA1 are used as common IO ports to output test results.
3. ADDR1 state: if the xram_test_en is 1, if the I2C continues to issue the write instruction, the ADDR2 state is entered, the low-eight address of the register is configured, and otherwise the ADDR1 state is maintained.
4. ADDR2 state: if xram_test_en is 1, if I2C continues to issue a write instruction, the state is WDAT, if I2C issues a read instruction, the state is RDAT, otherwise the state of ADDR2 is maintained.
5. WDAT state: in this state, data is written to the corresponding address register through I2C, and then the IDLE state is returned.
6. RDAT state: in this state, data is read from the corresponding address register through the I2C, and then the IDLE state is returned.
The device for realizing chip test on the integrated circuit with few packaging ports comprises:
a processor configured to execute computer-executable instructions;
and a memory storing one or more computer-executable instructions which, when executed by the processor, perform the steps of the method for performing chip testing for a package-port-less integrated circuit described above.
The processor for realizing the chip test for the integrated circuit with the small packaging opening is configured to execute computer executable instructions, and when the computer executable instructions are executed by the processor, the steps of the method for realizing the chip test for the integrated circuit with the small packaging opening are realized.
The computer readable storage medium having stored thereon a computer program executable by a processor to perform the steps of the method for chip testing for package-less integrated circuits described above.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and further implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution device.
Those of ordinary skill in the art will appreciate that all or a portion of the steps carried out in the method of the above-described embodiments may be implemented by a program to instruct related hardware, and the program may be stored in a computer readable storage medium, where the program when executed includes one or a combination of the steps of the method embodiments.
The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, or the like.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "examples," "specific examples," or "embodiments," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
By adopting the method, the device, the processor and the computer readable storage medium for realizing chip test for the integrated circuit with few packaging ports, all registers under normal functions can be accessed, a special register is not required to be arranged in a test module, and the area of the test module is reduced; and because all registers with normal functions can be flexibly configured, comprehensive functional tests can be performed, and the reliability of the chip is improved; in addition, as the registers can be matched, the items which need to be tested by programming normal functional programs are not existed in the prior art because the test module is not fully designed, the test time is shortened, the efficiency is improved, and the cost is saved. Meanwhile, the invention outputs the test output signal completely through the I2C communication port, reduces the dependence of chip test on the number of pins to the minimum, and can realize the test of the whole chip only through the I2C communication port. Compared with the prior art, the chip has the advantages that pins required for testing are fewer, and the chip area is small; the switching between the communication port and the common IO port is realized completely through hardware, a complex software program is not needed, the CPU occupies less resources, and the requirements on software personnel and chip testers are not high; and the test time is short, the test function is comprehensive and the flexibility is high.
In this specification, the invention has been described with reference to specific embodiments thereof. It will be apparent, however, that various modifications and changes may be made without departing from the spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims (13)

1. A method for implementing chip testing for an integrated circuit with a small package opening, the method comprising the steps of:
(1) Inputting instruction command operation through a preset communication port of the chip, and entering a test mode;
(2) In the test mode, accessing a register under normal functions through the configuration of the preset communication port, and switching the current preset communication port into a common IO port to output a corresponding test signal;
(3) When the test signal is output, the common IO port is switched to a preset communication port to perform the operation of inputting the instruction command of the next test signal;
(4) Repeating the steps (2) to (3) until all the signals to be tested are tested.
2. The method for implementing chip testing for integrated circuits with few package openings according to claim 1, wherein said step (1) specifically comprises the steps of:
(1.1) taking the zeroth PAD port PA0 of the chip as a clock input port of the preset communication port, and taking the first PAD port PA1 of the chip as a data input and output port of the preset communication port;
the zeroth PAD port PA0 and the first PAD port PA1 described in (1.2) input a first command enabling command test_en into a TEST mode according to a preset communication protocol.
3. The method for implementing chip testing for integrated circuits with fewer package openings according to claim 2, wherein said step (2) specifically comprises the steps of:
(2.1) enabling the command to enter a corresponding test item for testing according to the currently input instruction;
(2.2) accessing registers under normal functions through the preset communication port configuration in the current test mode;
(2.3) switching the zeroth PAD port PA0 and the first PAD port PA1 into common IO ports so as to output corresponding test signals.
4. The method for implementing chip testing on a package-less integrated circuit as recited in claim 3, wherein said step (3) comprises the steps of:
(3.1) when the test signals output by the zeroth PAD port PA0 and the first PAD port PA1 are output, switching the zeroth PAD port PA0 and the first PAD port PA1 into the preset communication port again;
(3.2) the chip described currently performs the next configuration of registers or instructs the next test item.
5. The method for implementing chip testing on an integrated circuit with few package ports according to any one of claims 2 to 4, wherein the preset communication port specifically includes the following state transition processing procedures:
IDLE state: after entering a test mode by making an instruction command through the preset communication port, continuing to input a second instruction enabling command xram_test_en, and configuring all registers in the test mode;
in this state, if the preset communication port sends a write instruction, the address one ADDR1 state is entered, and the high eight-bit address of the register is configured; if the preset communication port is in the preset communication port switching mode i2c_mode, the preset communication port sends a stop signal in the state, the zeroth PAD port PA0 and the first PAD port PA1 are switched from the preset communication port to a test signal output port, the state machine enters a CMD state, and otherwise, the state machine continues to keep the IDLE state.
6. The method for implementing chip testing on a package less integrated circuit according to claim 5, wherein said preset communication port further comprises the following state transition process:
CMD state: when the preset communication port is in the preset communication port exit mode i2c_mode_exit, the zeroth PAD port PA0 and the first PAD port PA1 are switched to the preset communication port, otherwise, the CMD state is kept, and the zeroth PAD port PA0 and the first PAD port PA1 are used as common IO ports to output test results.
7. The method for implementing chip testing on a package less integrated circuit of claim 6, wherein said preset communication port further comprises the following state transition process:
ADDR1 state: when the second instruction enabling command xram_test_en is in a trigger state, if the preset communication port continues to send a writing instruction, the writing instruction enters an ADDR2 state, a low eight-bit address of a register is configured, and otherwise, the ADDR1 state is continuously maintained.
8. The method for implementing chip testing on a package-less integrated circuit of claim 7, wherein said ADDR2 state specifically performs the following state transition process:
when the second instruction enabling command xram_test_en is in a trigger state, if the preset communication port continues to send a write instruction, the WDAT state is entered, if the preset communication port sends a read instruction, the RDAT state is entered, and otherwise, the ADDR2 state is continuously maintained.
9. The method for implementing chip testing for the integrated circuit with few package openings according to claim 8, wherein the WDAT state specifically performs the following state transition processing:
and according to the received writing instruction, performing data writing operation on the corresponding address register through the preset communication port, and returning to the IDLE state.
10. The method for implementing chip testing for integrated circuits with few package openings according to claim 8, wherein said RDAT state specifically performs the following state transitions:
and according to the received reading instruction, performing data reading operation on the corresponding address register through the preset communication port, and returning to the IDLE state.
11. An apparatus for implementing chip testing for an integrated circuit with a small package opening, the apparatus comprising:
a processor configured to execute computer-executable instructions;
a memory storing one or more computer-executable instructions which, when executed by the processor, perform the steps of the method of claim 10 for performing chip testing for a package-port-less integrated circuit.
12. A processor for implementing a chip test for a package-on-package integrated circuit, the processor being configured to execute computer-executable instructions that, when executed by the processor, implement the steps of the method for implementing a chip test for a package-on-package integrated circuit of claim 10.
13. A computer readable storage medium having stored thereon a computer program executable by a processor to perform the steps of the method of claim 10 for chip testing for a package-less integrated circuit.
CN202111366423.1A 2021-11-18 2021-11-18 Method, device, processor and computer readable storage medium for realizing chip test for integrated circuit with few packaging ports Pending CN116136814A (en)

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