CN116131810B - Signal processing device, chip, method and equipment - Google Patents
Signal processing device, chip, method and equipment Download PDFInfo
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- CN116131810B CN116131810B CN202310402262.XA CN202310402262A CN116131810B CN 116131810 B CN116131810 B CN 116131810B CN 202310402262 A CN202310402262 A CN 202310402262A CN 116131810 B CN116131810 B CN 116131810B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H21/00—Adaptive networks
- H03H21/0012—Digital adaptive filters
- H03H21/0067—Means or methods for compensation of undesirable effects
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H21/00—Adaptive networks
- H03H21/0012—Digital adaptive filters
- H03H2021/0085—Applications
- H03H2021/0094—Interference Cancelling
Abstract
The invention provides a signal processing device, a chip, a method and equipment. The device comprises: a comparator configured to receive the written value and the current stored value of the filter coefficient, compare the two values, and output a comparison result; an edge detector configured to receive an input signal, determine whether an edge transition occurs, and output a determination result; the state machine is respectively connected with the output ends of the comparator and the edge detector and is configured to confirm whether to output a signal containing the written value of the filter coefficient according to the comparison result and the judgment result; and the counter is respectively connected with the output end of the state machine and the output end of the edge detector, and is configured to confirm whether to count based on the written value of the filter coefficient according to the signal input by the state machine and the judgment result input by the edge detector and correspondingly output a control signal for sampling the input signal. The scheme disclosed by the invention avoids the problem that the real input signal cannot be restored due to the change of the filter coefficient.
Description
Technical Field
The present invention relates to the field of computers, and in particular, to a signal processing apparatus, a chip, a method, and a device.
Background
In the process of processing a signal, filtering (Wave filtering) is an operation of filtering out frequencies in a specific band in the signal, and is an important measure for suppressing and preventing interference. In which only signal components in a certain frequency range are allowed to pass normally, and a circuit which blocks the passage of another part of the signal components is called a filter circuit. When the input signal is severely interfered by the outside and the signal distortion is serious, the input signal needs to be adaptively filtered, and sampling is carried out according to different filter coefficients (the period of the signal which keeps stable is smaller than the filter coefficient is considered as noise), so that the real input signal is restored.
In the related art of signal processing, if a filter coefficient is suddenly changed, a new filter coefficient may affect a current filter result, and an input signal at a current moment may cause a missing problem, that is, a problem that the current input signal cannot be collected normally.
Disclosure of Invention
In view of this, the present invention provides a signal processing device, a chip, a method and a device, which solve the problem that in the related art of signal processing, when a filtering coefficient is suddenly changed, the new filtering coefficient affects the current filtering result, and the current input signal cannot be collected normally.
Based on the above object, an aspect of an embodiment of the present invention provides a signal processing apparatus including: a comparator configured to receive the written value and the current stored value of the filter coefficient, compare the two values, and output a comparison result; an edge detector configured to receive an input signal, determine whether an edge transition occurs, and output a determination result; the state machine is respectively connected with the output ends of the comparator and the edge detector and is configured to confirm whether to output a signal containing the written value of the filter coefficient according to the comparison result and the judging result; and the counter is respectively connected with the output end of the state machine and the output end of the edge detector, and is configured to confirm whether to count based on the written value of the filter coefficient according to the signal input by the state machine and the judgment result input by the edge detector and correspondingly output a control signal for sampling the input signal.
In some embodiments, the signal processing apparatus further comprises: and the selector is connected with the output end of the counter and is configured to sample the input signal according to the control signal and output a sampling result.
In some embodiments, the comparator is further configured to: and outputting a first comparison result in response to the received written value of the filter coefficient being the same as the current stored value.
In some embodiments, the comparator is further configured to: and outputting a second comparison result in response to the received written value of the filter coefficient being different from the current stored value.
In some embodiments, the edge detector is further configured to: and outputting a first judgment result in response to the received input signal that the edge jump does not occur.
In some embodiments, the edge detector is further configured to: and responding to the received input signal to generate edge jump, and outputting a second judgment result.
In some embodiments, the state machine is further configured to: and skipping to a corresponding state according to the comparison result and the judging result and confirming whether to output a signal containing the written value of the filter coefficient or not based on the corresponding state.
In some embodiments, the state machine is further configured to: in response to receiving the first comparison result and the first determination result, in an initial state and based on the initial state, a signal containing a written value of the filter coefficient is not output.
In some embodiments, the state machine is further configured to: in response to receiving the second comparison result and the second judgment result, jumping from the initial state to a signal edge jumping state; judging whether the written value of the filter coefficient is valid or not based on the signal edge jump state; and confirming whether to jump from the signal edge jump state to the output state according to the result of judging whether the written value of the filter coefficient is valid or not, and outputting a signal containing the written value of the filter coefficient.
In some embodiments, the state machine is further configured to: and in response to the written value of the filter coefficient being valid, jumping from the signal edge jumping state to the output state outputs a signal containing the written value of the filter coefficient.
In some embodiments, the state machine is further configured to: and in response to the written value of the filter coefficient being invalid, jumping from the signal edge jumping state to the initial state.
In some embodiments, the state machine is further configured to: in response to receiving the second comparison result and the first judgment result, jumping from the initial state to a signal edge non-jumping state; judging whether the second judging result is received or not and whether the written value of the filter coefficient is valid or not based on the signal edge non-jump state; and confirming whether the signal edge is jumped to an output state from the state that the signal edge is not jumped to output the signal containing the written value of the filter coefficient according to the second judgment result and the result of judging whether the written value of the filter coefficient is valid.
In some embodiments, the state machine is further configured to: and in response to receiving the second judgment result and the written value of the filter coefficient is valid, jumping from the signal edge non-jumping state to an output state outputs a signal containing the written value of the filter coefficient.
In some embodiments, the state machine is further configured to: and in response to receiving the second judgment result and the written value of the filter coefficient being invalid, jumping from the signal edge jumping state to the initial state.
In some embodiments, the state machine is further configured to: and responding to the fact that the second judging result is not received, and waiting for receiving the second judging result in the state that the signal edge is not jumped.
In some embodiments, the signal processing apparatus further comprises: and the first register is connected with the input end of the comparator and is configured to store the current stored value of the filter coefficient and output the current stored value to the comparator.
In some embodiments, the signal processing apparatus further comprises: and the second register is connected with the input end of the edge detector and is configured for storing the current value of the received input signal, outputting the current value to the edge detector and outputting the current value to the selector.
In some embodiments, the signal processing apparatus further comprises: and the third register is connected with the output end of the second register, is configured to store the previous value of the input signal and outputs the previous value to the selector.
In another aspect of the embodiment of the present invention, there is also provided a signal processing chip, including: a comparator circuit configured to receive the written value and the current stored value of the filter coefficient, compare the two values, and output a comparison result; an edge detector circuit configured to receive an input signal, determine whether an edge transition occurs, and output a determination result; a state machine circuit connected to outputs of the comparator circuit and the edge detector circuit, respectively, and configured to confirm whether or not to output a signal containing a write value of the filter coefficient based on the comparison result and the determination result; and the counter circuit is respectively connected with the output of the state machine circuit and the output of the edge detector circuit, and is configured to confirm whether to count based on the written value of the filter coefficient according to the signal input by the state machine circuit and the judgment result input by the edge detector circuit and correspondingly output a control signal for sampling the input signal.
In some embodiments, the signal processing chip further comprises: and the selector circuit is connected with the output of the counter circuit and is configured to sample the input signal according to the control signal and output a sampling result.
In some embodiments, the comparator circuit is further configured to: and outputting a first comparison result in response to the received written value of the filter coefficient being the same as the current stored value.
In some embodiments, the comparator circuit is further configured to: and outputting a first comparison result in response to the received written value of the filter coefficient being the same as the current stored value.
In some embodiments, the comparator circuit is further configured to: and outputting a second comparison result in response to the received written value of the filter coefficient being different from the current stored value.
In some embodiments, the edge detector circuit is further configured to: and outputting a first judgment result in response to the received input signal that the edge jump does not occur.
In some embodiments, the edge detector circuit is further configured to: and responding to the received input signal to generate edge jump, and outputting a second judgment result.
In some embodiments, the state machine circuit is further configured to: and skipping to a corresponding state according to the comparison result and the judging result and confirming whether to output a signal containing the written value of the filter coefficient or not based on the corresponding state.
In some embodiments, the state machine circuit is further configured to: in response to receiving the first comparison result and the first determination result, in an initial state and based on the initial state, a signal containing a written value of the filter coefficient is not output.
In some embodiments, the state machine circuit is further configured to: in response to receiving the second comparison result and the second judgment result, jumping from the initial state to a signal edge jumping state; judging whether the written value of the filter coefficient is valid or not based on the signal edge jump state; and confirming whether to jump from the signal edge jump state to the output state according to the result of judging whether the written value of the filter coefficient is valid or not, and outputting a signal containing the written value of the filter coefficient.
In some embodiments, the state machine circuit is further configured to: and in response to the written value of the filter coefficient being valid, jumping from the signal edge jumping state to the output state outputs a signal containing the written value of the filter coefficient.
In some embodiments, the state machine circuit is further configured to: and in response to the written value of the filter coefficient being invalid, jumping from the signal edge jumping state to the initial state.
In some embodiments, the state machine circuit is further configured to: in response to receiving the second comparison result and the first judgment result, jumping from the initial state to a signal edge non-jumping state; judging whether the second judging result is received or not and whether the written value of the filter coefficient is valid or not based on the signal edge non-jump state; and confirming whether the signal edge is jumped to an output state from the state that the signal edge is not jumped to output the signal containing the written value of the filter coefficient according to the second judgment result and the result of judging whether the written value of the filter coefficient is valid.
In some embodiments, the state machine circuit is further configured to: and in response to receiving the second judgment result and the written value of the filter coefficient is valid, jumping from the signal edge non-jumping state to an output state outputs a signal containing the written value of the filter coefficient.
In some embodiments, the state machine circuit is further configured to: and in response to receiving the second judgment result and the written value of the filter coefficient being invalid, jumping from the signal edge jumping state to the initial state.
In some embodiments, the state machine circuit is further configured to: and responding to the fact that the second judging result is not received, and waiting for receiving the second judging result in the state that the signal edge is not jumped.
In some embodiments, the signal processing chip further comprises: and the first register circuit is connected with the input of the comparator circuit and is configured to store the current stored value of the filter coefficient and output the current stored value to the comparator circuit.
In some embodiments, the signal processing chip further comprises: and a second register circuit connected to the input of the edge detector circuit and configured to hold a current value of the received input signal and output to the edge detector circuit and to the selector circuit.
In some embodiments, the signal processing chip further comprises: and a third register circuit connected to an output of the second register circuit, configured to hold a previous value of the input signal, and output the previous value to the selector circuit.
In another aspect of the embodiment of the present invention, there is also provided a signal processing method, including: comparing the received written value of the filter coefficient with the current stored value through a comparator, and outputting a comparison result to a state machine; judging whether the received input signal generates edge jump or not through an edge detector, and outputting a judging result to the state machine; the state machine confirms whether to output a signal containing the written value of the filter coefficient to a counter according to the received comparison result and the judgment result; and receiving signals input by the state machine through the counter, confirming whether to count based on the written value of the filter coefficient based on the judging result input by the edge detector, and correspondingly outputting a control signal for sampling the input signals.
In another aspect of the embodiment of the present invention, there is also provided a signal processing apparatus including at least one processor; and a memory storing computer instructions executable on the processor, the instructions when executed by the processor performing the steps of the method described above.
In another aspect of the embodiments of the present invention, there is also provided a computer-readable storage medium storing a computer program which, when executed by a processor, implements the method steps as described above.
The invention has at least the following beneficial effects: the signal processing device provided by the invention can avoid missing the input signal when the filter coefficient changes in the process of adaptively filtering the input signal, avoid undersampling the input signal to restore the real input signal due to the change of the filter coefficient, and realize the maximum restoration of the real input signal in the signal processing process.
Drawings
In order to more clearly illustrate the embodiments of the invention or the solutions of the prior art, the drawings which are necessary for the description of the embodiments or the prior art will be briefly described, it being evident that the drawings in the following description are only some embodiments of the invention and that other embodiments can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a signal processing device according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a signal processing device according to another embodiment of the present invention;
fig. 3 is a process diagram of state switching of a state machine in a signal processing apparatus according to an embodiment of the present invention;
fig. 4 shows a flowchart of a signal processing method according to an embodiment of the present invention;
fig. 5 shows a schematic structural diagram of a signal processing apparatus according to an embodiment of the present invention;
fig. 6 shows a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention are described below. However, it is to be understood that the disclosed embodiments are merely examples and that other embodiments may take various alternative forms.
Furthermore, it should be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
One or more embodiments of the present application will be described below with reference to the accompanying drawings.
Based on the above object, a first aspect of the embodiments of the present invention proposes an embodiment of a signal processing apparatus. Fig. 1 is a schematic structural diagram of a signal processing device according to an embodiment of the present invention, where, as shown in fig. 1, the signal processing device includes: a comparator configured to receive the written value and the current stored value of the filter coefficient, compare the two values, and output a comparison result; an edge detector configured to receive an input signal, determine whether an edge transition occurs, and output a determination result; the state machine is respectively connected with the output ends of the comparator and the edge detector and is configured to confirm whether to output a signal containing the written value of the filter coefficient according to the comparison result and the judging result; and the counter is respectively connected with the output end of the state machine and the output end of the edge detector, and is configured to confirm whether to count based on the written value of the filter coefficient according to the signal input by the state machine and the judgment result input by the edge detector and correspondingly output a control signal for sampling the input signal.
According to several embodiments of the present invention, the signal processing apparatus further comprises: and the selector is connected with the output end of the counter and is configured to sample the input signal according to the control signal and output a sampling result.
According to several embodiments of the invention, the comparator is further configured to: and outputting a first comparison result in response to the received written value of the filter coefficient being the same as the current stored value.
According to several embodiments of the invention, the comparator is further configured to: and outputting a second comparison result in response to the received written value of the filter coefficient being different from the current stored value.
According to several embodiments of the invention, the edge detector is further configured to: and outputting a first judgment result in response to the received input signal that the edge jump does not occur.
According to several embodiments of the invention, the edge detector is further configured to: and responding to the received input signal to generate edge jump, and outputting a second judgment result.
According to several embodiments of the present invention, the state machine is further configured to: and skipping to a corresponding state according to the comparison result and the judgment result and confirming whether to output a signal containing the written value of the filter coefficient or not based on the corresponding state.
According to several embodiments of the present invention, the state machine is further configured to: in response to receiving the first comparison result and the first determination result, a signal containing the written value of the filter coefficient is not output in an initial state and based on the initial state.
According to several embodiments of the present invention, the state machine is further configured to: in response to receiving the second comparison result and the second judgment result, jumping from the initial state to a signal edge jumping state; judging whether the written value of the filter coefficient is valid or not based on the signal edge jump state; and confirming whether to jump from the signal edge jump state to the output state according to the result of judging whether the written value of the filter coefficient is valid or not, and outputting the signal containing the written value of the filter coefficient.
According to several embodiments of the present invention, the state machine is further configured to: in response to the written value of the filter coefficient being valid, a signal output containing the written value of the filter coefficient is output from the signal edge transition state to the output state.
According to several embodiments of the present invention, the state machine is further configured to: the transition from the signal edge transition state to the initial state is made in response to the written value of the filter coefficient being invalid.
According to several embodiments of the present invention, the state machine is further configured to: in response to receiving the second comparison result and the first judgment result, jumping from the initial state to a signal edge non-jumping state; judging whether a second judging result is received or not based on the non-jump state of the signal edge, and judging whether the written value of the filter coefficient is valid or not; and confirming whether the signal is jumped from the signal edge non-jumped state to the output state according to the second judging result and the result of judging whether the written value of the filter coefficient is valid or not, and outputting the signal containing the written value of the filter coefficient.
According to several embodiments of the present invention, the state machine is further configured to: and in response to receiving the second judgment result and the written value of the filter coefficient being valid, jumping from the signal edge non-jumping state to the output state outputs a signal containing the written value of the filter coefficient.
According to several embodiments of the present invention, the state machine is further configured to: and in response to receiving the second judgment result and the written value of the filter coefficient being invalid, jumping from the signal edge jumping state to the initial state.
According to several embodiments of the present invention, the state machine is further configured to: and in response to not receiving the second judgment result, waiting to receive the second judgment result in the state that the signal edge is not hopped.
According to several embodiments of the present invention, the signal processing apparatus further comprises: and the first register is connected with the input end of the comparator and is configured for storing the current stored value of the filter coefficient and outputting the current stored value to the comparator.
According to several embodiments of the present invention, the signal processing apparatus further comprises: and the second register is connected with the input end of the edge detector and is configured for storing the current value of the received input signal and outputting the current value to the edge detector and the selector.
According to several embodiments of the present invention, the signal processing apparatus further comprises: and the third register is connected with the output end of the second register, is configured to store the previous value of the input signal and outputs the previous value to the selector.
The following is another embodiment of a signal processing device provided by the present invention.
The BMC (Baseboard Management Controller ) chip communicates with external devices through GPIO (General purpose input/output), and reads external signals and outputs internal signals. For external signal input, noise may be generated due to factors such as signal jitter or electromagnetic interference, and filtering and jitter elimination are needed for the input signal, i.e. filtering out the noise signal to restore the real input signal.
In the process of signal processing, when the signal is severely interfered by external environment, namely, the signal distortion is severe, the signal needs to be subjected to real-time adaptive filtering, and the real input signal is restored by setting different filtering coefficients. In the signal processing process, if the filter coefficient is changed suddenly, the newly written filter coefficient can affect the current filter result, and then the problem of missing the input signal can be caused, so that the acquired input signal is missing and the real input signal cannot be restored, and the two sides of the equipment cannot perform data communication.
Fig. 2 is a schematic structural diagram of a signal processing apparatus according to another embodiment of the present invention, as shown in fig. 2, an input signal is filtered and collected by the signal processing apparatus, a current stored value of a filter coefficient in a filter circuit is output to a comparator through a first register, a written value coff_new of the filter coefficient in the filter circuit is simultaneously output to the comparator, the current stored value and the written value coff_new of the filter coefficient are compared through the comparator, whether the current stored value and the written value coff_new are identical is determined, and a determination result (identical or different) is output to a state machine. Meanwhile, an input signal input_signal in the filter circuit is output to the edge detector through the second register, whether edge jump occurs in the input signal input_signal at the moment is judged through the edge detector, and a judging result (whether edge jump occurs or not) is output to the state machine. The state machine is respectively connected with the output end of the edge detector and the output end of the comparator, and when the state machine receives the result output by the comparator and the result output by the edge detector, the state machine judges whether to output a signal containing the filter coefficient writing value coff_new to the counter for counting according to the two results. The counter is respectively connected with the output end of the state machine and the output end of the edge detector, the numerical value for counting is determined according to the result input by the state machine, and whether 0 clearing is carried out is determined according to the result input by the edge detector. Specifically, when the counter receives a signal containing a write value coff_new of a filter coefficient input by the state machine, and receives a judging result of edge jump of an input signal input_signal input by the edge detector, the counter counts the value of the signal, clears 0 and starts counting according to the write value coff_new of the filter coefficient, and after the counter counts the write value coff_new of the filter coefficient, a control signal for sampling the input signal input_signal is sent to the selector, so that the selector samples the current value of the input signal input_signal received from the second register according to the control signal; otherwise the selector samples the previous value of the input signal input _ signal received from the third register in accordance with the current stored value of the filter coefficient. That is, the selector samples and outputs the input signal according to the control signal, i.e., the output signal. For example, when the current storage of the filter coefficient in the filter circuit is 4, and the filter coefficient is newly written into a, when the filter coefficient jumps from 4 to a, the current input signal input_signal (8 bits are the same) is 0x00, the duration period is 4 periods, the previous signal is 0xff, and the duration period is 4 periods. At the time when the filter coefficient jumps from 4 to a, the current input signal 0x00 does not jump, so that the input signal input_signal is sampled according to the current stored value 4 of the filter coefficient, and after the jump of the input signal input_signal occurs in the effective period of the filter coefficient a, the input signal input_signal is sampled according to the new filter coefficient a.
Fig. 3 is a process diagram of state switching of a state machine in the signal processing apparatus according to the embodiment of the present invention, as shown in fig. 3, when the state machine is not configured with a filter coefficient, the state machine defaults to an IDLE state (initial state), and at this time, the filter coefficient of the filter circuit defaults to 0, and no filtering and jitter removing operation is performed, and at this time, an output signal is an input signal.
If the input signal jumps and a new filter coefficient (namely EDGE & coff changed) is written at the same time, the state machine jumps from the IDLE state to the signal EDGE jump state (EDGE state), then judges whether the current newly written filter coefficient is 0 or not in the EDGE state, and confirms whether to jump to the OUTPUT state (OUTPUT state) or to the IDLE state according to the judging result. Specifically, if the current newly written filter coefficient is not 0 (cof |=0), the state machine transitions from the EDGE state to the OUTPUT state to sample the input; if the current newly written filter coefficient is 0 (coff=0), the state machine transitions from EDGE state to IDLE state.
If the input signal does not jump and a new filter coefficient is written at the same time (namely NO EDGE & & coff changed), the state machine jumps from the IDLE state to the NO_EDGE state (signal EDGE non-jump state), and then waits for the input signal jump EDGE to arrive in the NO_EDGE state. If NO input signal jump EDGE arrives, the state machine continues waiting in the NO_EDGE state; if the input signal has EDGE jump (EDGE), judging whether the current newly written filter coefficient is 0 in the NO_EDGE state, and confirming whether to jump to the OUTPUT state (OUTPUT state) or to jump to the IDLE state according to the judging result. Specifically, if an EDGE transition occurs in the input signal and the current newly written filter coefficient is not 0 (cof |=0 & & EDGE), the state machine transitions from the no_edge state to the OUTPUT state to sample the input; if the current newly written filter coefficient is 0 (coff=0), the state machine transitions from EDGE state to IDLE state.
After the state machine enters the OUTPUT state, the state machine performs filtering operation by using the updated filtering coefficient in the state. If the current filter coefficient is changed continuously, according to whether the current input signal has edge jump or not, corresponding state jump is further carried out continuously, the latest filter coefficient is updated, and then the filter operation is carried out continuously. Specifically, if the current filter coefficient continues to change and the current input signal EDGE transitions (i.e., EDGE & & coff changed), the state machine transitions from the OUTPUT state to the EDGE state; if the current filter coefficients continue to change and NO EDGE transitions (i.e., NO EDGE & & coff changed) of the current input signal occur, the state machine transitions from the OUTPUT state to the NO EDGE state.
In a second aspect of the embodiments of the present invention, a signal processing chip is provided, including: a comparator circuit configured to receive the written value and the current stored value of the filter coefficient, compare the two values, and output a comparison result; an edge detector circuit configured to receive an input signal, determine whether an edge transition occurs, and output a determination result; a state machine circuit connected to outputs of the comparator circuit and the edge detector circuit, respectively, and configured to confirm whether or not to output a signal containing a written value of the filter coefficient based on the comparison result and the judgment result; and the counter circuit is respectively connected with the output of the state machine circuit and the output of the edge detector circuit, and is configured to confirm whether to count based on the written value of the filter coefficient according to the signal input by the state machine circuit and the judgment result input by the edge detector circuit and correspondingly output a control signal for sampling the input signal.
In a third aspect of the embodiments of the present invention, a signal processing method is provided. Fig. 4 is a flowchart of a signal processing method according to an embodiment of the present invention. As shown in fig. 4, a signal processing method provided by an embodiment of the present invention includes:
s1, comparing a received written value of a filter coefficient with a current stored value through a comparator, and outputting a comparison result to a state machine;
s2, judging whether the received input signal generates edge jump or not through an edge detector, and outputting a judging result to the state machine;
s3, the state machine confirms whether to output a signal containing the written value of the filter coefficient to a counter according to the received comparison result and the received judgment result;
s4, receiving signals input by the state machine through the counter, confirming whether to count based on the written value of the filter coefficient based on the judging result input by the edge detector, and correspondingly outputting control signals for sampling the input signals.
In a fourth aspect of the embodiment of the present invention, a signal processing apparatus is provided, and fig. 5 is a schematic structural diagram of a signal processing apparatus provided in the embodiment of the present invention. As shown in fig. 5, a signal processing device provided by an embodiment of the present invention includes the following modules: at least one processor 021; and a memory 022, the memory 022 storing computer instructions 023 executable on the processor 021, the computer instructions 023 implementing the steps of the method as described above when executed by the processor 021.
The invention also provides a computer readable storage medium. Fig. 6 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention. As shown in fig. 6, the computer-readable storage medium 031 stores a computer program 032 which, when executed by a processor, performs the steps of the method as described above.
Finally, it should be noted that, as will be understood by those skilled in the art, implementing all or part of the above-described methods in the embodiments may be implemented by a computer program to instruct related hardware, and the program of the method for setting system parameters may be stored in a computer readable storage medium, where the program may include the flow of the embodiments of the methods described above when executed. The storage medium of the program may be a magnetic disk, an optical disk, a read-only memory (ROM), a random-access memory (RAM), or the like. The computer program embodiments described above may achieve the same or similar effects as any of the method embodiments described above.
Furthermore, the method disclosed according to the embodiment of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. The above-described functions defined in the methods disclosed in the embodiments of the present invention are performed when the computer program is executed by a processor.
Furthermore, the above-described method steps and system units may also be implemented using a controller and a computer-readable storage medium storing a computer program for causing the controller to implement the above-described steps or unit functions.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general purpose or special purpose computer or general purpose or special purpose processor. Further, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DOL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The foregoing embodiment of the present invention has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, and the program may be stored in a computer readable storage medium, where the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the invention, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the invention, and many other variations of the different aspects of the embodiments of the invention as described above exist, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present invention.
Claims (21)
1. A signal processing apparatus, comprising:
a comparator configured to receive the written value and the current stored value of the filter coefficient, compare the two values, and output a comparison result;
an edge detector configured to receive an input signal, determine whether an edge transition occurs, and output a determination result;
the state machine is respectively connected with the output ends of the comparator and the edge detector and is configured to confirm whether to output a signal containing the written value of the filter coefficient according to the comparison result and the judging result;
And the counter is respectively connected with the output end of the state machine and the output end of the edge detector, and is configured to confirm whether to count based on the written value of the filter coefficient according to the signal input by the state machine and the judgment result input by the edge detector and correspondingly output a control signal for sampling the input signal.
2. The apparatus as recited in claim 1, further comprising:
and the selector is connected with the output end of the counter and is configured to sample the input signal according to the control signal and output a sampling result.
3. The apparatus of claim 1, wherein the comparator is further configured to:
and outputting a first comparison result in response to the received written value of the filter coefficient being the same as the current stored value.
4. The apparatus of claim 3, wherein the comparator is further configured to:
and outputting a second comparison result in response to the received written value of the filter coefficient being different from the current stored value.
5. The apparatus of claim 4, wherein the edge detector is further configured to:
and outputting a first judgment result in response to the received input signal that the edge jump does not occur.
6. The apparatus of claim 5, wherein the edge detector is further configured to:
and responding to the received input signal to generate edge jump, and outputting a second judgment result.
7. The apparatus of claim 6, wherein the state machine is further configured to:
and skipping to a corresponding state according to the comparison result and the judging result and confirming whether to output a signal containing the written value of the filter coefficient or not based on the corresponding state.
8. The apparatus of claim 7, wherein the state machine is further configured to:
in response to receiving the first comparison result and the first determination result, in an initial state and based on the initial state, a signal containing a written value of the filter coefficient is not output.
9. The apparatus of claim 8, wherein the state machine is further configured to:
in response to receiving the second comparison result and the second judgment result, jumping from the initial state to a signal edge jumping state;
judging whether the written value of the filter coefficient is valid or not based on the signal edge jump state;
And confirming whether to jump from the signal edge jump state to the output state according to the result of judging whether the written value of the filter coefficient is valid or not, and outputting a signal containing the written value of the filter coefficient.
10. The apparatus of claim 9, wherein the state machine is further configured to:
and in response to the written value of the filter coefficient being valid, jumping from the signal edge jumping state to the output state outputs a signal containing the written value of the filter coefficient.
11. The apparatus of claim 9, wherein the state machine is further configured to:
and in response to the written value of the filter coefficient being invalid, jumping from the signal edge jumping state to the initial state.
12. The apparatus of claim 8, wherein the state machine is further configured to:
in response to receiving the second comparison result and the first judgment result, jumping from the initial state to a signal edge non-jumping state;
judging whether the second judging result is received or not and whether the written value of the filter coefficient is valid or not based on the signal edge non-jump state;
And confirming whether the signal edge is jumped to an output state from the state that the signal edge is not jumped to output the signal containing the written value of the filter coefficient according to the second judgment result and the result of judging whether the written value of the filter coefficient is valid.
13. The apparatus of claim 12, wherein the state machine is further configured to:
and in response to receiving the second judgment result and the written value of the filter coefficient is valid, jumping from the signal edge non-jumping state to an output state outputs a signal containing the written value of the filter coefficient.
14. The apparatus of claim 12, wherein the state machine is further configured to:
and in response to receiving the second judgment result and the written value of the filter coefficient being invalid, jumping from the signal edge jumping state to the initial state.
15. The apparatus of claim 12, wherein the state machine is further configured to:
and responding to the fact that the second judging result is not received, and waiting for receiving the second judging result in the state that the signal edge is not jumped.
16. The apparatus according to any one of claims 1-15, further comprising:
And the first register is connected with the input end of the comparator and is configured to store the current stored value of the filter coefficient and output the current stored value to the comparator.
17. The apparatus as recited in claim 16, further comprising:
and the second register is connected with the input end of the edge detector and is configured for storing the current value of the received input signal, outputting the current value to the edge detector and outputting the current value to the selector.
18. The apparatus as recited in claim 17, further comprising:
and the third register is connected with the output end of the second register, is configured to store the previous value of the input signal and outputs the previous value to the selector.
19. A signal processing chip, comprising:
a comparator circuit configured to receive the written value and the current stored value of the filter coefficient, compare the two values, and output a comparison result;
an edge detector circuit configured to receive an input signal, determine whether an edge transition occurs, and output a determination result;
a state machine circuit connected to outputs of the comparator circuit and the edge detector circuit, respectively, and configured to confirm whether or not to output a signal containing a write value of the filter coefficient based on the comparison result and the determination result;
And the counter circuit is respectively connected with the output of the state machine circuit and the output of the edge detector circuit, and is configured to confirm whether to count based on the written value of the filter coefficient according to the signal input by the state machine circuit and the judgment result input by the edge detector circuit and correspondingly output a control signal for sampling the input signal.
20. A signal processing method, comprising:
comparing the received written value of the filter coefficient with the current stored value through a comparator, and outputting a comparison result to a state machine;
judging whether the received input signal generates edge jump or not through an edge detector, and outputting a judging result to the state machine;
the state machine confirms whether to output a signal containing the written value of the filter coefficient to a counter according to the received comparison result and the judgment result;
and receiving signals input by the state machine through the counter, confirming whether to count based on the written value of the filter coefficient based on the judging result input by the edge detector, and correspondingly outputting a control signal for sampling the input signals.
21. A signal processing apparatus, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, the memory performing the method of claim 20 when the instructions are executed.
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| KR100188692B1 (en) * | 1996-01-20 | 1999-06-01 | 윤종용 | Digital filter |
| US6738441B1 (en) * | 2000-07-05 | 2004-05-18 | Schneider Automation Inc. | Method and device for filtering input signals |
| JP2002229968A (en) * | 2001-02-01 | 2002-08-16 | Sony Corp | Signal conditioning device |
| JP4701962B2 (en) * | 2005-09-27 | 2011-06-15 | ヤマハ株式会社 | Regression sound removal device |
| JP4742226B2 (en) * | 2005-09-28 | 2011-08-10 | 国立大学法人九州大学 | Active silencing control apparatus and method |
| GB2499080B (en) * | 2012-12-04 | 2014-12-31 | Broadcom Corp | Method and apparatus for adjusting layer 3 filter coefficients |
| US9178545B2 (en) * | 2013-04-11 | 2015-11-03 | Stmicroelectronics Asia Pacific Pte Ltd | Digital IIR filter with adjustable filter weights based on measured changes in the processed data |
| CN103631161A (en) * | 2013-09-17 | 2014-03-12 | 北京理工大学 | Filtering method based on state machine |
| US10270428B1 (en) * | 2018-01-22 | 2019-04-23 | Allegro Microsystems, Llc | Filter circuit with dynamic parameter generation |
| CN208768080U (en) * | 2018-06-27 | 2019-04-19 | 珠海市一微半导体有限公司 | A kind of BMC code self-adapting decoding system |
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