CN116131766A - Frequency hopping phase continuous frequency synthesizer and control method thereof - Google Patents
Frequency hopping phase continuous frequency synthesizer and control method thereof Download PDFInfo
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- CN116131766A CN116131766A CN202211596034.2A CN202211596034A CN116131766A CN 116131766 A CN116131766 A CN 116131766A CN 202211596034 A CN202211596034 A CN 202211596034A CN 116131766 A CN116131766 A CN 116131766A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention discloses a frequency hopping phase continuous frequency synthesizer, which comprises a constant-temperature crystal oscillator, a power divider, a clock distributor, a comb spectrum generator, an FPGA, a duplexer, a first filter, a DDS, an M-path S-band switch filter bank, a second filter, a first amplifier, a mixer, an N-path S-band switch filter bank, a second amplifier, a frequency doubler, a third filter and a third amplifier. The frequency synthesizer adopts a brand new frequency standard frequency, intermediate frequency and control logic calculation method, so that the problem of frequency hopping phase continuity of the DDS output frequency is solved, and the problem of small stepping hopping phase continuity of the frequency synthesizer is solved. The frequency synthesizer has the advantages of low noise and large step jump of direct analog frequency synthesis technology, and has the characteristics of small step jump of direct digital frequency synthesis technology.
Description
Technical Field
The invention relates to the technical field of radio frequency electronics, in particular to a frequency hopping phase continuous frequency synthesizer and a control method thereof.
Background
The frequency synthesis technology is various and can be classified into direct frequency synthesis and indirect frequency synthesis. Direct frequency synthesis techniques include direct analog and direct digital frequency synthesis techniques. At present, a frequency synthesizer realized by adopting indirect frequency synthesis modes such as a phase-locked loop and the like cannot realize high-speed frequency hopping, and cannot realize phase continuity after frequency hopping; the direct analog frequency synthesizer realized by the operations of adding, subtracting, multiplying and the like of the reference frequency can realize the phase continuity after frequency hopping, but the frequency hopping stepping frequency realized by the method is generally an integer multiple of the reference frequency, the frequency hopping of small steps cannot be realized, the product is large in size and high in power consumption, and the current requirement on the frequency synthesizer cannot be met.
The invention provides a frequency hopping phase continuous frequency synthesizer with continuous phase after small step frequency hopping and a control method thereof.
Disclosure of Invention
The invention provides a frequency hopping phase continuous frequency synthesizer with continuous phase after small step frequency hopping and a control method thereof.
The invention aims to provide a frequency hopping phase continuous frequency synthesizer, which comprises a constant-temperature crystal oscillator, a power divider, a clock divider, a comb spectrum generator, an FPGA, a duplexer, a first filter, a DDS, an M-path S-band switch filter bank, a second filter, a first amplifier, a mixer, an N-path S-band switch filter bank, a second amplifier, a frequency doubler, a third filter and a third amplifier, wherein the output port of the constant-temperature crystal oscillator is connected with the input port of the power divider, the two output ports of the power divider are respectively connected with the input ports of the comb spectrum generator and the clock divider, the output port of the clock divider is connected with the clock input port of the FPGA, the I/0 port of the FPGA is respectively connected with the D0-DN and the I0/UPDATA ports of the DDS, the output port of the comb spectrum generator is connected with the input public port of the duplexer, the output port H port of the duplexer is connected with the input port of the first filter, the output port L port of the duplexer is connected with the radio frequency input port of the M-path S-band switch filter bank, the multi-path I0 port of the FPGA is connected with the logic control input end of the M-path S-band switch filter bank, the radio frequency output end of the M-path S-band switch filter bank is connected with the first amplifier, the output port of the first amplifier is connected with the local oscillation input port of the mixer, the output port of the DDS is connected with the input port of the second filter, the output port of the second filter is connected with the intermediate frequency input port of the mixer, the radio frequency output port of the mixer is connected with the radio frequency input end of the N-path S-band switch filter bank, the radio frequency output port of the N-path S-band switch filter bank is connected with the input port of the second amplifier, the output port of the second amplifier is connected with the input port of the frequency doubling device, the output port of the frequency doubler is connected with the input port of the third filter, and the output port of the third filter is connected with the input port of the third amplifier.
Further, the high-stability clock generated by the constant temperature crystal oscillator provides an overall high-stability system clock f1.
Further, the comb spectrum generator generates a comb spectrum signal with a frequency interval f1, and the constant temperature crystal oscillator provides a system running clock clk for the FPGA through the clock distributor.
Further, the FPGA controls the frequency, phase and amplitude of the DDS.
Further, the first filter extracts a reference clock REF-CLK required by the DDS in the comb spectrum generation signal, and provides a high-frequency clock reference signal for the DDS.
Furthermore, the M-path S-band switch filter bank generates M S-band marks, and the FPGA carries out selective output on M S-band frequency mark signals.
Further, the first amplifier amplifies the M frequency standard signals generated by the filtering, and provides a local oscillation driving signal for the mixer.
Further, under the control of the FPGA, the DDS generates intermediate frequency signals with the step delta f/2MHz, the second filter filters out the intermediate frequency signals generated by the DDS in an out-of-band spurious mode, and the second filter provides intermediate frequency signals for frequency mixing.
Further, the mixer mixes the input local oscillation signal with the intermediate frequency signal and generates an S-band radio frequency signal with the stepping frequency of Deltaf/2 MHz, the N paths of S-band switch filter banks filter out non-required inter-modulation signals under the control of the FPGA, the second amplifier amplifies the S-band signal generated by the sectional filtering, the second amplifier multiplies the input S-band signal fx with the stepping frequency of Deltaf/2 MHz, the third filter filters out fundamental frequencies fx, 3fx, 4fx and the like output by the second amplifier to obtain a C-band signal with the stepping frequency of DeltafMHz, and the third amplifier amplifies the required C-band signal to required power.
A control method of a frequency hopping phase continuous frequency synthesizer is applied to the frequency hopping phase continuous frequency synthesizer, and comprises the following steps:
the clock (clk) distributed by the clock distributor acts as the system clock for the FPGA. clk is used as a detection control clock for issuing DDS frequency control words and phase control words (D0 … DN), and detecting the health state of the frequency synthesizer. And performing K frequency division processing on the clk clock in the FPGA to obtain a SYCN_FPGA signal, wherein the frequency of the SYCN_FPGA signal is the greatest common divisor of the DDS output signal of 2.5MHz, the intermediate frequency output frequency and the DDS system working clock.
F_en is an external frequency control latch signal, and F0 … FN is a frequency control signal for the frequency synthesizer. When the external control signal is issued to the frequency synthesizer, after the F_EN instruction arrives, the frequency synthesizer carries out latch decoding on the external frequency control instruction, and the frequency word and the phase control word of the DDS are issued to the DDS in synchronization with clk, and the IO/UPDATA is issued to the DDS and the switch driver in synchronization with SYCN_FPGA signals.
The invention has the following advantages: the frequency synthesizer adopts a new logic control clock calculation method, realizes the frequency hopping phase continuity of the DDS output frequency, and solves the problem of the small stepping hopping phase continuity of the frequency synthesizer. The frequency synthesizer has the advantages of low noise and large step jump of direct analog frequency synthesis technology, and has the characteristics of small step jump of direct digital frequency synthesis technology. In addition, by modifying the number of the frequency switch filters of the switch filter bank, the frequency synthesis with larger bandwidth can be realized, and the method has strong expansibility. Meanwhile, in the frequency synthesizer provided by the patent, DDS replaces a large number of switch filter sets, and the power consumption and the volume of the product can be greatly reduced.
Drawings
FIG. 1 is a schematic block diagram of the present invention;
fig. 2 is a control schematic block diagram of the present invention.
In the figure: 1. constant temperature crystal oscillator; 2. a power divider; 3. a clock distributor; 4. a comb spectrum generator; 5. an FPGA; 6. a diplexer; 7. a first filter; 8. DDS; 9. m-path S-band switch filter bank; 10. a first amplifier; 11. a second filter; 12. a mixer; 13. n-path S-band switch filter bank; 14. a second amplifier; 15. a frequency doubler; 16. a third filter; 17. and a third amplifier.
Detailed Description
The invention provides a frequency hopping phase continuous frequency synthesizer, which comprises a constant temperature crystal oscillator 1, a power divider 2, a clock distributor 3, a comb spectrum generator 4, an FPGA5, a duplexer 6, a first filter 7, a DDS8, an M-path S-band switch filter 9 group, a second filter 11, a first amplifier 10, a mixer 12, an N-path S-band switch filter group 13, a second amplifier 14, a frequency doubler 15, a third filter 16 and a third amplifier 17, wherein the output port of the constant temperature crystal oscillator 1 is connected with the input port of the power divider 2, the two output ports of the power divider 2 are respectively connected with the input ports of the comb spectrum generator 4 and the clock distributor 3, the output port of the clock distributor 3 is connected with the clock input port of the FPGA5, the I/0 port of the FPGA5 is respectively connected with the D0-DN and I0/UPDATA ports of the DDS8, the output port of the comb spectrum generator 4 is connected with the input public port of the duplexer 6, the output port H port of the duplexer 6 is connected with the input port of the first filter 7, the output port L port of the duplexer 6 is connected with the radio frequency input port of the M-path S-band switch filter bank 9, the multi-path I0 port of the FPGA5 is connected with the logic control input end of the M-path S-band switch filter bank 9, the radio frequency output end of the M-path S-band switch filter bank 9 is connected with the first amplifier 10, the output port of the first amplifier 10 is connected with the local oscillator input port of the mixer 12, the output port of the DDS8 is connected with the input port of the second filter 11, the output port of the second filter 11 is connected with the intermediate frequency input port of the mixer 12, the radio frequency output port of the mixer 12 is connected with the radio frequency input end of the N-path S-band switch filter bank 13, the radio frequency output port of the N-way S-band switch filter bank 13 is connected to the input port of the second amplifier 14, the input port of the second amplifier 14 is connected to the input port of the frequency doubler 15, the output port of the frequency doubler 15 is connected to the input port of the first filter, and the output port of the third filter 16 is connected to the input port of the third amplifier 17.
In this embodiment, the high-stability clock generated by the constant temperature crystal oscillator 1 provides the overall high-stability system clock f1.
In this embodiment, the comb spectrum generator generates a comb spectrum signal with a frequency interval f1, and the oven controlled crystal oscillator 1 provides a system running clock clk for the FPGA through the clock distributor.
In this embodiment, the FPGA5 controls the frequency, phase and amplitude of the DDS 8.
In this embodiment, the first filter 7 extracts the reference clock REF-CLK required for the DDS8 in the comb spectrum generation signal, and provides the DDS8 with a high frequency clock reference signal.
In this embodiment, the M-channel S-band switch filter bank 9 generates M S-band labels, and the FPGA5 selects and outputs M S-band frequency label signals.
In this embodiment, the first amplifier 10 amplifies M frequency scale signals generated by filtering and provides a local oscillation driving signal to the mixer 12.
In this embodiment, the DDS8 generates an intermediate frequency signal stepped to Δf/2MHz under the control of the FPGA5, the second filter 11 filters out-of-band spurious signals generated by the DDS8, and the second filter 11 provides the intermediate frequency signal for mixing.
In this embodiment, the mixer 12 mixes the input local oscillator signal with the intermediate frequency signal and generates an S-band radio frequency signal with a step frequency of Δf/2MHz, the N-channel S-band switch filter bank 13 filters out the unwanted intermodulation signal under the control of the FPGA5, the second amplifier 14 amplifies the S-band signal generated by the step filtering, the second multiplier 15 multiplies the input S-band signal fx with a step of Δf/2MHz, the third filter 16 filters out fundamental frequencies fx, 3fx, 4fx and the like output by the second multiplier 15 to obtain a C-band signal with a step of Δfmhz, and the third amplifier 17 amplifies the required C-band signal to a required power.
The invention also provides a control method of the frequency hopping phase continuous frequency synthesizer, which is applied to the frequency hopping phase continuous frequency synthesizer and comprises the following steps:
the clock (clk) distributed by the clock distributor acts as the system clock for the FPGA. clk is used as a detection control clock for issuing DDS frequency, phase and amplitude control words (D0 … DN), and detecting the health state of the frequency synthesizer. And performing K frequency division processing on the clk clock in the FPGA to obtain a SYCN_FPGA signal, and taking the greatest common divisor of the SYCN_FPGA signal frequency of delta f/2, the DDS output intermediate frequency and the DDS system working clock.
F_en is an external frequency control latch signal, and F0 … FN is an external frequency control signal for the frequency synthesizer. When an external control signal is issued to the frequency synthesizer, the frequency synthesizer decodes the external frequency control instruction, synchronizes the frequency, the phase and the amplitude control word of the DDS to the DDS in clk, and after the F_EN instruction arrives, the IO/UPDATA is issued to the DDS in synchronization with the SYCN_FPGA signal, and simultaneously, the N-path S-band switch filter group and the M-path S-band switch filter group switch control signals are issued in synchronization with the SYCN_FPGA to realize frequency selection.
Although specific embodiments of the invention have been described in detail with reference to the accompanying drawings, it should not be construed as limiting the scope of protection of the present patent. Various modifications and variations which may be made by those skilled in the art without the creative effort are within the scope of the patent described in the claims.
Claims (10)
1. The utility model provides a frequency hopping phase continuous frequency synthesizer, includes constant temperature crystal oscillator, merit divides ware, clock distributor, comb spectrum generator, FPGA, duplexer, first wave filter, DDS, M way S wave band switch filter bank, second wave filter, first amplifier, mixer, N way S wave band switch filter bank, second amplifier, frequency doubler, third wave filter, third amplifier, its characterized in that: the output port of the constant temperature crystal oscillator is connected with the input port of the power divider, the two output ports of the power divider are respectively connected to the comb spectrum generator and the input port of the clock distributor, the output port of the clock distributor is connected with the clock input port of the FPGA, the I/0 port of the FPGA is respectively connected with the D0-DN and I0/UPDATA ports of the DDS, the output port of the comb spectrum generator is connected with the input common port of the duplexer, the output port H port of the duplexer is connected with the input port of the first filter, the output port L port of the duplexer is connected with the radio frequency input port of the M-way S-band switch filter bank, the multipath I0 port of the FPGA is connected with the logic control input end of the M-way S-band switch filter bank, the output port of the first amplifier is connected with the local oscillator input port of the mixer, the output port of the DDS is connected with the input port of the second filter, the output port of the intermediate frequency filter is connected with the output port of the mixer, the output port of the second filter is connected with the frequency multiplier-S input port of the second filter, the output port of the frequency multiplier-S is connected with the output port of the third filter, the frequency multiplier-S is connected with the output port of the third filter.
2. A frequency hopping phase continuous frequency synthesizer as claimed in claim 1, wherein: the high-stability clock generated by the constant-temperature crystal oscillator provides an integral high-stability system clock f1.
3. A frequency hopping phase continuous frequency synthesizer as claimed in claim 1, wherein: the comb spectrum generator generates a comb spectrum signal with a frequency interval f1, and the constant-temperature crystal oscillator provides a system running clock clk for the FPGA through a clock distributor.
4. A frequency hopping phase continuous frequency synthesizer as claimed in claim 1, wherein: the FPGA controls the frequency, the phase and the amplitude of the DDS.
5. A frequency hopping phase continuous frequency synthesizer as claimed in claim 1, wherein: the first filter extracts a reference clock REF-CLK required by the DDS in the comb spectrum generation signal, and provides a high-frequency clock reference signal for the DDS.
6. A frequency hopping phase continuous frequency synthesizer as claimed in claim 1, wherein: the M paths of S wave band switch filter groups generate M S wave band marks, and the FPGA carries out selective output on M S wave band frequency mark signals.
7. A frequency hopping phase continuous frequency synthesizer as claimed in claim 1, wherein: the first amplifier amplifies M frequency standard signals generated by filtering and provides local oscillation driving signals for the mixer.
8. The frequency hopping phase continuous frequency synthesizer of claim, wherein: under the control of the FPGA, the DDS generates intermediate frequency signals with the step delta f/2MHz, the second filter filters out-of-band spurious signals of the intermediate frequency signals generated by the DDS, and the second filter provides intermediate frequency signals for mixing.
9. A frequency hopping phase continuous frequency synthesizer as claimed in claim 1, wherein: the mixer mixes an input local oscillator signal with an intermediate frequency signal and generates an S-band radio frequency signal with a stepping frequency of delta f/2MHz, the N paths of S-band filter banks filter out non-required inter-modulation signals under the control of the FPGA, the second amplifier amplifies the S-band signal generated by the segmented filtering, the second frequency multiplier multiplies the input S-band signal fx with the stepping frequency of delta f/2MHz, the third filter filters out fundamental frequencies fx, 3fx, 4fx and the like output by the second frequency multiplier to obtain C-band signals with the stepping frequency of delta fMHz, and the third amplifier amplifies the required C-band signals to required power.
10. A control method of a frequency hopping phase continuous frequency synthesizer, which is applied to a frequency hopping phase continuous frequency synthesizer in claim 1, and comprises the following steps:
the clock (clk) distributed by the clock distributor acts as the system clock for the FPGA. clk is used as a detection control clock for issuing DDS frequency, phase and amplitude control words (D0 … DN), and detecting the health state of the frequency synthesizer. And performing K frequency division processing on the clk clock in the FPGA to obtain a SYCN_FPGA signal, and taking the greatest common divisor of the SYCN_FPGA signal frequency of delta f/2, the DDS output intermediate frequency and the DDS system working clock.
F_en is an external frequency control latch signal, and F0 … FN is an external frequency control signal for the frequency synthesizer. When an external control signal is issued to the frequency synthesizer, the frequency synthesizer decodes the external frequency control instruction, synchronizes the frequency, the phase and the amplitude control word of the DDS to the DDS in clk, and after the F_EN instruction arrives, the IO/UPDATA is issued to the DDS in synchronization with the SYCN_FPGA signal, and simultaneously, the N-path S-band switch filter group and the M-path S-band switch filter group switch control signals are issued in synchronization with the SYCN_FPGA to realize frequency selection.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211596034.2A CN116131766A (en) | 2022-12-13 | 2022-12-13 | Frequency hopping phase continuous frequency synthesizer and control method thereof |
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| CN202211596034.2A CN116131766A (en) | 2022-12-13 | 2022-12-13 | Frequency hopping phase continuous frequency synthesizer and control method thereof |
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| CN116131766A true CN116131766A (en) | 2023-05-16 |
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| CN202211596034.2A Pending CN116131766A (en) | 2022-12-13 | 2022-12-13 | Frequency hopping phase continuous frequency synthesizer and control method thereof |
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