CN116130421A - Manufacturing method of electrostatic discharge protection device based on BCD platform and electronic device - Google Patents

Manufacturing method of electrostatic discharge protection device based on BCD platform and electronic device Download PDF

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Publication number
CN116130421A
CN116130421A CN202211709954.0A CN202211709954A CN116130421A CN 116130421 A CN116130421 A CN 116130421A CN 202211709954 A CN202211709954 A CN 202211709954A CN 116130421 A CN116130421 A CN 116130421A
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region
well region
type
electrostatic discharge
doping
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陈芳
曹亚历
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Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
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Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type

Abstract

The invention provides a manufacturing method of an electrostatic discharge protection device based on a BCD platform and an electronic device. The method includes providing a semiconductor substrate; forming a well region with a first doping type in a semiconductor substrate; forming a gate electrode on a surface of the semiconductor substrate over the well region; forming a source region and a drain region with a second doping type in the well regions at two sides of the grid respectively; after forming the well region, an ion doping process is performed on the well region to reduce the resistance of the well region. The manufacturing method is compatible with the BCD process, the ion doping process of the well region in the BCD process is fully utilized to improve the electrostatic discharge performance, and no additional mask and process steps of a BCD platform are needed.

Description

Manufacturing method of electrostatic discharge protection device based on BCD platform and electronic device
Technical Field
The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular, to a BCD platform-based method for manufacturing an electrostatic discharge protection device and an electronic apparatus.
Background
Grounded Gate NMOS (GGNMOS) is a common electrostatic discharge (ESD) protection device. The drain terminal is connected to the I/O PAD, the gate terminal is connected to the power ground, and the ESD utilizes an NPN triode parasitic by the GGNMOS to form a low-impedance discharge path so as to protect the internal circuit of the IC. The design window of ESD is shown in fig. 1, where the turn-on voltage Vt1 is less than the breakdown voltage BV (breakdown voltage) of the protected device, so as to ensure that when an ESD event occurs, the ESD device can be turned on and off rapidly with a high ESD current in preference to the protected device, thereby protecting the device. The sustain voltage Vh > the operating voltage Vop to prevent Latch-up Risk (Latch-up Risk). The larger the secondary breakdown current It2, the better the ESD performance. When ESD stress is generated at the drain, the drain voltage rises with the drain-substrate junction being reversed biased. When the reverse bias voltage increases to a certain extent, avalanche breakdown occurs, and then the generated holes drift to the substrate electrode position, forming a large hole current. Since the substrate doping is not very high, this hole current will cause a voltage drop across the substrate, biasing the source-substrate junction forward. When the emitter-base (source-substrate) voltage exceeds 0.6V, the parasitic transistor turns on, creating a new, stronger path to drain current. More importantly, such a smaller electric field is sufficient to maintain the same avalanche hole generation rate and emitter-base voltage due to the increased current flowing through the drain high field region. Thus, the drain voltage drops with increasing current, resulting in a current-voltage hysteresis (snapback) characteristic.
In a high-voltage Bipolar-complementary metal oxide semiconductor-double-diffused metal oxide semiconductor (BCD, bipolarcmos-DMOS) platform, in order to raise the device withstand voltage, the concentration of the lower end of well ion implantation is usually lower, the well resistance Rwell is larger, so that in an ESD GGNMOS parasitic NPN (drain n+/body PW/source n+), vt1 is larger, vh is lower, it2 is lower, latch-up risk occurs when Vh is lower than Vop, and ESD performance is poor.
The related art generally adopts an increase of the channel length to solve the problem of lower Vh, and because of the increase of the base area, vh is increased, but this increases the original design area and changes the structure of the original device. In addition, it2 is reduced by increasing the overall width, however, the method also increases the original design area and changes the structure of the original device. How to improve ESD performance without changing the original device structure and without increasing process costs is a challenge.
Therefore, there is a need to design a method for manufacturing an electrostatic discharge protection device based on BCD platform and an electronic device.
Disclosure of Invention
In the summary, a series of concepts in a simplified form are introduced, which will be further described in detail in the detailed description. The summary of the invention is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The invention provides a manufacturing method of an electrostatic discharge protection device based on a BCD platform, which comprises the following steps: providing a semiconductor substrate; forming a well region with a first doping type in a semiconductor substrate; forming a gate electrode on a surface of the semiconductor substrate over the well region; forming a source region and a drain region with a second doping type in the well regions at two sides of the grid respectively; after forming the well region, an ion doping process is performed on the well region to reduce the resistance of the well region.
The invention also provides a manufacturing method of the electrostatic discharge protection device based on the BCD platform, which comprises the following steps: providing a semiconductor substrate; forming a well region with a first doping type in a semiconductor substrate; forming a gate electrode on a surface of the semiconductor substrate over the well region; forming a source region and a drain region with a second doping type in the well regions at two sides of the grid respectively; after forming the well region, an ion doping process is performed on the well region below the drain region to increase the doping concentration of the well region.
Optionally, the width of the ion doping process is smaller than the width of the drain region.
Optionally, the ion doping process is a first doping type doping process.
Optionally, the ion doping process comprises a body region doping process.
Optionally, the doping depth of the ion doping process is greater than the depth of the well region to form an integral region below the well region, or the doping depth is less than the depth of the well region to form an integral region within the well region.
Optionally, the electrostatic discharge protection device comprises a GGNMOS device.
Optionally, the first doping type is P-type and the second doping type is N-type.
An electrostatic discharge protection device is manufactured by the manufacturing method of the electrostatic discharge protection device.
An electronic device comprises the electrostatic discharge protection device.
Compared with the traditional manufacturing method, the manufacturing method is compatible with the BCD process, no extra mask or process step is needed, the starting voltage Vt1 is reduced by reducing the resistance of a trap, the design redundancy is increased, the maintenance voltage Vh is increased, the latch-up risk is reduced, the secondary breakdown current It2 is increased, the ESD performance is improved, meanwhile, the design area is not increased, and the device model (spice model) is unchanged and the process cost is not increased because the size and the structure of the device are not changed.
Drawings
The following drawings are included to provide an understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and their description to explain the principles of the invention.
In the accompanying drawings:
FIG. 1 shows a schematic diagram of an ESD design window;
FIG. 2 shows a schematic diagram of an electrostatic discharge protection device;
fig. 3 illustrates a method of manufacturing a BCD platform based electrostatic discharge protection device in accordance with an embodiment of the present invention;
fig. 4 illustrates a method of manufacturing an electrostatic discharge protection device based on a BCD platform in accordance with another embodiment of the present invention;
FIG. 5 shows a schematic diagram of an electrostatic discharge protection device in accordance with an embodiment of the present invention;
FIG. 6 shows a schematic diagram of an electrostatic discharge protection device in accordance with an embodiment of the present invention;
fig. 7 shows an equivalent circuit diagram of a GGNMOS device for ESD protection according to one embodiment of the present invention;
fig. 8 shows a comparison of junction breakdown voltages before and after increasing the P-type body region in accordance with one embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without one or more of these details. In other instances, well-known features have not been described in detail in order to avoid obscuring the invention.
It should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In the following description, for the purpose of providing a thorough understanding of the present invention, detailed structures and steps are presented in order to illustrate the technical solution presented by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.
As shown in fig. 2, in a GGNMOS device for ESD protection, in a high voltage BCD stage, in order to raise the device withstand voltage, the concentration of the lower end of well ion implantation is usually lighter, and the well resistance Rwell is larger. Resulting in an ESD GGNMOS parasitic NPN (drain n+/bulk PW/source n+):
the turn-on voltage Vt1 is larger, close to the breakdown voltage BV;
the sustain voltage Vh is low, and when Vh is lower than the operating voltage Vop, latch-up risk occurs;
the secondary breakdown current It2 is low and ESD performance is poor.
In order to solve the above-mentioned problems, a method for manufacturing an electrostatic discharge protection device is proposed, in order to directly manufacture the electrostatic discharge protection device on a BCD platform without increasing a process flow, in particular without increasing a mask.
Example 1
A method for manufacturing an electrostatic discharge protection device based on a BCD platform, as shown in fig. 3, includes the following steps:
s1, providing a semiconductor substrate. Wherein the semiconductor substrate may be at least one of the following mentioned materials: si, ge, siGe, siC, siGeC, inAs, gaAs, inP or other III/V compound semiconductors, and also include multilayer structures of these semiconductors or are silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), and the like. By way of example, in one embodiment, the semiconductor substrate is formed from monocrystalline silicon. In one embodiment, the semiconductor substrate may be a doped silicon substrate. In one embodiment, the semiconductor substrate may be a P-type silicon substrate.
S2, forming a well region with a first doping type in the semiconductor substrate. May be formed by epitaxial growth or ion implantation, and is not limited herein. Such as PVD, CVD, ALD. As an example, in one embodiment, the well region is formed by ion implantation. The first doping type may be N-type or P-type. By way of example, in one embodiment, the well region is a P-type well region.
S3, forming a grid electrode on the surface of the semiconductor substrate above the well region. The gate may be a polysilicon gate or a metal gate, or any other suitable material known to those skilled in the art. In this embodiment, a polysilicon gate is exemplified.
S4, forming a source region and a drain region with a second doping type in the well regions at two sides of the grid respectively. The second doping type may be P-type or N-type. By way of example, in one embodiment, the source and drain regions are both N-type doped.
S5, after the well region is formed, an ion doping process is carried out on the well region so as to reduce the resistance of the well region. The ion doping process is illustratively an ion implantation process.
In one embodiment, the ion doping process is a first doping type doping process.
In one embodiment, the ion doping process includes a body region doping process.
In one embodiment, the doping depth of the ion doping process is greater than the depth of the well region to form an integral region beneath the well region. By way of example, in one embodiment, the body region is P-type, consistent with the doping type of the well region.
In one embodiment, the width of the body region coincides with the width of the well region. In one embodiment, the width of the body region may also be slightly narrower than the width of the well region, but the width of the body region is greater than the width of the drain region.
Example two
A method for manufacturing an electrostatic discharge protection device based on a BCD platform, as shown in fig. 4, includes the following steps:
s1', providing a semiconductor substrate. Wherein the semiconductor substrate may be at least one of the following mentioned materials: si, ge, siGe, siC, siGeC, inAs, gaAs, inP or other III/V compound semiconductors, and also include multilayer structures of these semiconductors or are silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), and the like. By way of example, in one embodiment, the semiconductor substrate is formed from monocrystalline silicon. In one embodiment, the semiconductor substrate may be a doped silicon substrate. In one embodiment, the semiconductor substrate may be a P-type silicon substrate.
S2', forming a well region with a first doping type in the semiconductor substrate. May be formed by epitaxial growth or ion implantation, and is not limited herein. Such as PVD, CVD, ALD. As an example, in one embodiment, the well region is formed by ion implantation. The first doping type may be N-type or P-type. By way of example, in one embodiment, the well region is a P-type well region.
And S3', forming a gate on the surface of the semiconductor substrate above the well region. The gate may be a polysilicon gate or a metal gate, or any other suitable material known to those skilled in the art. In this embodiment, a polysilicon gate is exemplified.
S4', forming a source region and a drain region with a second doping type in the well regions at two sides of the grid respectively. The second doping type may be P-type or N-type. By way of example, in one embodiment, the source and drain regions are both N-type doped.
S5', after forming the well region, performing an ion doping process on the well region below the drain region to improve the doping concentration of the well region. The ion doping process is illustratively an ion implantation process.
In one embodiment, the width of the ion doping process is less than the width of the drain region.
In one embodiment, the ion doping process is a first doping type doping process.
In one embodiment, the ion doping process includes a body region doping process.
In one embodiment, the doping depth of the ion doping process is greater than the depth of the well region to form an integral region beneath the well region. By way of example, in one embodiment, the body region is P-type, consistent with the doping type of the well region.
In one embodiment, the electrostatic discharge protection device comprises a GGNMOS device.
In one embodiment, the first doping type is P-type and the second doping type is N-type.
Example III
An electrostatic discharge protection device is manufactured by adopting the manufacturing method of the electrostatic discharge protection device based on the BCD platform.
In one embodiment, as shown in fig. 5, a GGNMOS device for ESD protection includes a P-type semiconductor substrate PSUB, a gate G built on the P-type semiconductor substrate, a source terminal S and a drain terminal D located at both sides of the gate, and a P-type heavily doped region SP disposed between the source terminal and the source terminal, the source terminal having an N-type heavily doped region and being connected to the gate, the drain terminal having an N-type heavily doped region SN and being connected to the gate through a silicide block SAB, a P-type well PW located between the gate and the P-type semiconductor substrate through ion implantation, and a P-type body material Pbody located between the gate and the P-type semiconductor substrate through ion implantation.
In one embodiment, the width of the P-type body material is the same as the width of the P-type well.
In one embodiment, the width of the P-type body material is less than the width of the P-type well.
Ion implantation of LDMOS P-type body material using a high voltage BCD platform, as shown in FIG. 5, is performed under the source/block (bulk) to reduce the resistance of the well under the source/block. Penetration effects (Punch though effect) of the drain N drift region (to boost the device drain withstand voltage) and the source n+ are also prevented.
Example IV
An electrostatic discharge protection device, as shown in fig. 6, is illustratively a GGNMOS device, where the P-type body material is located below the N-type doped region at the drain and has a width less than the N-type doped region at the drain.
In one embodiment, the depth of the P-type body material is greater than the depth of the P-type well.
In one embodiment, a channel is formed between the P-type doped region and the N-type doped region at the source end, and the depth of the channel is greater than the depth of the P-type doped region and also greater than the depth of the N-type doped region at the source end.
In one embodiment, the depth of the P-type well is greater than the depth of the channel.
In one embodiment, the N-doped region of the drain is electrically connected to the positive electrode.
In one embodiment, the N-doped region of the source is electrically connected to the gate and then electrically connected to the P-doped region to the cathode.
In one embodiment, the gate and source are grounded GND, the drain is connected to the IC, and the circuit diagram is shown in fig. 7.
In one embodiment, as shown in fig. 8, there is a comparison of the breakdown voltage BV of the no P-body and the junction with the P-body, wherein the breakdown voltage BV of the no P-body (n+/PW) junction is 11.8V, the breakdown voltage BV of the increased P-body (n+/(PW & PB)) junction is 8V, a 3.8V reduction.
Example five
A manufacturing method of a GGNMOS device for ESD protection, for manufacturing a GGNMOS device for ESD protection as in embodiment three or embodiment four, the manufacturing method comprising the steps of:
s01, providing a P-type semiconductor substrate, and forming a P-type well in the P-type semiconductor substrate by ion implantation;
s02, arranging a channel on the P-type semiconductor substrate through a photoetching process;
s03, performing ion implantation in a P-type well by utilizing P-type body materials used by the high-voltage BCD platform to form P-type body materials;
s04, defining a grid electrode, a source end and a drain end with a silicide block SAB on a P-type semiconductor substrate;
s05, depositing a gate material on the P-type semiconductor substrate, manufacturing and forming a gate, and then carrying out ion implantation on the source end area and the drain end area to form an N-type doped area SN;
s06, performing ion implantation at the other end of the channel to form a P-type doped region SP.
P-type body material ion implantation (Pbody implant) in a high voltage BCD platform is performed in the P-type well PW region of the GGNMOS, as shown in FIG. 5.
The GGNMOS device for ESD protection has the following advantages:
1) Reducing the resistance Rwell of the well;
i) The starting voltage Vt1 is reduced, the ESD high current can be quickly started and discharged when the ESD event occurs, the design redundancy is increased, and the ESD high current can be used as independent ESD protection;
ii) increasing the sustain voltage Vh, reducing latch-up risk;
iii) The secondary breakdown current It2 is increased, and the ESD performance is improved;
2) The design Area is not increased while the ESD performance is improved;
3) The ESD performance is improved without additional mask and process steps, and the process cost is not increased;
4) Since the device size and MOS structure are not changed, the device model (spice model) is unchanged, re-extraction is not needed, and the process is simplified.
Example six
In one embodiment, as shown in fig. 6, the P-type body material ion implantation region only covers the Drain (Drain) CT region, and it is enough to meet the basic process P-type body material design rule (P-type body material width, space), and cannot cover the entire Drain n+ region SN.
The GGNMOS device for ESD protection has the following advantages:
1) After the ion implantation of the P-type body material is added, the Drain Junction (Drain-Bulk Junction) is changed from N+/PW (diode D) to N+/PW (diode D) and N+/PW & Pbody (diode D'). PW & Pbody is thicker than PW, so that the local well resistance Rwell below the drain CT is reduced, D' is lower than the breakdown voltage of D, and the drain CT is preferentially opened;
i) The starting voltage Vt1 is reduced, the ESD high current can be quickly started and discharged when the ESD event occurs, the design redundancy is increased, and the ESD high current can be used as independent ESD protection;
ii) increasing the second breakdown current It2, improving ESD performance;
2) The design Area is not increased while the ESD performance is improved;
3) The ESD performance is improved without additional mask and process steps, and the process cost is not increased;
4) The basic size of the device and the MOS junction are unchanged, and a device model (spice model) is not required to be extracted again, so that the process is simplified.
Example seven
An electronic device comprising the electrostatic discharge protection device of the above embodiment.
The electronic device of the embodiment may be any electronic product or apparatus such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, MP3, MP4, PSP, and the like, and may also be any intermediate product including a circuit. The electronic device provided by the embodiment of the invention has better performance due to the use of the semiconductor device.
Compared with the traditional manufacturing method, the manufacturing method and the electronic device of the electrostatic discharge protection device based on the BCD platform form a P-type body material by utilizing the high-voltage BCD platform to perform ion implantation, so that the resistance of a P-type well is reduced, the starting voltage Vt1 is reduced, the design redundancy is increased, the maintenance voltage Vh is increased, the latch-up risk is reduced, the secondary breakdown current It2 is increased, the ESD performance is improved, meanwhile, the design area is not increased, no additional mask and process steps are required, and the device model (spice model) is unchanged and the process cost is not increased because the device size and the MOS structure are not changed.
The present invention has been illustrated by the above-described embodiments, but it should be understood that the above-described embodiments are for purposes of illustration and description only and are not intended to limit the invention to the embodiments described. In addition, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications are possible in light of the teachings of the invention, which variations and modifications are within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (10)

1. A method for manufacturing an electrostatic discharge protection device based on a BCD platform, comprising the steps of:
providing a semiconductor substrate;
forming a well region with a first doping type in the semiconductor substrate;
forming a gate on a surface of the semiconductor substrate over the well region;
forming a source region and a drain region with a second doping type in the well regions at two sides of the grid respectively;
after forming the well region, an ion doping process is performed on the well region to reduce the resistance of the well region.
2. A method for manufacturing an electrostatic discharge protection device based on a BCD platform, comprising the steps of:
providing a semiconductor substrate;
forming a well region with a first doping type in the semiconductor substrate;
forming a gate on a surface of the semiconductor substrate over the well region;
forming a source region and a drain region with a second doping type in the well regions at two sides of the grid respectively;
after forming the well region, an ion doping process is performed on the well region below the drain region to increase the doping concentration of the well region.
3. The method of claim 2, wherein the ion doping process has a width less than a width of the drain region.
4. The method of claim 1 or 2, wherein the ion doping process is a first doping type doping process.
5. The method of claim 1 or 2, wherein the ion doping process comprises a body region doping process.
6. The method of claim 1 or 2, wherein the ion doping process has a doping depth greater than a depth of the well region to form an integrated region under the well region or a doping depth less than the well region to form an integrated region within the well region.
7. The method of manufacturing a BCD platform based electrostatic discharge protection device of claim 1 or 2, wherein said electrostatic discharge protection device comprises a GGNMOS device.
8. The method of claim 1 or 2, wherein the first doping type is P-type and the second doping type is N-type.
9. An electrostatic discharge protection device manufactured by the BCD platform-based electrostatic discharge protection device manufacturing method according to any one of claims 1-8.
10. An electronic device comprising the electrostatic discharge protection device of claim 9.
CN202211709954.0A 2022-12-29 2022-12-29 Manufacturing method of electrostatic discharge protection device based on BCD platform and electronic device Pending CN116130421A (en)

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