CN116129970B

CN116129970B - EEPROM (electrically erasable programmable read-Only memory) programming power-on method, EEPROM chip and replaceable accessory

Info

Publication number: CN116129970B
Application number: CN202310420290.4A
Authority: CN
Inventors: 阮荣斌; 龚明
Original assignee: Jihai Microelectronics Co ltd
Current assignee: Jihai Microelectronics Co ltd
Priority date: 2023-04-19
Filing date: 2023-04-19
Publication date: 2023-09-01
Anticipated expiration: 2043-04-19
Also published as: CN116959530A; CN116129970A

Abstract

The embodiment of the application provides a burning powering-on method of an EEPROM, an EEPROM chip and a replaceable accessory, wherein the method comprises the following steps: when a burning operation sent by a host is received, detecting a burning duration corresponding to the burning operation; if the programming operation is judged to be the first programming operation according to the programming duration, the EEPROM is controlled to output a level signal according to a preset level output rule, the first programming operation is the programming operation with the programming duration smaller than a preset programming duration threshold, and the level output rule is matched with the programming power-on characteristics of the EPROM. In the embodiment of the application, the electrical characteristic of the EEPROM is simulated by the burning of the EPROM, so that an electrical end detection mechanism of the host is satisfied, and compatible and replaceable accessories are available in the host.

Description

EEPROM (electrically erasable programmable read-Only memory) programming power-on method, EEPROM chip and replaceable accessory

Technical Field

The application relates to the technical field of electronics, in particular to a burning power-on method of an EEPROM, an EEPROM chip and a replaceable accessory.

Background

With the development of printing image forming technology, image forming apparatuses such as printers, copiers, facsimile machines, word processors, and the like have been widely used. Image forming apparatuses have built therein a replaceable item, i.e., an imaging cartridge, for easy replacement by a user for containing an imaging substance (e.g., ink, toner, etc.), wherein the imaging cartridge is typically provided with an imaging cartridge chip. The imaging process (e.g., printing process) of the image forming apparatus is mainly completed by the interaction of the imaging cartridge chip and the image forming apparatus. The image forming apparatus stores authentication information for authenticating the cartridge chip by presetting the model, color, and the like of the cartridge. The imaging cartridge chip interacts with the image forming device for purposes of performing validation of the imaging cartridge and providing imaging information during subsequent imaging.

The original imaging cartridge chip of the image forming apparatus typically employs erasable programmable read-only memory (Erasable Programmable Read Only Memory, EPROM) for data storage. However, compatible imaging cartridges typically employ electrically erasable programmable read-only memory (Electrically Erasable Programmable Read Only Memory, EEPROM) for data storage. Because of the different characteristics of EPROM and EEPROM, when a compatible imaging cartridge is installed on an image forming device, it is sometimes unrecognizable to the image forming device, resulting in the compatible imaging cartridge being unusable.

Disclosure of Invention

In view of this, the present application provides a method for powering on an EEPROM, an EEPROM chip, and a replaceable accessory, so as to solve the problem in the prior art that a compatible imaging box cannot be identified by an image forming apparatus, and thus the compatible imaging box is not usable.

In a first aspect, an embodiment of the present application provides a method for powering on an EEPROM during programming, including:

when a burning operation sent by a host is received, detecting a burning duration corresponding to the burning operation;

if the programming operation is judged to be the first programming operation according to the programming duration, the EEPROM is controlled to output a level signal according to a preset level output rule, the first programming operation is the programming operation with the programming duration smaller than a preset programming duration threshold, and the level output rule is matched with the programming power-on characteristics of the EPROM.

In one possible implementation manner, the controlling the EEPROM to output a level signal according to a preset level output rule includes:

and controlling the EEPROM to gradually increase the level signal output after each time of receiving the first burning operation in the target level interval.

In one possible implementation manner, the controlling the EEPROM to gradually increase the level signal output after each time the first writing operation is received in the target level interval includes:

and controlling the EEPROM to gradually increase the level grade corresponding to the level signal output after each time of the first burning operation is received in the target level interval according to the level grade divided by the target level interval.

In one possible implementation manner, the controlling the EEPROM to gradually increase, in a target level interval, a level corresponding to a level signal output after each time of receiving the first writing operation according to a level divided by the target level interval includes:

first data are configured in a first EE module of the EEPROM, so that the first EE module outputs a level signal corresponding to the target level interval;

and configuring second data in a second EE module of the EEPROM, and rewriting a level grade corresponding to a level signal output by the first EE module according to the second data, wherein after each time of receiving the first burning operation, the second data configured in the second EE module is increased or decreased, so that the level grade corresponding to the level signal output by the first EE module is increased.

In one possible implementation, the method further includes:

and configuring third data in the second EE module, wherein the third data is used for indicating the protection state of the level signal output by the first EE module, and when the level signal output by the first EE module is in the protected state, the level signal output by the first EE module is not rewritten according to the second data configured in the second EE module.

In one possible implementation, the method further includes:

fourth data is configured in the third EE module of the EEPROM, the fourth data being used to indicate a gradient in which the second data is incremented or decremented each time the first burning operation is received.

In one possible implementation, the method further includes:

and configuring fifth data in a third EE module of the EEPROM, wherein the fifth data is used for indicating the effective duration of the first burning operation.

In one possible implementation manner, before the EEPROM is controlled to gradually increase the level signal output after each time the first writing operation is received in the target level interval, the method further includes:

receiving address information sent by the host, wherein the address information is used for indicating a bit to be accessed by the host;

and determining the target level interval according to the address information, wherein the target level interval corresponds to a bit to be accessed by the host.

In one possible implementation manner, after detecting the writing duration corresponding to the writing operation when the writing operation of the host is received, the method further includes:

and if the writing operation is judged to be a second writing operation according to the writing time length, writing the data in the EEPROM according to the second writing operation, wherein the second writing operation is the writing operation with the writing time length being greater than or equal to a preset writing time length threshold value.

In one possible implementation manner, before the recording duration corresponding to the recording operation is detected when the recording operation sent by the host is received, the method further includes:

and judging the operation type corresponding to the time sequence sent by the host, wherein the operation type comprises a burning operation and a reading operation.

In a second aspect, an embodiment of the present application provides an EEPROM chip, including:

EEPROM；

a controller configured to perform the method of any of the first aspects.

In one possible implementation, the EEPROM includes a first EE module and a second EE module.

In one possible implementation, the EEPROM further comprises a third EE module.

In a third aspect, embodiments of the present application provide a replaceable accessory comprising the EEPROM chip of any one of the second aspects.

The technical scheme provided by the embodiment of the application has at least the following advantages:

1. the electrical characteristics of the EEPROM are simulated and recorded by the EPROM, so that an electrical end detection mechanism of the host is met, and the compatible replaceable accessory is available in the host;

2. the second EE module is used for realizing multi-level output of the first EE module, so that the requirements of each level grade are met, the output level signals can be adjusted according to corresponding configuration parameters, and the anti-upgrading capability is stronger;

3. by configuring the ascending or descending gradient of the second data in the second EE module through the third EE module, the simulation of the burning power-on characteristics of the EPROM is more flexible.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic view of an application scenario provided in an embodiment of the present application;

fig. 2 is a schematic diagram of another application scenario provided in an embodiment of the present application;

fig. 3 is a schematic diagram of a conventional one-time writing scheme for EPROM according to an embodiment of the present application;

fig. 4 is a schematic diagram of a scheme for performing multiple burning and detection on EPROM according to an embodiment of the present application;

fig. 5 is a schematic diagram of communication between an image forming apparatus and an EPROM memory circuit according to an embodiment of the present application;

FIG. 6 is a schematic flow chart of a method for powering on an EEPROM according to an embodiment of the present application;

FIG. 7 is a block diagram of an EEPROM according to an embodiment of the present application;

FIG. 8 is a block diagram of an EEPROM chip according to an embodiment of the present application;

fig. 9 is a block diagram of a replaceable accessory according to an embodiment of the present application.

Detailed Description

For a better understanding of the technical solution of the present application, the following detailed description of the embodiments of the present application refers to the accompanying drawings.

It should be understood that the described embodiments are merely some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one way of describing an association of associated objects, meaning that there may be three relationships, e.g., a and/or b, which may represent: the first and second cases exist separately, and the first and second cases exist separately. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

EPROM is a ROM memory with erasable function, which can be reprogrammed after erasing, and the existing data content in the EPROM must be removed by ultraviolet irradiation before writing. EPROM chips are relatively easy to identify, and the package contains a "quartz glass window", which is typically covered with black sticker to prevent direct sunlight. EPROM uses a gate to store electrons, characterizes different voltages by how much electrons are stored, and expresses some related information and data by voltages, wherein the stored electrons are realized by external voltage burning, similar to the charging of a capacitor, and change with time and change of external voltage in the charging process. If the burning duration is shorter during the charging period and the data is read out after each burning, the read voltage will be in a gradually rising state, and the image forming apparatus can detect the rising state (the rising speed, the rising amplitude, the local interval and other parameters) so as to confirm whether the imaging box is an original imaging box. Compatible imaging cartridges typically employ EEPROMs for data storage, and the read-out voltages of EEPROMs typically do not have a gradual rise. Therefore, when a compatible imaging cartridge is installed on an image forming apparatus, it is often unrecognizable by the image forming apparatus, resulting in the compatible imaging cartridge being unusable.

Based on this, the embodiment of the application provides a programming and powering scheme of the EEPROM, and the programming and powering characteristics of the EPROM are simulated by the EEPROM, so that an electrical end detection mechanism of a host is satisfied, and compatible replaceable accessories are available in the host, and detailed description is made below with specific implementation modes.

Referring to fig. 1, a schematic view of an application scenario is provided in an embodiment of the present application. As shown in fig. 1, the electronic device includes a host and an EEPROM chip, which may be a chip on a replaceable accessory that is used with the host. When the accessory is mounted on the host, the host and the EEPROM chip are communicatively coupled. The communication connection may be by way of a contact, antenna or coil. By way of example, the host may be a computer, mobile phone, tablet, image forming device, etc., and the accessory may be a camera, USB memory, battery, data line, charger, docking station, imaging box, etc.

In the following embodiments, an image forming apparatus and an imaging box are taken as examples to facilitate understanding, and a technical solution provided by the embodiments of the present application is described. However, this should not be taken as limiting the scope of the application.

Referring to fig. 2, another application scenario is schematically provided in an embodiment of the present application. As shown in fig. 2, the imaging cartridge 2 includes an EEPROM chip 21, and the EEPROM chip 21 has an EEPROM211 and a controller 212. It will be appreciated that the imaging cartridge 2 including the EEPROM chip 21 is a compatible imaging cartridge, and in order to solve the problem that the compatible imaging cartridge is not usable in the image forming apparatus, the embodiment of the present application simulates the electrical characteristics of the EPROM by the EEPROM, so that the compatible imaging cartridge can pass the authentication of the image forming apparatus, and further, normal use of the compatible imaging cartridge in the image forming apparatus is realized. The principle thereof will be described in detail hereinafter.

Referring to fig. 3, a schematic diagram of a conventional one-time writing scheme for EPROM is provided in an embodiment of the present application. As shown in fig. 3, the writing scheme is that the EPROM is written from an original low level to a high level by a high voltage signal with a duration of more than 1ms, and at the moment, the data of the EPROM is changed from 0 to 1, so that the purpose of writing and replacing the data is achieved.

Referring to fig. 4, a schematic diagram of a scheme for performing multiple burning and detection on EPROM according to an embodiment of the present application is provided. As shown in fig. 4, if the writing duration is shortened during writing, each writing is incomplete (for example, 15us is written in fig. 4), the voltage gradually rises as shown in fig. 4 after multiple times of writing, and the last writing is performed for 1ms, so as to ensure that the data writing is completed. Because of the process difference of each manufacturer, each product has the charging characteristic, the voltage rising state with different slopes can be presented, and some compatible accessories can be checked by utilizing the specific slopes and the characteristics, so that the aim of checking and detecting is fulfilled.

Referring to fig. 5, a schematic diagram of communication between an image forming apparatus and an EPROM memory circuit according to an embodiment of the present application is provided. The existing partial model image forming apparatus reads information on a consumable chip by a connection manner as shown in fig. 5. In the image forming apparatus, a current source I and a voltage source U are respectively provided, wherein the output voltage of the voltage source U is 16V, and the driving current is greater than 10mA; the driving current of the current source I is 1mA, the highest voltage amplitude is 15V, and the current source signal or the voltage source signal can be switched and output to the signal line ID through the Switch under the control of the controller. The signal line ID is connected to an EPROM memory circuit of the consumable chip, which illustratively includes four information bits FG1, FG2, FG3, and FG4, respectively, where bit FG1 is a reference bit that is set to be unprogrammable; bit FG2 has been fully programmed, the resistance between drain and source is very large (equivalent to an open circuit); bits FG3 and FG4 are Stacked-gate injection MOS (Stacked-gate Injection Metal Oxide Semiconductor, SIMOS), and the consumable chip receives address information (transmission path of the address information is not shown in the figure) sent from the image forming apparatus, selects bits to be accessed through word lines WL (word lines) and bit lines BL (bit lines) after decoding, and the source of the selected bits is connected to a low level.

For example, when the bit FG4 is to be programmed (generally defined as programming is written "1", the programmed SIMOS is defined as storing information "1"), the image forming apparatus outputs a voltage source signal on the signal line ID, selects the bit FG4 through the word line WL and the bit line BL, and since the control gate and drain of the bit FG4 are both at a high voltage of 16V and the source is at a low level, the condition of SIMOS programming is satisfied, the PN junction between the drain and the substrate will exhibit avalanche breakdown, high-energy electrons generated by avalanche breakdown pass through the silicon oxide insulating layer of the control gate under the action of the gate electric field, and are injected onto the floating gate, which after injecting electrons, raises the turn-on voltage (also referred to as threshold voltage) of the SIMOS. When an access to an EPROM memory circuit is to be made, an image forming apparatus outputs a current source signal on a signal line ID, selects a bit to which address information is directed through a word line WL and a bit line BL, and a digital-to-analog converter (Analog to Digital Converter, ADC) provided in the image forming apparatus can acquire a voltage value of the signal line ID at this time, by which the image forming apparatus can determine a value read in the EPROM memory circuit. For example, reading bit FG3, since bit FG3 has not been programmed (defined to store information "0"), the turn-on voltage at this time is relatively low, the resistance between the drain and source of FG3 is small (about 3.3kΩ), and the voltage that the image forming apparatus captures on the ID signal line is about 3.3V. Similarly, if the image forming apparatus accesses bit FG4, the resistance between the drain and source increases (about 7kΩ) because bit FG4 has been programmed, and the voltage that the image forming apparatus captures on the ID signal line is about 7V. When accessing the reference bit FG1, the resistance between the drain and source of the bit FG1 is typically between programmed and unprogrammed, e.g., 4KΩ, the voltage that the image forming device captures on the ID signal line is about 4V; when the bit FG2 is accessed, the voltage collected by the image forming apparatus on the ID signal line is the highest amplitude 15V output by the current source I, because the bit FG2 corresponds to an open circuit. It can be seen that the digital-to-analog converter ADC needs to read signals of 4 different voltage values, not just high or low, when accessing the consumable chip.

Referring to fig. 6, a flowchart of a method for powering on an EEPROM during programming is provided in an embodiment of the present application. The method can be applied to the application scenario shown in fig. 1 and 2, and as shown in fig. 6, the method mainly comprises the following steps.

Step S601: when a burning operation sent by a host is received, detecting the burning duration corresponding to the burning operation.

In a specific implementation, it may be first determined whether the operation type corresponding to the timing of the host transmission is a writing operation (the state of the Switch selection voltage source U shown in fig. 5) or a reading operation (the state of the Switch selection current source I shown in fig. 5). When the operation type corresponding to the time sequence sent by the host is judged to be the burning operation, detecting the burning duration corresponding to the burning operation.

According to the writing time length, the writing operation can be divided into a first writing operation and a second writing operation. The first writing operation is a writing operation (writing operation corresponding to multiple times of writing in fig. 4) with a writing duration less than a preset writing duration threshold (for example, 1 ms); the second writing operation is a writing operation (the writing operation corresponding to the last writing in fig. 4) with a writing time length greater than or equal to a preset writing time length threshold.

Step S602: if the burning operation is judged to be the first burning operation according to the burning time length, the EEPROM is controlled to output a level signal according to a preset level output rule.

In a specific implementation, a level output rule may be configured in the EEPROM chip, and it is understood that in order to simulate the burn-in electrical characteristics of the EPROM, the level output rule should match the burn-in electrical characteristics of the EPROM. When the burning operation is judged to be the first burning operation according to the burning time length, the EEPROM is controlled to output a level signal according to a preset level output rule, so that the simulation of the burning power-on characteristics of the EPROM is realized.

As described above, in some possible implementations, the electrical characteristic of the EPROM during the programming is that the voltage is gradually increased in a certain level interval, where the level interval corresponds to a bit, and the level interval corresponding to different bits may be different. Illustratively, the level interval corresponding to bit FG3 in FIG. 5 is 3-4V; the level interval corresponding to bit FG4 is 6-8V. For ease of illustration, this level interval is referred to herein in other sections as a "target level interval". Thus, in some possible implementations, controlling the EEPROM to output the level signal according to the preset level output rule may specifically include: and controlling the EEPROM to gradually increase the level signal output after each time of receiving the first burning operation in the target level interval.

It will be appreciated that, since the "target level interval" information is required to be used in the above steps, the target level interval is generally required to be determined before the "control EEPROM gradually increases the level signal output after each time the first writing operation is received in the target level interval". Specifically, address information sent by a host is received, wherein the address information is used for indicating bits to be accessed by the host; and determining a target level interval according to the address information. For example, if it is determined that the bit to be accessed is bit FG3 according to the address information, the target level interval is 3-4V; if it is determined that the bit to be accessed is bit FG4 according to the address information, the target level interval is 6-8V. Note that, in the application scenario shown in fig. 5, since the level signals corresponding to the bit FG3 and the bit FG4 are section data, only the level signals corresponding to the bit FG3 and the bit FG4 need to be simulated. In addition, in some possible application scenarios, the target level interval may also be information preconfigured in the EEPROM, and need not be determined temporarily according to address information sent by the host, which is not limited by the embodiment of the present application.

With continued reference to fig. 4, in the application scenario, after 15us of each burning, the read level signal gradually increases according to a certain gradient. In order to simulate the power-on characteristic of the recording, in one possible implementation manner, the target level interval is divided into a plurality of level grades, and the EEPROM is controlled to gradually increase the level grade corresponding to the level signal output after each time of receiving the first recording operation in the target level interval according to the level grade divided by the target level interval. It should be noted that the higher the level, the higher the corresponding level signal. For example, the target level interval 3-4V corresponding to the bit FG3 is divided into 16 level classes, respectively: 3.000-3.0625, 3.0625-3.125, 3.125-3.1875, 3.1875-3.25, 3.25-3.3125, 3.3125-3.375, 3.375-3.4375, 3.4375-3.5, 3.5-3.5625, 3.5625-3.625, 3.625-3.6875, 3.6875-3.75, 3.75-3.8125, 3.8125-3.875, 3.875-3.9375, 3.9375-4.000; the target level interval 6-8V corresponding to the bit FG4 is divided into 16 level classes, which are respectively: 6.000-6.125, 6.125-6.250, 6.250-6.375, 6.375-6.500, 6.500-6.625, 6.625-6.750, 6.750-6.875, 6.875-7.000, 7.000-7.125, 7.125-7.250, 7.250-7.375, 7.375-7.500, 7.500-7.625, 7.625-7.750, 7.750-7.875, 7.875-8.000. It should be noted that, according to actual needs, those skilled in the art may divide the target level interval into other numbers of level levels, such as 17, 18, 32 or 64 level levels, which is not particularly limited by the embodiment of the present application.

In addition, after each time the first burning operation is received, the level corresponding to the output level signal may be increased according to different gradients. Illustratively, the output level signal is increased by 1 level, 2 level levels, or more after each reception of the first writing operation, which is not particularly limited in the embodiment of the present application.

In a specific implementation, corresponding data may be configured in the EEPROM, so as to gradually increase a level corresponding to the output level signal after each time of receiving the first writing operation, which will be described in detail below with reference to the accompanying drawings.

Referring to fig. 7, a block diagram of an EEPROM according to an embodiment of the present application is provided. As shown in fig. 7, the EEPROM includes 3 EE (EEPROM) modules, which are a first EE module, a second EE module, and a third EE module, respectively. The first EE module is used for configuring first data, and the first data is used for indicating to output a corresponding level signal. Illustratively, when it is desired to output a 3-4V interval level signal (analog bit FG 3), the first data is configured to 01; when a 6-8V interval level signal is required to be output ((analog bit FG 4), the first data is configured to be 00, when a 3.3V fixed level signal is required to be output (analog bit FG 1), the first data is configured to be 10, when a 15V fixed level signal is required to be output (analog bit FG 2), the first data is configured to be 11, the second EE module is used for configuring second data, the second data is used for indicating a level grade corresponding to the level signal output by the first EE module, after each first burning operation is received, the level grade corresponding to the output interval level signal is gradually increased by rewriting the second data.

In one possible implementation, the target level interval is divided into 16 level classes. It can be appreciated that when the target level interval is divided into 16 level classes, the second data can realize the configuration of the 16 level classes by 4 bits. Exemplary, the correspondence between the configuration parameters of the second data and the level levels is shown in table one.

Table one:

configuration parameters	Actual output level (V)/analog bit FG4	Actual output level (V)/analog bit FG3
			0000	6.000~6.125	3.000~3.0625
0001	6.125~6.250	3.0625~3.125
			0010	6.250~6.375	3.125~3.1875
0011	6.375~6.500	3.1875~3.25
			0100	6.500~6.625	3.25~3.3125
0101	6.625~6.750	3.3125~3.375
			0110	6.750~6.875	3.375~3.4375
0111	6.875~7.000	3.4375~3.5
			1000	7.000~7.125	3.5~3.5625
1001	7.125~7.250	3.5625~3.625
			1010	7.250~7.375	3.625~3.6875
1011	7.375~7.500	3.6875~3.75
			1100	7.500~7.625	3.75~3.8125
1101	7.625~7.750	3.8125~3.875
			1110	7.750~7.875	3.875~3.9375
1111	7.875~8.000	3.9375~4.000

It can be understood that in the first table, the second data is in a proportional relationship with the level, so that after each time the first writing operation is received, the second data is configured to be incremented, and the level corresponding to the output level signal can be incremented. For example, when the analog bit FG4 is received for the 1 st time, the configuration parameter of the second data is 0000, and the actual output level is 6.000-6.125; after the first burning operation is received for the 2 nd time, adding 1 to the configuration parameter of the second data, adjusting the configuration parameter to 0001, and enabling the actual output level to be 6.125-6.250; after receiving the first burning operation for the 3 rd time, adding 1 to the configuration parameter of the second data, adjusting the configuration parameter to 0010, and enabling the actual output level to be 6.625-6.750; and so on, and will not be described in detail herein.

In some possible application scenarios, it may not be necessary to rewrite the level signal output by the first EE module according to the second data, and thus, it is necessary to protect the level signal output by the first EE module. In a specific implementation, third data are configured in the second EE module, where the third data are used to indicate a protection state of the level signal output by the first EE module, and when the level signal output by the first EE module is in the protected state, the level signal output by the first EE module is not rewritten according to the second data configured in the second EE module. For example, 5 bits of data are configured in the second EE module, wherein 1 bit is the third data, and is used for representing the protection state; the other 4 bits are second data for representing the level gradation. For example, with the most significant bit as the protection bit (third data), when the data configured in the second EE module is 0XXXX (or 1 XXXX), the level signal indicating the output of the first EE module is not in the protected state, which can be rewritten according to the level identified by the last 4 bits; when the data configured in the second EE module is 1XXXX (or 0 XXXX), the level signal representing the output of the first EE module is in a protected state, which cannot be rewritten according to the level of the last 4-bit flag.

In the above embodiment, the configuration parameter of the second data is increased by 1 after each time the first writing operation is received. In some possible implementations, the configuration parameters of the second data may need to have other increasing or decreasing gradients each time the first burning operation is received to better simulate the burning power-on characteristics of the EPROM. In a specific implementation, fourth data may be configured in the third EE module, where the fourth data is used to indicate a gradient in which the second data is incremented or decremented each time the first burning operation is received. For example, the configuration parameters of the second data may be increased by 2 or decreased by 2, increased by 3 or decreased by 3, etc. after each time the first recording operation is received by configuring the fourth data, which is not particularly limited in the embodiment of the present application.

In some possible implementations, fifth data may be further configured in the third EE module, where the fifth data is used to indicate the duration of the valid first burning operation. Specifically, only when the writing operation reaches a certain period (e.g., 20 us), the valid first writing operation is considered to be received, so as to realize increment or decrement of the second data.

In addition, if the writing operation is judged to be a second writing operation according to the writing time length, the data in the EEPROM is rewritten according to the second writing operation, so that a successful writing result is achieved.

In summary, the method for powering on the EEPROM by burning provided by the embodiment of the application has at least the following advantages:

Corresponding to the above embodiment, the embodiment of the application also provides an EEPROM chip.

Referring to fig. 8, a structural block diagram of an EEPROM chip is further provided in an embodiment of the present application. As shown in fig. 8, the EEPROM chip includes an EEPROM and a controller configured to perform some or all of the steps in the above-described method embodiments. The specific details of the embodiments of the present application may be referred to the descriptions of the foregoing examples, and are not repeated herein for brevity.

Corresponding to the above embodiments, the embodiments of the present application also provide a replaceable accessory.

Referring to fig. 9, a block diagram of a replaceable accessory is also provided in accordance with an embodiment of the present application. As shown in fig. 9, the replaceable accessory includes an EEPROM chip, and the details of the EEPROM chip can be found in the description of the above example, and the details are not repeated herein for brevity.

Corresponding to the above embodiments, the present application also provides a computer program product comprising executable instructions which, when executed on a computer, cause the computer to perform some or all of the steps of the above method embodiments.

In the embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relation of association objects, and indicates that there may be three kinds of relations, for example, a and/or B, and may indicate that a alone exists, a and B together, and B alone exists. Wherein A, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of the following" and the like means any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.

Those of ordinary skill in the art will appreciate that the various elements and algorithm steps described in the embodiments disclosed herein can be implemented as a combination of electronic hardware, computer software, and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In several embodiments provided by the present application, any of the functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a read-only memory (ROM), a random access memory (random access memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The foregoing is merely exemplary embodiments of the present application, and any person skilled in the art may easily conceive of changes or substitutions within the technical scope of the present application, which should be covered by the present application. The protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for powering up an EEPROM by burning, comprising:

if the programming operation is judged to be the first programming operation according to the programming duration, the EEPROM is controlled to output a level signal according to a preset level output rule, the first programming operation is the programming operation with the programming duration smaller than a preset programming duration threshold, and the level output rule is matched with the programming power-on characteristics of the EPROM;

wherein, the controlling the EEPROM outputs a level signal according to a preset level output rule, and the controlling comprises:

2. The method of claim 1, wherein controlling the EEPROM to gradually increase the level signal output each time the first writing operation is received within a target level interval comprises:

3. The method of claim 2, wherein controlling the EEPROM to gradually increase the level corresponding to the level signal output after each reception of the first writing operation in the target level section according to the level divided in the target level section comprises:

4. A method according to claim 3, characterized in that the method further comprises:

5. The method according to claim 3 or 4, characterized in that the method further comprises:

6. The method according to claim 3 or 4, characterized in that the method further comprises:

7. An EEPROM chip, comprising:

EEPROM；

a controller configured to perform the method of any of claims 1-2.

8. The EEPROM chip of claim 7, characterized in that the EEPROM comprises a first EE module and a second EE module, the controller being further configured to perform the method of any of claims 3-4.

9. The EEPROM chip of claim 7, characterized in that the EEPROM further comprises a third EE module, the controller being further configured to perform the method of any of claims 5-6.

10. A replaceable accessory comprising the EEPROM chip of any one of claims 7-9.