CN116126576A - Data verification method, electronic device and storage medium - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 238000013524 data verification Methods 0.000 title claims abstract description 22
- 238000012795 verification Methods 0.000 claims abstract description 88
- 238000012545 processing Methods 0.000 claims abstract description 56
- 230000007958 sleep Effects 0.000 claims abstract description 14
- 230000003068 static effect Effects 0.000 claims abstract description 7
- 230000005059 dormancy Effects 0.000 claims description 15
- 238000004590 computer program Methods 0.000 claims description 5
- 230000004044 response Effects 0.000 claims description 4
- 230000008569 process Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to the technical field of computers, and discloses a data verification method, electronic equipment and a storage medium. The data verification method is applied to a verification circuit and comprises the following steps: receiving a check signal sent by a central processing unit, checking data in a Static Random Access Memory (SRAM) and obtaining a first check result; receiving a verification signal sent by the CPU after the sleep is finished, and verifying the data in the SRAM again to obtain a second verification result; the first check result and the second check result are used for the central processing unit to determine that the data in the SRAM is correct when the second check result is equal to the first check result. The central processing unit can control the hardware verification circuit to verify the data in the SRAM, so that the data in the SRAM is conveniently verified, meanwhile, the data in the SRAM is not limited by the processing performance of the central processing unit, and the speed of verifying the data in the SRAM is effectively improved.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a data verification method, an electronic device, and a storage medium.
Background
A Static Random-Access Memory (SRAM) is one type of Random Access Memory. By "static", it is meant that such memory is constantly maintained for data stored therein as long as it remains powered on. In order to avoid errors in data transmission or processing caused by SRAM missing data, it is necessary to check the correctness of the data stored in the SRAM.
However, the inventors of the present invention found that: the technical difficulty of checking the data stored in the SRAM is relatively large at present, and the technical difficulty is very dependent on the processing capacity of the central processing unit.
Disclosure of Invention
The embodiment of the invention aims to provide a data verification method, electronic equipment and a storage medium, which are used for ensuring that verification of data in an SRAM is not limited by the processing performance of a central processing unit.
In order to achieve the above object, an embodiment of the present invention provides a method for verifying data applied to a central processing unit, including: sending out a check signal, controlling a check circuit to check data in the SRAM and obtaining a first check result; dormancy is carried out, and after the dormancy is finished, a check signal is sent out, and a check circuit is controlled to check the data in the SRAM again to obtain a second check result; and if the second checking result is equal to the first checking result, determining that the data in the SRAM is correct.
In order to achieve the above object, an embodiment of the present invention further provides a verification method applied to verifying data of a circuit, including: receiving a check signal sent by a central processing unit, checking data in a Static Random Access Memory (SRAM) and obtaining a first check result; receiving a verification signal sent by the CPU after the sleep is finished, and verifying the data in the SRAM again to obtain a second verification result; the first check result and the second check result are used for the central processing unit to determine that the data in the SRAM is correct when the second check result is equal to the first check result.
In order to achieve the above object, an embodiment of the present invention further provides an electronic device, including: a central processing unit and a verification circuit; the central processing unit is used for executing the data verification method; the verification circuit is used for executing the data verification method.
In order to achieve the above object, an embodiment of the present invention further provides a computer-readable storage medium storing a computer program, which when executed by a processor, implements the above-described data verification method.
In the embodiment of the invention, the central processing unit firstly sends out a check signal to control the check circuit to check the data in the SRAM and obtain a first check result. And then dormancy is performed, and after the dormancy is finished, a check signal is sent out, and a check circuit is controlled to check the data in the SRAM again to obtain a second check result. Further, if the second check result is equal to the first check result, it is determined that the data in the SRAM is correct because the data in the SRAM is unchanged from the data in the SRAM in the first check when the second check is performed by the check circuit. By using the data verification method provided by the embodiment, the data in the SRAM can be verified by using the hardware verification circuit, so that the data in the SRAM can be conveniently verified, and meanwhile, the data in the SRAM can be verified without being limited by the processing performance of the central processing unit, and the speed of verifying the data in the SRAM can be effectively improved.
In at least one embodiment, after the control verification circuit verifies the data in the SRAM and obtains the first verification result, the method further includes: in response to an interrupt signal, the verification circuitry is stopped from performing the verification.
In at least one embodiment, the first verification result is stored on-chip by the verification circuitry. The first check result obtained before the central processing unit sleeps is stored in the specific storage medium chip, and the first check result can be conveniently obtained when the step of comparing the first check result with the second check result is carried out.
In at least one embodiment, if the second check result is equal to the first check result, determining that the data in the SRAM is correct includes: comparing the first verification result stored in the AON with the second verification result. The method can conveniently acquire the stored first check result in the chip and compare the first check result with the second check result, and further can realize the determination of the correctness of the data in the SRAM in a simple and quick manner.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures do not depict a proportional limitation unless expressly stated otherwise.
FIG. 1 is a flow chart of a method for verifying data applied to a CPU according to an embodiment of the invention;
FIG. 2 is a flow chart of a comparison check result according to an embodiment of the present invention;
fig. 3 is a flow chart of a verification method applied to data of a verification circuit according to an embodiment of the invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the following detailed description of the embodiments of the present invention will be given with reference to the accompanying drawings. However, those of ordinary skill in the art will understand that in various embodiments of the present invention, numerous technical details have been set forth in order to provide a better understanding of the present application. However, the technical solutions claimed in the present application can be implemented without these technical details and with various changes and modifications based on the following embodiments.
In the description of the present invention, it should be understood that the terms "comprises" and "comprising," and any variations thereof, as used herein, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements that are expressly listed or inherent to such process, method, article, or apparatus.
It should be noted that, in the present invention, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a number" means at least two, for example, two, three, etc., unless specifically defined otherwise.
An embodiment of the invention relates to a data verification method, which is applied to a central processing unit. In this embodiment, the data verification method includes: sending out a check signal, controlling a check circuit to check data in the SRAM and obtaining a first check result; dormancy is carried out, and after the dormancy is finished, a check signal is sent out, and a check circuit is controlled to check the data in the SRAM again to obtain a second check result; and if the second checking result is equal to the first checking result, determining that the data in the SRAM is correct.
The implementation details of the data verification method in this embodiment are specifically described below, and the following is only for facilitating understanding of the implementation details of this embodiment, and is not necessary for implementing this embodiment. The specific flow is shown in fig. 1, and may include the following steps:
In this step, the central processing unit sends a verification signal to the verification circuit, and the verification signal can control the verification circuit to verify the data in the SRAM. The result of the verification circuit for verifying the data in the SRAM is the first verification result involved in the step.
In this embodiment, the specific configuration of the verification circuit is not limited, and the verification circuit according to this embodiment may be any circuit configuration that can be used to achieve the corresponding technical effects.
In one example, after the control verification circuit included in step 101 verifies the data in the SRAM and obtains the first verification result, the method may further include: in response to an interrupt signal, the verification circuitry is stopped from performing the verification.
An interrupt refers to the entire process of the central processing unit handling an emergency event occurring during program execution. In the process of program operation, if an emergency occurs outside the system, inside the system or the current program itself, the central processing unit immediately stops the operation of the current program, automatically transfers to a corresponding processing program (interrupt service routine), and returns to the original program operation after the processing is finished, and the whole process is called program interrupt. When the central processor accepts an interrupt, it only needs to pause one or several cycles without executing the interrupt of the handler, called a simple interrupt. Interrupts can be categorized into masked interrupts and unmasked interrupts. Interrupts whose masking can be controlled by a program are called masked interrupts or maskable interrupts. When masked, the central processor will not accept interrupts. Conversely, interrupts whose masking cannot be controlled by the program, which the central processor must immediately handle, are referred to as unmasked interrupts or unmasked interrupts. The non-shielded interrupt is mainly used in the case of power failure, etc. which must be dealt with immediately. The central processing unit does not need to execute the query program when responding to the interrupt. Interrupts that are sent out to the CPU by the responded to interrupt source are called vector interrupts, and vice versa are non-vector interrupts. Vector interrupts can increase interrupt response speed.
Based on this, the interrupt signal referred to in this example can be understood as a signal that triggers the central processor to stop the program currently being executed, and to execute a new program instead. It will be appreciated that the type of interrupt corresponding to the interrupt signal is not limited in this embodiment.
Further, in some embodiments, the first verification result is stored in the chip after the verification circuit obtains the first verification result in this step. By means of the method and the device, the first check result obtained before the central processing unit sleeps can be stored in the specific storage medium chip, and the first check result can be conveniently obtained when the step of comparing the first check result with the second check result is carried out.
In the step, the central processing unit is in a dormant state, and sends a check signal to the check circuit after the dormancy is finished, wherein the check signal can control the check circuit to check the data in the SRAM again. The result obtained by the verification circuit verifying the data in the SRAM again is the second verification result involved in this step.
If the first check result is equal to the second check result, the data currently stored in the SRAM is the same as the data before the CPU sleeps, so that the CPU determines that the current data in the SRAM is correct.
In a more specific embodiment, step 103 may further include the following steps, and the flow chart described in this embodiment may refer to fig. 2:
in an embodiment in which the first verification result is stored in the chip after the verification circuit obtains the first verification result, the step may specifically include: and comparing the first check result stored in the chip with the second check result. The method can conveniently acquire the stored first check result in the chip and compare the first check result with the second check result, and further can realize the determination of the correctness of the data in the SRAM in a simple and quick manner.
if the first verification result is equal to the second verification result, jumping to step 1034; if the first check result is not equal to the second check result, the process goes to step 1033.
if the comparison in the previous step results in the first check result and the second check result being unequal, the data stored in the SRAM is different from the data stored in the CPU before the sleep, and the data stored in the SRAM is wrong, so that the CPU reports the error. In addition, the central processing unit can also perform other corresponding handling processing after reporting the error.
If the comparison in the previous step shows that the first check result is equal to the second check result, the data currently stored in the SRAM is the same as the data before the central processing unit sleeps, and therefore the central processing unit determines that the current data in the SRAM is correct. In addition, the CPU can also use the SRAM or the data therein to perform other processing or execute corresponding programs after the step.
In this embodiment, the central processing unit first sends out a check signal to control the check circuit to check the data in the SRAM and obtain a first check result. And then dormancy is performed, and after the dormancy is finished, a check signal is sent out, and a check circuit is controlled to check the data in the SRAM again to obtain a second check result. Further, if the second check result is equal to the first check result, it is determined that the data in the SRAM is correct because the data in the SRAM is unchanged from the data in the SRAM in the first check when the second check is performed by the check circuit. By using the data verification method provided by the embodiment, the data in the SRAM can be verified by using the hardware verification circuit, so that the data in the SRAM can be conveniently verified, and meanwhile, the data in the SRAM can be verified without being limited by the processing performance of the central processing unit, and the speed of verifying the data in the SRAM can be effectively improved.
Another embodiment of the invention relates to a data verification method applied to a verification circuit. In this embodiment, the data verification method includes: receiving a check signal sent by a central processing unit, checking data in a Static Random Access Memory (SRAM) and obtaining a first check result; receiving a verification signal sent by the CPU after the sleep is finished, and verifying the data in the SRAM again to obtain a second verification result; the first check result and the second check result are used for the central processing unit to determine that the data in the SRAM is correct when the second check result is equal to the first check result.
The implementation details of the data verification method in this embodiment are specifically described below, and the following is only for facilitating understanding of the implementation details of this embodiment, and is not necessary for implementing this embodiment. The specific flow is shown in fig. 3, and may include the following steps:
in the step, the checking circuit receives the checking signal sent by the central processing unit and checks the data in the SRAM under the control of the checking signal. The result obtained by the verification circuit in the verification is the first verification result.
In some embodiments, after the verifying the data in the SRAM and obtaining the first verification result, the step 201 further includes: and storing the first check result in a chip. By means of the method, the verification circuit can store the first verification result obtained before the central processing unit sleeps in a specific storage medium chip, and a foundation is provided for conveniently obtaining the first verification result when the step of comparing the first verification result with the second verification result is carried out.
In other embodiments, the verifying the data in the SRAM and obtaining the first verification result in step 201 may include: and reading data in a plurality of SRAMs, and checking the data in the SRAMs in parallel. In this example, the data in the SRAM is checked in parallel by the checking circuit, that is, the data in a plurality of SRAMs can be checked at the same time, so that the speed of checking the data in the SRAM can be further increased, and the time required for checking the data in the SRAM is shortened.
In the step, the central processing unit finishes dormancy, and the verification circuit firstly receives a verification signal sent by the central processing unit after the dormancy is finished and performs re-verification on data in the SRAM under the control of the verification signal. And (3) performing the secondary verification to obtain a result which is the second verification result involved in the step.
In some other embodiments, the verifying the data in the SRAM and obtaining a second verification result in step 202 may include: and reading the data in the plurality of SRAMs, and checking the data in the plurality of SRAMs again in parallel. In this example, the verification circuit performs the re-verification of the data in the SRAM in a parallel verification manner, so that the speed of verifying the data in the SRAM can be increased, and the time required for verifying the data in the SRAM can be shortened.
In addition, it is worth mentioning that the data in the SRAM is checked by utilizing a parallel check mode before the sleep of the central processing unit, and the data in the SRAM is checked again by utilizing a parallel check mode after the sleep of the central processing unit is finished, so that the speed of determining the correctness of the data in the SRAM can be further improved. In practice, the time to complete a data check can be tens of microseconds.
It should be noted that the technical details and the technical effects that can be achieved in the foregoing embodiments are still effective in the present embodiment. Repetition is not reduced, and detailed description is omitted in this embodiment.
In this embodiment, the verification circuit first receives a verification signal sent by the central processing unit, verifies data in the SRAM, and obtains a first verification result; receiving a verification signal sent by the CPU after the sleep is finished, and verifying the data in the SRAM again to obtain a second verification result; the first check result and the second check result are used for the central processing unit to determine that the data in the SRAM is correct when the second check result is equal to the first check result. In the embodiment, the hardware verification circuit can verify the data in the SRAM, so that the data in the SRAM can be verified conveniently, and meanwhile, the data in the SRAM can be verified without being limited by the processing performance of the central processing unit, and the speed of verifying the data in the SRAM can be effectively improved.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present application may be performed in parallel, sequentially, or in a different order, so long as the desired result of the technical solution disclosed in the present application is achieved, and the present application is not limited herein.
Another embodiment of the invention discloses an electronic device comprising a central processing unit and a verification circuit. Wherein the central processing unit is configured to execute the data verification method described in the foregoing embodiment; the verification circuit is used for executing the data verification method in the previous embodiment.
The technical details and the technical solutions that can be achieved in the foregoing embodiments are still applicable in the present embodiment. In order to reduce repetition, a description is omitted in this embodiment.
The product may perform the method provided by the embodiment of the present application, and have corresponding functional modules and beneficial effects of the performing method, and technical details not described in detail in the embodiment of the present application may be referred to the method provided by the embodiment of the present application. It should be noted that, each module in the foregoing embodiments of the present invention may be understood as a logic module, and in practical application, one logic unit may be one physical unit, or a part of one physical unit, or may be implemented by a combination of multiple physical units. In addition, in order to highlight the innovative part of the present invention, units that are not so close to solving the technical problem presented by the present invention are not introduced in the present embodiment, but this does not indicate that other units are not present in the present embodiment.
Embodiments of the present application also provide a computer-readable storage medium storing a computer program. The computer program, when executed by the processor, implements the method of verifying the data described above.
Those skilled in the art will appreciate that all or part of the steps in implementing the methods of the embodiments described above may be implemented by a program stored in a storage medium, where the program includes several instructions for causing a device (which may be a single-chip microcomputer, a chip or the like) or a processor (processor) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present invention have been shown and described, it will be understood that the above embodiments are provided to one of ordinary skill in the art to make and use the invention and are not to be construed as limiting the invention, and that various changes, modifications, substitutions and alterations may be made to the above embodiments by one of ordinary skill in the art without departing from the inventive concepts of the present application. The scope of the invention is thus not limited by the above embodiments, but should be accorded the broadest scope consistent with the novel features set forth herein.
Claims (10)
1. The data verification method is characterized by being applied to a central processing unit and comprising the following steps of:
sending out a check signal, controlling a check circuit to check data in the SRAM and obtaining a first check result;
dormancy is carried out, and after the dormancy is finished, a check signal is sent out, and a check circuit is controlled to check the data in the SRAM again to obtain a second check result;
and if the second checking result is equal to the first checking result, determining that the data in the SRAM is correct.
2. The method according to claim 1, wherein after the control verification circuit verifies the data in the SRAM and obtains the first verification result, further comprising:
in response to an interrupt signal, the verification circuitry is stopped from performing the verification.
3. The method of claim 2, wherein the first verification result is stored in a chip by the verification circuitry.
4. The method according to claim 3, wherein determining that the data in the SRAM is correct if the second check result is equal to the first check result comprises:
and comparing the first check result stored in the chip with the second check result.
5. A method for verifying data, applied to a verification circuit, comprising:
receiving a check signal sent by a central processing unit, checking data in a Static Random Access Memory (SRAM) and obtaining a first check result;
receiving a verification signal sent by the CPU after the sleep is finished, and verifying the data in the SRAM again to obtain a second verification result;
the first check result and the second check result are used for the central processing unit to determine that the data in the SRAM is correct when the second check result is equal to the first check result.
6. The method according to claim 5, further comprising, after the verifying the data in the SRAM and obtaining the first verification result:
and storing the first check result in a chip.
7. The method for verifying data according to claim 5 or 6, wherein verifying the data in the SRAM and obtaining the first verification result comprises:
and reading data in a plurality of SRAMs, and checking the data in the SRAMs in parallel.
8. The method of verifying data of claim 7, wherein the verifying the data in the SRAM again and obtaining a second verification result comprises:
and reading the data in the plurality of SRAMs, and checking the data in the plurality of SRAMs again in parallel.
9. An electronic device, comprising: a central processing unit and a verification circuit;
wherein the central processing unit is configured to perform the data verification method according to any one of claims 1 to 4; the verification circuit is configured to perform a method of verifying data as claimed in any one of claims 5 to 8.
10. A computer readable storage medium storing a computer program, wherein the computer program when executed by a processor implements the method of verifying data according to any one of claims 1 to 8.
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| CN104200835A (en) * | 2005-12-20 | 2014-12-10 | 罗伯特·博世有限公司 | Method for recognizing a power outage in a data memory and recovering the data memory |
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