CN116126091B - Radio frequency power control method, system, terminal and computer readable storage medium - Google Patents
Radio frequency power control method, system, terminal and computer readable storage medium Download PDFInfo
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- CN116126091B CN116126091B CN202310390711.3A CN202310390711A CN116126091B CN 116126091 B CN116126091 B CN 116126091B CN 202310390711 A CN202310390711 A CN 202310390711A CN 116126091 B CN116126091 B CN 116126091B
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
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Abstract
The invention discloses a radio frequency power control method, a radio frequency power control system, a radio frequency power control terminal and a computer readable storage medium, wherein a pulse mode setting instruction is acquired, and an FPGA (field programmable gate array) arranged in a radio frequency signal generator is controlled to enter a pulse mode; when the FPGA is in the pulse mode and a first appointed level is detected, acquiring pulse frequency generated by the FPGA, and acquiring frequency pulses according to the pulse frequency; when the FPGA reaches a first designated pulse state in the frequency pulses, acquiring a current voltage value corresponding to the first designated pulse state through an A/D conversion circuit, and obtaining pulse power corresponding to the current voltage value through a mapping algorithm; and converting the current voltage value through a D/A conversion circuit to obtain an analog voltage signal, controlling according to the analog voltage signal, and outputting according to the pulse power. The invention realizes the control of the radio frequency power by controlling the pulse frequency, not only meets the requirement of the output power, but also can control the temperature in a reasonable range.
Description
Technical Field
The present invention relates to the field of computer information technologies, and in particular, to a radio frequency power control method, a radio frequency power control system, a radio frequency power control terminal, and a computer readable storage medium.
Background
The RF signal generator is an electronic test device that generates RF signals at various frequencies with high spectral purity and stable frequency and amplitude. The radio frequency signal generator is different from the vector signal generator, and the vector signal generator generates radio frequency signals, but has complex digital modulation capability and has the formats of QPSK, QAM, FSK, BPSK, OFDM and the like; and the modulation provided by the radio frequency signal generator includes Amplitude Modulation (AM), frequency Modulation (FM), phase Modulation (PM), and pulse modulation.
At present, the existing radio frequency signal generator controls the actual output radio frequency power by feeding back the input current, but in the actual application, unstable conditions are caused when the radio frequency generator outputs high power due to unstable factors caused by influences of working environments (such as temperature change, electromagnetic interference and the like), when the temperature is abnormal, the output accuracy is also deviated, and particularly in the semiconductor industry, if the output abnormality or the temperature abnormality occurs, the product yield is directly affected.
Accordingly, the prior art is still in need of improvement and development.
Disclosure of Invention
The invention mainly aims to provide a radio frequency power control method, a system, a terminal and a computer readable storage medium, which aim to solve the problem that an unstable state occurs in a radio frequency generator in the prior art when high power is output.
In order to achieve the above object, the present invention provides a radio frequency power control method, which includes the following steps:
acquiring a pulse mode setting instruction, and controlling an FPGA which is arranged in a radio frequency signal generator and connected with an ARM processor to enter a pulse mode;
when the FPGA is in the pulse mode and a first appointed level is detected, acquiring pulse frequency generated by the FPGA, and acquiring frequency pulses according to the pulse frequency;
when the FPGA reaches a first designated pulse state in the frequency pulses, acquiring a current voltage value corresponding to the first designated pulse state through an A/D conversion circuit, and obtaining pulse power corresponding to the current voltage value through a mapping algorithm;
and converting the current voltage value based on a D/A conversion circuit arranged in the radio frequency signal generator to obtain an analog voltage signal, controlling according to the analog voltage signal, and outputting according to the pulse power.
Optionally, in the radio frequency power control method, the acquiring a pulse mode setting instruction controls an FPGA disposed in a radio frequency signal generator and connected to an ARM processor to enter a pulse mode, and specifically includes:
when a pulse mode setting instruction issued by a PC end is received, transmitting the pulse mode setting instruction to an ARM processor;
the ARM processor is controlled to analyze the pulse mode setting instruction, and the analyzed pulse mode setting instruction is sent to an FPGA which is arranged in the radio frequency signal generator and connected with the ARM processor;
and when the FPGA is determined to receive the analyzed pulse mode setting instruction, controlling the FPGA to enter a pulse mode.
Optionally, in the radio frequency power control method, when the FPGA is in the pulse mode and detects a first designated level, the method acquires a pulse frequency generated by the FPGA, and obtains a frequency pulse according to the pulse frequency, including:
when the FPGA enters a pulse mode, a pulse calculator in the FPGA is controlled to identify the level generated in the pulse mode;
when the pulse calculator identifies a first designated level, controlling the pulse calculator to count, obtaining periodic variation of the first designated level, and obtaining corresponding pulse frequency according to the periodic variation;
acquiring parameters sent by an upper computer in a PC (personal computer) terminal, and acquiring frequency pulses generated by the pulse calculator according to the parameters and the pulse frequency;
the parameters include a frequency period and a division factor.
Optionally, in the radio frequency power control method, when the FPGA reaches a first specified pulse state in the frequency pulses, a current voltage value corresponding to the first specified pulse state is obtained through an a/D conversion circuit, and a mapping algorithm is used to obtain pulse power corresponding to the current voltage value, which specifically includes:
after obtaining frequency pulses generated by a pulse calculator in the FPGA, when the FPGA reaches a first designated pulse state in the frequency pulses, converting the frequency pulses corresponding to the first designated pulse state by an A/D conversion circuit arranged in a radio frequency signal generator to obtain voltage values corresponding to the first designated pulse state;
reading the voltage value corresponding to the first designated pulse state for a plurality of times, and stopping reading when the voltage values are all in a preset range to obtain a current voltage value;
and obtaining the pulse power corresponding to the current voltage value through a mapping algorithm.
Optionally, in the radio frequency power control method, the converting the current voltage value based on a D/a conversion circuit disposed in a radio frequency signal generator to obtain an analog voltage signal, and controlling according to the analog voltage signal, and outputting according to the pulse power specifically includes:
inputting the current voltage value into a D/A conversion circuit arranged in a radio frequency signal generator for conversion, obtaining an analog voltage signal after conversion, controlling the analog voltage signal, and outputting according to the pulse power;
the value of the analog voltage signal = the present voltage value/4.
Optionally, in the radio frequency power control method, the converting the current voltage value based on a D/a conversion circuit disposed in a radio frequency signal generator to obtain an analog voltage signal, controlling according to the analog voltage signal, and outputting according to the pulse power, and then further includes:
controlling the temperature through the output of the pulse power;
when the temperature rises above a preset temperature threshold, the pulse frequency is reduced to a first preset threshold, and the output pulse power is controlled to be reduced;
and when the output of the pulse power is lower than a preset second threshold value, increasing the high level proportion in the pulse mode, and controlling the output pulse power to rise.
Optionally, in the radio frequency power control method, the voltage value is:
v=vr/4095×ad; v represents a voltage value, vr represents a reference voltage, and AD represents an AD value generated during A/D conversion.
In addition, to achieve the above object, the present invention further provides a radio frequency power control system, wherein the radio frequency power control system includes:
the pulse mode entering module is used for acquiring a pulse mode setting instruction and controlling an FPGA which is arranged in the radio frequency signal generator and connected with the ARM processor to enter a pulse mode;
the frequency pulse acquisition module is used for acquiring the pulse frequency generated by the FPGA when the FPGA is in the pulse mode and the first designated level is detected, and acquiring frequency pulses according to the pulse frequency;
the pulse power acquisition module is used for acquiring a current voltage value corresponding to a first designated pulse state through an A/D conversion circuit when the FPGA reaches the first designated pulse state in the frequency pulses, and acquiring pulse power corresponding to the current voltage value through a mapping algorithm;
the pulse power output module is used for converting the current voltage value based on a D/A conversion circuit arranged in the radio frequency signal generator to obtain an analog voltage signal, controlling according to the analog voltage signal and outputting according to the pulse power.
In addition, to achieve the above object, the present invention also provides a terminal, wherein the terminal includes: the system comprises a memory, a processor and a radio frequency power control program stored in the memory and capable of running on the processor, wherein the radio frequency power control program realizes the steps of the radio frequency power control method when being executed by the processor.
In addition, to achieve the above object, the present invention also provides a computer-readable storage medium storing a radio frequency power control program which, when executed by a processor, implements the steps of the radio frequency power control method as described above.
In the invention, a pulse mode setting instruction is acquired, and an FPGA which is arranged in a radio frequency signal generator and connected with an ARM processor is controlled to enter a pulse mode; when the FPGA is in the pulse mode and a first appointed level is detected, acquiring pulse frequency generated by the FPGA, and acquiring frequency pulses according to the pulse frequency; when the FPGA reaches a first designated pulse state in the frequency pulses, acquiring a current voltage value corresponding to the first designated pulse state through an A/D conversion circuit, and obtaining pulse power corresponding to the current voltage value through a mapping algorithm; and converting the current voltage value based on a D/A conversion circuit arranged in the radio frequency signal generator to obtain an analog voltage signal, controlling according to the analog voltage signal, and outputting according to the pulse power. The invention controls the actual output radio frequency power by controlling the pulse frequency, indirectly controls the temperature of the radio frequency signal generator, reduces the pulse frequency when the temperature is increased, reduces the output radio frequency power, and improves the high pulse proportion in the pulse mode when the output radio frequency power cannot meet the requirement, thereby not only meeting the requirement on the output radio frequency power, but also controlling the temperature in a reasonable range and greatly improving the time requirement on the radio frequency output.
Drawings
FIG. 1 is a flow chart of a preferred embodiment of the RF power control method of the present invention;
FIG. 2 is a schematic diagram of an RF power source according to a preferred embodiment of the RF power control method of the present invention;
FIG. 3 is a schematic diagram of the burst mode control of a preferred embodiment of the RF power control method of the present invention;
FIG. 4 is a block diagram of a preferred embodiment of the RF power control system of the present invention;
fig. 5 is a block diagram of a preferred embodiment of the terminal of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clear and clear, the present invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
As shown in fig. 1, the radio frequency power control method according to the preferred embodiment of the present invention includes the following steps:
step S10, acquiring a pulse mode setting instruction, and controlling an FPGA which is arranged in the radio frequency signal generator and connected with the ARM processor to enter a pulse mode.
The RF signal generator is an electronic test device that generates RF signals at various frequencies with high spectral purity and stable frequency and amplitude. The radio frequency signal generator is different from the vector signal generator, and the vector signal generator generates radio frequency signals, but has complex digital modulation capability and has the formats of QPSK, QAM, FSK, BPSK, OFDM and the like; and the modulation provided by the radio frequency signal generator, which is present in the radio frequency power supply (as shown in fig. 2), includes Amplitude Modulation (AM), frequency Modulation (FM), phase Modulation (PM) and pulse modulation.
The radio frequency power supply provided by the invention is characterized by comprising the following components:
1. belonging to all-digital control; 2. belongs to a pulse working mode and supports the pulse synchronization of a plurality of machines; 3. the device has the radio frequency function, the frequency variation range is 27.12MH plus or minus 5%, and the automatic matching function can be realized through frequency sweep; 4. enabling real-time power and load impedance measurements; 5. has arc extinguishing function.
The application fields of the radio frequency power supply comprise:
1. plasma etching; 2. PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma-enhanced chemical vapor deposition); 3. typical processes for semiconductor and solar thin films such as rf sputtering, parallel plate, rf laser, ICP, RIE, CVD and PVD.
The radio frequency signal generator is mainly controlled through a power control circuit, the power control circuit is connected with a PC through an Ethernet, the power control circuit comprises a circuit module taking an FPGA chip as a core, and the circuit module taking the FPGA chip as the core is used for sending out double-8-bit radio frequency digital signals.
The power control circuit comprises a detection circuit, an A/D conversion circuit, a control circuit, a current detection circuit, a D/A conversion circuit, a temperature control circuit and an adjustment circuit, wherein the circuits are electrically connected, and the power control circuit further comprises a gain compensation circuit for compensating an input signal, wherein the conversion circuit is used for converting a digital signal and an analog signal.
The A/D conversion circuit is used for converting double 8-bit digital quantity output by a digital control module taking an FPGA chip as a core and outputting two paths of radio frequency signals, wherein the A/D conversion circuit adopts an LTC2298UP chip.
The D/A conversion circuit is used for converting the radio frequency signals detected by the radio frequency output port into digital signals and sending the digital signals to the digital control module taking the FPGA chip as a core to display the radio frequency signals in real time, wherein the D/A conversion circuit adopts AD9767ASTZ and AD9709ASTZ chips.
According to the invention, a digital control signal is generated according to the obtained stable voltage value, and is converted into an analog control signal through a D/A conversion circuit, the current voltage is respectively adjusted by an adjusting circuit according to the analog control signal, and the gain compensation circuit can be controlled according to the analog control signal.
The power control circuit adjusts, controls and the like based on the output signal of the radio frequency signal generator, and the main body of the power control circuit can be independently composed of hardware, so that the purpose of detecting and analyzing the output signal is achieved, the purpose of controlling voltage is achieved, and the working efficiency of the whole circuit is improved. The control circuit can comprise a controller and a memory, and is integrated with a high-speed chip such as an FPGA control chip and an ARM memory, and the like, so as to calculate, store, compare and the like detection signals in the A/D conversion circuit.
The FPGA (Field Programmable Gate Array) is an integrated chip mainly comprising a digital circuit, belongs to one of programmable logic devices (Programmable Logic Device and PLD), and the FPGA is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), so that the defect of custom circuits is overcome, the defect of limited gate circuits of the original programmable devices is overcome, and the FPGA is positioned in the radio frequency signal generator and used for controlling the radio frequency signal generator.
Specifically, as shown in fig. 3, when a pulse mode setting instruction issued by the PC side is received, the pulse mode setting instruction is transmitted to the ARM processor.
Among these, the ARM (Advanced RISC Machine) processor is the first RISC microprocessor designed by Acorn, uk for low power consumption and cost. ARM processors are themselves 32-bit designs, but are also equipped with a 16-bit instruction set, generally saving up to 35% of the equivalent 32-bit code, while retaining all the advantages of a 32-bit system.
The ARM processor is characterized in that: the power consumption is low, the function is strong, the 16 bit/32 bit double instruction set and the cooperation partners are numerous, and the following 6 advantages are also provided:
1. small volume, low power consumption, low cost and high performance;
2. the Thumb (16 bits)/ARM (32 bits) double instruction sets are supported, and 8 bits/16 bits devices can be well compatible;
3. the registers are used in a large quantity, so that the instruction execution speed is higher;
4. most data operations are done in registers;
5. the addressing mode is flexible and simple, and the execution efficiency is high;
6. the instruction length is fixed.
And controlling the ARM processor to analyze the pulse mode setting instruction, and sending the analyzed pulse mode setting instruction to an FPGA which is arranged in the radio frequency signal generator and connected with the ARM processor.
And when the FPGA is determined to receive the analyzed pulse mode setting instruction, controlling the FPGA to enter a pulse mode.
And step S20, when the FPGA is in the pulse mode and a first designated level is detected, acquiring the pulse frequency generated by the FPGA, and obtaining frequency pulses according to the pulse frequency.
The power control circuit corrects the current and voltage values input by the A/D conversion circuit according to the voltage correction parameter and the current correction parameter obtained by the parameter correction data algorithm; after the power output control value is obtained, the power output control value is corrected again according to the impedance value and by utilizing the voltage correction parameter and the current correction parameter under different load impedances.
Specifically, after the FPGA enters a pulse mode (representing the current state of the FPGA), a pulse calculator in the FPGA is controlled to identify the level generated in the pulse mode.
Wherein, the pulse mode refers to: usually refers to a short fluctuating electric impulse (voltage or current) like a pulse, which is often used in electronic technology, and has the main characteristics of waveform, amplitude, width and repetition frequency, the pulse is a signal which occurs in a short time in the whole signal period relative to a continuous signal, no signal exists in most signal periods, just like a pulse of a person, the pulse signal is generally referred to as a digital signal, the pulse signal is already a signal in half of one period, and the signal in a computer is a pulse signal and is also called a digital signal.
The pulse counter is mainly used for counting the number of pulses in a digital system so as to realize the functions of measurement, counting and control, and has the frequency division function at the same time, and the pulse counter is generated by a program written in the FPGA, so that pulse frequency and frequency pulses can be generated.
As shown in fig. 2, when the pulse calculator identifies a first designated level, the pulse calculator is controlled to count to obtain periodic variation of the first designated level, corresponding pulse frequency is obtained according to the periodic variation, and data of the pulse frequency is obtained through a universal serial communication protocol serial port, wherein the first designated level refers to a high level, and when the FPGA enters a pulse mode, the level changes in height.
And acquiring parameters sent by an upper computer on the PC side, and acquiring frequency pulses generated by the pulse calculator according to the parameters and the pulse frequency, wherein the upper computer is application software used for controlling parameter data on the computer.
The pulse frequency refers to the number of effective discharge times occurring in the discharge gap in unit time, and the frequency pulse refers to a pulse signal value in a pulse mode.
The parameters include the period of the frequency that can be set, the amplitude of the DA output, the frequency division coefficient, and the like.
And step S30, when the FPGA reaches a first designated pulse state in the frequency pulses, acquiring a current voltage value corresponding to the first designated pulse state through an A/D conversion circuit, and obtaining pulse power corresponding to the current voltage value through a mapping algorithm.
Specifically, as shown in fig. 2, after the frequency pulse generated by the pulse calculator in the FPGA is obtained, when the FPGA reaches a first specified pulse state in the frequency pulses, the frequency pulse corresponding to the first specified pulse state is converted by an a/D conversion circuit disposed in the radio frequency signal generator, so as to obtain a voltage value corresponding to the first specified pulse state.
Firstly, a detection circuit collects a pulse signal to obtain a voltage signal, the voltage signal is converted into a detection digital signal through an A/D conversion circuit and then is input into a control circuit, and the control circuit marks the voltage signal as a maximum output detection voltage value. The control circuit records the gate voltage and the drain voltage outputted at the detected voltage, and sets the voltages as their initial reference values, respectively, and stores them in a ROM (memory). Meanwhile, the control circuit adjusts the grid voltage and the drain voltage by adjusting the values of the grid voltage and the drain voltage and then detecting and recording the input detection voltage, and the grid voltage and the drain voltage are adjusted under the condition that the detection voltage is unchanged.
The first designated pulse state is a high pulse state, and after the frequency pulse generated by the pulse calculator in the FPGA, the first designated pulse state waits until the arrival of the high pulse, wherein the high pulse state is detected to find state information when the high power is stable; on the other hand, in the invention, the first designated pulse state can be set to be a low pulse state, so that the corresponding output power can be found when the low pulse state is found, and the pulse frequency is changed correspondingly through adjusting parameters, and finally the pulse power is changed.
The A/D represents an analog signal to digital signal and is used for reading the feedback voltage value of the radio frequency power supply.
The voltage value is as follows: v=vr/4095×ad; v represents a voltage value, vr represents a reference voltage, the reference voltage is determined by a radio frequency signal generator, and AD represents an AD value generated in the A/D conversion process.
And reading the voltage value corresponding to the first designated pulse state for a plurality of times, and stopping reading when the voltage values are all in a preset range to obtain the current voltage value.
And reading the voltage value for multiple times to obtain an average value of the voltage value, and when the voltage value tends to be stable and does not change any more, reaching a stable state, wherein the pulse power value corresponding to the voltage value is an output power value for keeping the stability of the radio frequency signal generator at high power.
And obtaining the pulse power corresponding to the current voltage value through a mapping algorithm, wherein the mapping algorithm is similar to a ROM (read only memory), and the pulse power corresponding to each voltage value can be obtained by using an oscilloscope.
In the invention, the pulse width of an input signal is controlled to be converted into a power target set value through the power input by a radio frequency signal generator, and each pulse outputs set value data. The data precision can be selected between 12 bits and 16 bits.
Therefore, after the stable pulse power is obtained, the radio frequency power control method for the radio frequency signal generator comprises the following steps:
1. initializing, wherein the initializing comprises the steps of storing the power grade of the radio frequency signal generator and the power control data of each grade in a table in a one-to-one correspondence manner;
2. the power control circuit sends a command set to a pulse mode to the current radio frequency signal generator;
3. and according to the obtained level control information of the pulse power, obtaining corresponding power control data by checking the table:
4. the power control data is processed to obtain a group of control parameters;
5. under the control of the control circuit, the control parameters are sent according to ascending/descending order, and power control voltage in ascending/descending mode is generated;
6. starting the radio frequency transmitting power of the transmitter according to the power control voltage until the corresponding grade power setting is completed;
7. under control of the clock, the control parameters are sent in descending/ascending order, generating the power control voltage in descending/ascending manner.
And step S40, converting the current voltage value based on a D/A conversion circuit arranged in the radio frequency signal generator to obtain an analog voltage signal, controlling according to the analog voltage signal, and outputting according to the pulse power, wherein D/A represents that the digital signal is converted into an analog signal.
Specifically, the current voltage value is input into a D/a conversion circuit arranged in a radio frequency signal generator for conversion, an analog voltage signal is obtained after conversion, the analog voltage signal is used for control, the output is carried out according to the pulse power, and the value of the analog voltage signal is=the current voltage value/4.
And controlling the temperature through the output of the pulse power, wherein the temperature is proportional to the pulse power, and when the temperature rises above a preset temperature threshold value, the pulse frequency is reduced to a first preset threshold value, and the output pulse power is controlled to be reduced.
And when the output of the pulse power is lower than a preset second threshold value, increasing the high level proportion in the pulse mode, and controlling the output pulse power to rise.
Wherein the radio frequency signal generator further comprises a temperature control circuit, the ARM processor controlling the power of the pulses in response to the measured temperature as each pulse is applied. For example, the ARM processor may reduce the power of the pulses in response to the measured temperature approaching, reaching, or exceeding a preset temperature threshold T (the threshold temperature T may be, for example, between 40 and 65 ℃). Similarly, the ARM processor may increase the power of the pulses in response to the measured temperature being less than T. Thus, typically, the ARM processor alternately decreases and increases the power of each pulse in response to temperature.
In addition, to control each pulse, the ARM processor continuously uses the temperature readings to calculate a fractional change in the required power, and then adjusts the power of the pulse by the required change.
When the temperature exceeds a preset threshold, the temperature is indirectly controlled by controlling the radio frequency power, so that the working temperature of the power amplifier is reduced, and the service life of the product is prolonged.
The invention has the beneficial effects that:
1. by receiving the control command of the PC, the switching between the pulse and non-pulse functions can be achieved.
2. The pulse frequency can be adjusted by receiving the control command of the PC, the control of the actual power (pulse power) is realized, the corresponding radio frequency power is automatically output, and the operability of the product is improved.
3. The actual power control is realized through the pulse function, the temperature control is indirectly realized, and the pulse frequency is reduced when the temperature rises, so that the output radio frequency power is reduced; when the output power can not meet the requirement, the high/low pulse proportion in the pulse mode is improved, the requirement on power can be met, the temperature can be controlled in a reasonable range, the highest clock of the function reaches 65M (the higher the clock frequency is, the higher the sampling precision is), and the time requirement on radio frequency output is greatly improved.
Further, as shown in fig. 4, based on the above-mentioned radio frequency power control method, the present invention further provides a radio frequency power control system, where the radio frequency power control system includes:
the pulse mode entering module 51 is configured to obtain a pulse mode setting instruction, and control an FPGA that is disposed in the radio frequency signal generator and connected to the ARM processor to enter a pulse mode;
the frequency pulse acquisition module 52 is configured to acquire a pulse frequency generated by the FPGA when the FPGA is in the pulse mode and a first specified level is detected, and obtain a frequency pulse according to the pulse frequency;
the pulse power obtaining module 53 is configured to obtain, when the FPGA reaches a first specified pulse state in the frequency pulses, a current voltage value corresponding to the first specified pulse state through an a/D conversion circuit, and obtain, through a mapping algorithm, pulse power corresponding to the current voltage value;
the pulse power output module 54 is configured to convert the current voltage value based on a D/a conversion circuit provided in the radio frequency signal generator to obtain an analog voltage signal, and control the current voltage value according to the analog voltage signal, and output the current voltage value according to the pulse power.
Further, as shown in fig. 5, based on the above-mentioned radio frequency power control method and system, the present invention further provides a terminal correspondingly, where the terminal includes a processor 10, a memory 20 and a display 30. Fig. 5 shows only some of the components of the terminal, but it should be understood that not all of the illustrated components are required to be implemented and that more or fewer components may be implemented instead.
The memory 20 may in some embodiments be an internal storage unit of the terminal, such as a hard disk or a memory of the terminal. The memory 20 may in other embodiments also be an external storage device of the terminal, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card) or the like, which are provided on the terminal. Further, the memory 20 may also include both an internal storage unit and an external storage device of the terminal. The memory 20 is used for storing application software installed in the terminal and various data, such as program codes of the installation terminal. The memory 20 may also be used to temporarily store data that has been output or is to be output. In one embodiment, the memory 20 stores a radio frequency power control program 40, and the radio frequency power control program 40 is executable by the processor 10 to implement the radio frequency power control method in the present application.
The processor 10 may in some embodiments be a central processing unit (Central Processing Unit, CPU), microprocessor or other data processing chip for executing program code or processing data stored in the memory 20, for example for performing the radio frequency power control method or the like.
The display 30 may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, an OLED (Organic Light-Emitting Diode) touch, or the like in some embodiments. The display 30 is used for displaying information at the terminal and for displaying a visual user interface. The components 10-30 of the terminal communicate with each other via a system bus.
In one embodiment, the following steps are implemented when the processor 10 executes the radio frequency power control program 40 in the memory 20:
acquiring a pulse mode setting instruction, and controlling an FPGA which is arranged in a radio frequency signal generator and connected with an ARM processor to enter a pulse mode;
when the FPGA is in the pulse mode and a first appointed level is detected, acquiring pulse frequency generated by the FPGA, and acquiring frequency pulses according to the pulse frequency;
when the FPGA reaches a first designated pulse state in the frequency pulses, acquiring a current voltage value corresponding to the first designated pulse state through an A/D conversion circuit, and obtaining pulse power corresponding to the current voltage value through a mapping algorithm;
and converting the current voltage value based on a D/A conversion circuit arranged in the radio frequency signal generator to obtain an analog voltage signal, controlling according to the analog voltage signal, and outputting according to the pulse power.
The method for acquiring the pulse mode setting instruction comprises the steps of controlling an FPGA which is arranged in a radio frequency signal generator and connected with an ARM processor to enter a pulse mode, and specifically comprises the following steps:
when a pulse mode setting instruction issued by a PC end is received, transmitting the pulse mode setting instruction to an ARM processor;
the ARM processor is controlled to analyze the pulse mode setting instruction, and the analyzed pulse mode setting instruction is sent to an FPGA which is arranged in the radio frequency signal generator and connected with the ARM processor;
and when the FPGA is determined to receive the analyzed pulse mode setting instruction, controlling the FPGA to enter a pulse mode.
When the FPGA is in the pulse mode and a first designated level is detected, acquiring a pulse frequency generated by the FPGA, and obtaining a frequency pulse according to the pulse frequency, specifically including:
when the FPGA enters a pulse mode, a pulse calculator in the FPGA is controlled to identify the level generated in the pulse mode;
when the pulse calculator identifies a first designated level, controlling the pulse calculator to count, obtaining periodic variation of the first designated level, and obtaining corresponding pulse frequency according to the periodic variation;
acquiring parameters sent by an upper computer in a PC (personal computer) terminal, and acquiring frequency pulses generated by the pulse calculator according to the parameters and the pulse frequency;
the parameters include a frequency period and a division factor.
When the FPGA reaches a first designated pulse state in the frequency pulses, acquiring a current voltage value corresponding to the first designated pulse state through an A/D conversion circuit, and obtaining pulse power corresponding to the current voltage value through a mapping algorithm, wherein the method specifically comprises the following steps of:
after obtaining frequency pulses generated by a pulse calculator in the FPGA, when the FPGA reaches a first designated pulse state in the frequency pulses, converting the frequency pulses corresponding to the first designated pulse state by an A/D conversion circuit arranged in a radio frequency signal generator to obtain voltage values corresponding to the first designated pulse state;
reading the voltage value corresponding to the first designated pulse state for a plurality of times, and stopping reading when the voltage values are all in a preset range to obtain a current voltage value;
and obtaining the pulse power corresponding to the current voltage value through a mapping algorithm.
The method specifically includes the steps of:
inputting the current voltage value into a D/A conversion circuit arranged in a radio frequency signal generator for conversion, obtaining an analog voltage signal after conversion, controlling the analog voltage signal, and outputting according to the pulse power;
the value of the analog voltage signal = the present voltage value/4.
The D/A conversion circuit is arranged in the radio frequency signal generator, converts the current voltage value to obtain an analog voltage signal, controls the analog voltage signal, outputs the analog voltage signal according to the pulse power, and then further comprises:
controlling the temperature through the output of the pulse power;
when the temperature rises above a preset temperature threshold, the pulse frequency is reduced to a first preset threshold, and the output pulse power is controlled to be reduced;
and when the output of the pulse power is lower than a preset second threshold value, increasing the high level proportion in the pulse mode, and controlling the output pulse power to rise.
Wherein, the voltage value is: v=vr/4095×ad; v represents a voltage value, vr represents a reference voltage, and AD represents an AD value generated during A/D conversion.
The present invention also provides a computer readable storage medium storing a radio frequency power control program which when executed by a processor implements the steps of the radio frequency power control method as described above.
In summary, the present invention provides a radio frequency power control method and related devices, where the method includes: acquiring a pulse mode setting instruction, and controlling an FPGA which is arranged in a radio frequency signal generator and connected with an ARM processor to enter a pulse mode; when the FPGA is in the pulse mode and a first appointed level is detected, acquiring pulse frequency generated by the FPGA, and acquiring frequency pulses according to the pulse frequency; when the FPGA reaches a first designated pulse state in the frequency pulses, acquiring a current voltage value corresponding to the first designated pulse state through an A/D conversion circuit, and obtaining pulse power corresponding to the current voltage value through a mapping algorithm; and converting the current voltage value based on a D/A conversion circuit arranged in the radio frequency signal generator to obtain an analog voltage signal, controlling according to the analog voltage signal, and outputting according to the pulse power. The invention realizes the control of the pulse power by controlling the pulse frequency, and indirectly realizes the temperature control of the radio frequency signal generator, reduces the pulse frequency when the temperature rises, reduces the output radio frequency power, and improves the high pulse proportion in the pulse mode when the output radio frequency power can not meet the requirement, thereby not only meeting the requirement on the output radio frequency power, but also controlling the temperature in a reasonable range and greatly improving the time requirement on the radio frequency output.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal comprising the element.
Of course, those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by a computer program for instructing relevant hardware (e.g., processor, controller, etc.), the program may be stored on a computer readable storage medium, and the program may include the above described methods when executed. The computer readable storage medium may be a memory, a magnetic disk, an optical disk, etc.
It is to be understood that the invention is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.
Claims (9)
1. A radio frequency power control method, characterized in that the radio frequency power control method comprises:
acquiring a pulse mode setting instruction, and controlling an FPGA which is arranged in a radio frequency signal generator and connected with an ARM processor to enter a pulse mode;
when the FPGA is in the pulse mode and a first appointed level is detected, acquiring pulse frequency generated by the FPGA, and acquiring frequency pulses according to the pulse frequency;
when the FPGA reaches a first designated pulse state in the frequency pulses, acquiring a current voltage value corresponding to the first designated pulse state through an A/D conversion circuit, and obtaining pulse power corresponding to the current voltage value through a mapping algorithm;
when the FPGA reaches a first designated pulse state in the frequency pulses, acquiring a current voltage value corresponding to the first designated pulse state through an A/D conversion circuit, and obtaining pulse power corresponding to the current voltage value through a mapping algorithm, wherein the method specifically comprises the following steps of:
after obtaining frequency pulses generated by a pulse calculator in the FPGA, when the FPGA reaches a first designated pulse state in the frequency pulses, converting the frequency pulses corresponding to the first designated pulse state by an A/D conversion circuit arranged in a radio frequency signal generator to obtain voltage values corresponding to the first designated pulse state;
reading the voltage value corresponding to the first designated pulse state for a plurality of times, and stopping reading when the voltage values are all in a preset range to obtain a current voltage value;
the current voltage value is subjected to a mapping algorithm to obtain pulse power corresponding to the current voltage value;
and converting the current voltage value based on a D/A conversion circuit arranged in the radio frequency signal generator to obtain an analog voltage signal, controlling according to the analog voltage signal, and outputting according to the pulse power.
2. The method for controlling rf power according to claim 1, wherein the acquiring the pulse mode setting instruction controls the FPGA disposed in the rf signal generator and connected to the ARM processor to enter the pulse mode, specifically includes:
when a pulse mode setting instruction issued by a PC end is received, transmitting the pulse mode setting instruction to an ARM processor;
the ARM processor is controlled to analyze the pulse mode setting instruction, and the analyzed pulse mode setting instruction is sent to an FPGA which is arranged in the radio frequency signal generator and connected with the ARM processor;
and when the FPGA is determined to receive the analyzed pulse mode setting instruction, controlling the FPGA to enter a pulse mode.
3. The method according to claim 1, wherein when the FPGA is in the pulse mode and a first specified level is detected, acquiring a pulse frequency generated by the FPGA, and obtaining a frequency pulse according to the pulse frequency, specifically includes:
when the FPGA enters a pulse mode, a pulse calculator in the FPGA is controlled to identify the level generated in the pulse mode;
when the pulse calculator identifies a first designated level, controlling the pulse calculator to count, obtaining periodic variation of the first designated level, and obtaining corresponding pulse frequency according to the periodic variation;
acquiring parameters sent by an upper computer in a PC (personal computer) terminal, and acquiring frequency pulses generated by the pulse calculator according to the parameters and the pulse frequency;
the parameters include a frequency period and a division factor.
4. The method according to claim 1, wherein the converting the current voltage value based on a D/a conversion circuit provided in a radio frequency signal generator to obtain an analog voltage signal, and controlling according to the analog voltage signal, and outputting according to the pulse power, comprises:
inputting the current voltage value into a D/A conversion circuit arranged in a radio frequency signal generator for conversion, obtaining an analog voltage signal after conversion, controlling the analog voltage signal, and outputting according to the pulse power;
the value of the analog voltage signal = the present voltage value/4.
5. The method according to claim 1, wherein the converting the current voltage value based on a D/a converting circuit provided in a radio frequency signal generator to obtain an analog voltage signal, controlling according to the analog voltage signal, outputting according to the pulse power, and further comprising:
controlling the temperature through the output of the pulse power;
when the temperature rises above a preset temperature threshold, the pulse frequency is reduced to a first preset threshold, and the output pulse power is controlled to be reduced;
and when the output of the pulse power is lower than a preset second threshold value, increasing the high level proportion in the pulse mode, and controlling the output pulse power to rise.
6. The method of claim 1, wherein the voltage value is: v=vr/4095×ad; v represents a voltage value, vr represents a reference voltage, and AD represents an AD value generated during A/D conversion.
7. A radio frequency power control system, the radio frequency power control system comprising:
the pulse mode entering module is used for acquiring a pulse mode setting instruction and controlling an FPGA which is arranged in the radio frequency signal generator and connected with the ARM processor to enter a pulse mode;
the frequency pulse acquisition module is used for acquiring the pulse frequency generated by the FPGA when the FPGA is in the pulse mode and the first designated level is detected, and acquiring frequency pulses according to the pulse frequency;
the pulse power acquisition module is used for acquiring a current voltage value corresponding to a first designated pulse state through an A/D conversion circuit when the FPGA reaches the first designated pulse state in the frequency pulses, and acquiring pulse power corresponding to the current voltage value through a mapping algorithm;
when the FPGA reaches a first designated pulse state in the frequency pulses, acquiring a current voltage value corresponding to the first designated pulse state through an A/D conversion circuit, and obtaining pulse power corresponding to the current voltage value through a mapping algorithm, wherein the method specifically comprises the following steps of:
after obtaining frequency pulses generated by a pulse calculator in the FPGA, when the FPGA reaches a first designated pulse state in the frequency pulses, converting the frequency pulses corresponding to the first designated pulse state by an A/D conversion circuit arranged in a radio frequency signal generator to obtain voltage values corresponding to the first designated pulse state;
reading the voltage value corresponding to the first designated pulse state for a plurality of times, and stopping reading when the voltage values are all in a preset range to obtain a current voltage value;
the current voltage value is subjected to a mapping algorithm to obtain pulse power corresponding to the current voltage value;
the pulse power output module is used for converting the current voltage value based on a D/A conversion circuit arranged in the radio frequency signal generator to obtain an analog voltage signal, controlling according to the analog voltage signal and outputting according to the pulse power.
8. A radio frequency signal generator, the radio frequency signal generator comprising: memory, a processor and a radio frequency power control program stored on the memory and executable on the processor, which when executed by the processor, implements the steps of the radio frequency power control method according to any of claims 1-6.
9. A computer readable storage medium, characterized in that the computer readable storage medium stores a radio frequency power control program, which when executed by a processor, implements the steps of the radio frequency power control method according to any of claims 1-6.
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| CN102291104B (en) * | 2011-06-09 | 2013-12-11 | 电子科技大学 | High-power pulse current/voltage generating circuit |
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