CN116113070A - Method and apparatus in a node for wireless communication - Google Patents

Abstract

A method and apparatus in a node for wireless communication is disclosed. The first node receives first signaling, the first signaling being used to indicate a first set of REs; receiving second signaling, the second signaling being used to indicate a second set of REs; and transmitting the first bit block and the second bit block in the second RE set. The first RE set and the second RE set overlap in the time domain; the second set of REs comprises K subsets of REs; the first bit block is mapped to a number of REs in the K RE subsets not greater than a first constraint value, a product of a target value and a number of REs included in the target RE subset being used to determine the first constraint value; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the target value is a first value; the target value is a second value when the target RE subset belongs to only one of the K RE subsets.

Description

Method and apparatus in a node for wireless communication

Technical Field

The present application relates to a transmission method and apparatus in a wireless communication system, and more particularly, to a transmission method and apparatus for wireless signals in a wireless communication system supporting a cellular network.

Background

In the 5G system, in order to enhance coverage (coverage), WI (Work Item) of coverage enhancement (coverage) of the Release 17 is passed through NR (New Radio) on the 3GPP (3 rd Generation Partner Project, third generation partnership project) RAN (Radio Access Network ) #90e full. How to enhance the coverage of PUSCH (Physical Uplink Shared CHannel ) and PUCCH (Physical Uplink Control CHannel, physical uplink control channel) transmissions is an important study therein.

Disclosure of Invention

The inventors have found through research that when two resources reserved for two transmissions collide, bits of one transmission can be multiplexed over some REs in the other transmission, and how to determine the number of those REs is a critical issue.

In view of the above, the present application discloses a solution. It should be noted that, although the above description uses uplink as an example, the present application is also applicable to other scenarios such as downlink and accompanying link (sidlink), and achieves technical effects similar to those in uplink. Furthermore, the adoption of unified solutions for different scenarios (including but not limited to uplink, downlink and companion links) also helps to reduce hardware complexity and cost. Embodiments and features of embodiments in any node of the present application may be applied to any other node and vice versa without conflict. The embodiments of the present application and features in the embodiments may be combined with each other arbitrarily without conflict.

As an example, the term (terminality) in the present application is explained with reference to the definition of the 3GPP specification protocol TS36 series.

As an embodiment, the term in the present application is explained with reference to the definition of the 3GPP specification protocol TS38 series.

As an embodiment, the term in the present application is explained with reference to the definition of the 3GPP specification protocol TS37 series.

As one example, the term in the present application is explained with reference to the definition of the specification protocol of IEEE (Institute of Electrical and Electronics Engineers ).

The application discloses a method used in a first node of wireless communication, comprising the following steps:

receiving first signaling, the first signaling being used to indicate a first set of REs;

receiving second signaling, the second signaling being used to indicate a second set of REs;

transmitting a first bit block and a second bit block in the second RE set;

wherein the first RE set is reserved for the first bit block, the second RE set is reserved for the second bit block, and the first RE set and the second RE set overlap in the time domain; the second set of REs comprises K subsets of REs, K being a positive integer greater than 1; any two RE subsets of the K RE subsets are orthogonal in the time domain, and the first bit block is mapped to at least one RE subset of the K RE subsets; the first bit block is mapped to a number of REs in the K RE subsets not greater than a first constraint value, a product of a target value and a number of REs included in a target RE subset is used to determine the first constraint value, and the second RE set includes the target RE subset; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the target value is a first value; the target value is a second value when the target RE subset belongs to only one of the K RE subsets.

As one embodiment, the problems to be solved by the present application include: when two resources reserved for two transmissions collide in the time domain, the bits of one transmission are multiplexed onto some REs in the other transmission, how the number of REs is determined.

As an embodiment, the essence of the method is that: the first bit block is multiplexed into the resource reserved for the second bit block (i.e., the second RE set), and the first constraint value is the maximum number of REs that can be used for bit multiplexing in consideration of the transmission reliability of the second bit block, so setting a suitable first constraint value is a key point of bit multiplexing; the first constraint value and the target value are related to a product of the number of REs comprised by the target RE subset, and the target value is related to the target RE subset. The method has the advantages that under the two different conditions that the target RE subset belongs to a plurality of RE subsets and only one RE subset, proper target values are respectively set, so that proper maximum RE quantity for bit multiplexing is obtained, the problem of conflict between two transmissions is solved, and the reliable transmission of bit blocks of the two transmissions is ensured.

According to an aspect of the application, when the K RE subsets are jointly used to determine the size of the second bit block, the target RE subset belongs to a plurality of RE subsets of the K RE subsets; when only one of the K RE subsets is used to determine the size of the second bit block, the target RE subset belongs to only one of the K RE subsets.

According to an aspect of the application, when the K RE subsets are jointly used for determining the size of the second bit block, the K RE subsets are jointly used for transmitting one repetition of the second bit block; when only one of the K RE subsets is used to determine the size of the second bit block, the K RE subsets are used to transmit K repetitions of the second bit block, respectively.

According to one aspect of the application, the first value is one value of a first set and the second value is one value of a second set, the first set and the second set being different; the first set includes more than one value and the second set includes more than one value.

According to an aspect of the application, the number of REs in the K RE subsets mapped to the first bit block is not greater than a minimum of a first reference value and the first constraint value; the second signaling indicates a first offset, which is used to determine the first reference value.

According to an aspect of the application, the product of the first offset and the number of REs comprised by a reference RE subset comprising the target RE subset is used to determine the first reference value; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the reference RE subset belongs to a plurality of RE subsets of the K RE subsets; when the target RE subset belongs to only one of the K RE subsets, the reference RE subset belongs to only one of the K RE subsets.

According to an aspect of the application, the first bit block is mapped to only a first subset of REs out of the K subsets of REs, the first subset of REs being one of the K subsets of REs, the number of REs of the first bit block mapped to the K subsets of REs being the number of REs of the first bit block mapped to the first subset of REs; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the number of REs in the first bit block mapped to the first RE subset is equal to a minimum of the first reference value, the first constraint value, and a second constraint value; the second constraint value is not greater than a number of REs included in the first subset of REs.

The application discloses a method used in a second node of wireless communication, comprising the following steps:

transmitting first signaling, the first signaling being used to indicate a first set of REs;

transmitting second signaling, the second signaling being used to indicate a second set of REs;

receiving a first block of bits and a second block of bits in the second set of REs;

wherein the first RE set is reserved for the first bit block, the second RE set is reserved for the second bit block, and the first RE set and the second RE set overlap in the time domain; the second set of REs comprises K subsets of REs, K being a positive integer greater than 1; any two RE subsets of the K RE subsets are orthogonal in the time domain, and the first bit block is mapped to at least one RE subset of the K RE subsets; the first bit block is mapped to a number of REs in the K RE subsets not greater than a first constraint value, a product of a target value and a number of REs included in a target RE subset is used to determine the first constraint value, and the second RE set includes the target RE subset; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the target value is a first value; the target value is a second value when the target RE subset belongs to only one of the K RE subsets.

According to an aspect of the application, when the K RE subsets are jointly used to determine the size of the second bit block, the target RE subset belongs to a plurality of RE subsets of the K RE subsets; when only one of the K RE subsets is used to determine the size of the second bit block, the target RE subset belongs to only one of the K RE subsets.

According to an aspect of the application, when the K RE subsets are jointly used for determining the size of the second bit block, the K RE subsets are jointly used for transmitting one repetition of the second bit block; when only one of the K RE subsets is used to determine the size of the second bit block, the K RE subsets are used to transmit K repetitions of the second bit block, respectively.

According to one aspect of the application, the first value is one value of a first set and the second value is one value of a second set, the first set and the second set being different; the first set includes more than one value and the second set includes more than one value.

According to an aspect of the application, the number of REs in the K RE subsets mapped to the first bit block is not greater than a minimum of a first reference value and the first constraint value; the second signaling indicates a first offset, which is used to determine the first reference value.

According to an aspect of the application, the product of the first offset and the number of REs comprised by a reference RE subset comprising the target RE subset is used to determine the first reference value; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the reference RE subset belongs to a plurality of RE subsets of the K RE subsets; when the target RE subset belongs to only one of the K RE subsets, the reference RE subset belongs to only one of the K RE subsets.

According to an aspect of the application, the first bit block is mapped to only a first subset of REs out of the K subsets of REs, the first subset of REs being one of the K subsets of REs, the number of REs of the first bit block mapped to the K subsets of REs being the number of REs of the first bit block mapped to the first subset of REs; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the number of REs in the first bit block mapped to the first RE subset is equal to a minimum of the first reference value, the first constraint value, and a second constraint value; the second constraint value is not greater than a number of REs included in the first subset of REs.

The application discloses a first node device for wireless communication, comprising:

a first receiver that receives first signaling, the first signaling being used to indicate a first set of REs; receiving second signaling, the second signaling being used to indicate a second set of REs;

a first transmitter transmitting a first bit block and a second bit block in the second RE set;

wherein the first RE set is reserved for the first bit block, the second RE set is reserved for the second bit block, and the first RE set and the second RE set overlap in the time domain; the second set of REs comprises K subsets of REs, K being a positive integer greater than 1; any two RE subsets of the K RE subsets are orthogonal in the time domain, and the first bit block is mapped to at least one RE subset of the K RE subsets; the first bit block is mapped to a number of REs in the K RE subsets not greater than a first constraint value, a product of a target value and a number of REs included in a target RE subset is used to determine the first constraint value, and the second RE set includes the target RE subset; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the target value is a first value; the target value is a second value when the target RE subset belongs to only one of the K RE subsets.

The application discloses a second node device used for wireless communication, which is characterized by comprising:

a second transmitter that receives first signaling, the first signaling being used to indicate a first set of REs; receiving second signaling, the second signaling being used to indicate a second set of REs;

a second receiver transmitting a first bit block and a second bit block in the second RE set;

wherein the first RE set is reserved for the first bit block, the second RE set is reserved for the second bit block, and the first RE set and the second RE set overlap in the time domain; the second set of REs comprises K subsets of REs, K being a positive integer greater than 1; any two RE subsets of the K RE subsets are orthogonal in the time domain, and the first bit block is mapped to at least one RE subset of the K RE subsets; the first bit block is mapped to a number of REs in the K RE subsets not greater than a first constraint value, a product of a target value and a number of REs included in a target RE subset is used to determine the first constraint value, and the second RE set includes the target RE subset; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the target value is a first value; the target value is a second value when the target RE subset belongs to only one of the K RE subsets.

As an example, compared to the conventional solution, the present application has the following advantages:

-setting the appropriate parameter values in different transmission cases, respectively, resulting in an appropriate maximum number of REs for bit multiplexing.

Both solving the problem of collision between two transmissions and ensuring that the bit blocks of both transmissions are transmitted reliably.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the following drawings in which:

fig. 1 shows a flow chart of a first signaling, a second signaling, a first bit block and a second bit block according to one embodiment of the present application;

FIG. 2 shows a schematic diagram of a network architecture according to one embodiment of the present application;

fig. 3 shows a schematic diagram of an embodiment of a radio protocol architecture of a user plane and a control plane according to one embodiment of the present application;

FIG. 4 shows a schematic diagram of a first communication device and a second communication device according to one embodiment of the present application;

FIG. 5 illustrates a flow chart of transmissions according to one embodiment of the present application;

FIG. 6 illustrates a schematic diagram of a size of a second bit block according to one embodiment of the present application;

FIG. 7 shows a schematic diagram of a relationship between K RE subsets and a second bit block, according to one embodiment of the present application;

FIG. 8 illustrates a schematic diagram of a first value and a second value according to one embodiment of the present application;

FIG. 9 shows a schematic diagram of a first bit block being mapped to the number of REs in K subsets of REs, according to one embodiment of the present application;

FIG. 10 illustrates a schematic diagram of a first reference value according to one embodiment of the present application;

FIG. 11 illustrates a schematic diagram of a first bit block being mapped to a number of REs in a first subset of REs, according to one embodiment of the present application;

fig. 12 shows a block diagram of a processing arrangement for use in a first node device according to an embodiment of the present application;

fig. 13 shows a block diagram of a processing arrangement for a device in a second node according to an embodiment of the present application.

Detailed Description

The technical solution of the present application will be further described in detail with reference to the accompanying drawings, and it should be noted that, without conflict, the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other.

Example 1

Embodiment 1 illustrates a flow chart of a first signaling, a second signaling, a first bit block and a second bit block according to one embodiment of the present application, as shown in fig. 1. In 100 shown in fig. 1, each block represents a step.

In embodiment 1, the first node in the present application receives first signaling in step 101; receiving a second signaling in step 102; transmitting the first bit block and the second bit block in the second RE set in step 103; wherein the first signaling is used to indicate a first set of REs; the second signaling is used to indicate a second set of REs; the first RE set is reserved for the first bit block, the second RE set is reserved for the second bit block, and the first RE set and the second RE set overlap in the time domain; the second set of REs comprises K subsets of REs, K being a positive integer greater than 1; any two RE subsets of the K RE subsets are orthogonal in the time domain, and the first bit block is mapped to at least one RE subset of the K RE subsets; the first bit block is mapped to a number of REs in the K RE subsets not greater than a first constraint value, a product of a target value and a number of REs included in a target RE subset is used to determine the first constraint value, and the second RE set includes the target RE subset; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the target value is a first value; the target value is a second value when the target RE subset belongs to only one of the K RE subsets.

As an embodiment, the transmission of the first signaling is earlier than the transmission of the second signaling.

As an embodiment, the transmission of the first signaling is not earlier than the transmission of the second signaling.

As an embodiment, the second signaling is sent earlier than the first signaling.

As an embodiment, the second signaling is sent no earlier than the first signaling.

As an embodiment, the first signaling is physical layer signaling.

As an embodiment, the first signaling is DCI (downlink control information ) signaling.

As an embodiment, the first signaling is higher layer signaling.

As an embodiment, the first signaling is RRC signaling.

As an embodiment, the first signaling is MAC CE signaling.

As an embodiment, the higher layer signaling is RRC signaling.

As an embodiment, the higher layer signaling is MAC CE signaling.

As an embodiment, the first bit block includes UCI (Uplink Control Information ).

As an embodiment, the first bit block includes HARQ-ACK (Hybrid Automatic Repeat reQuest-Acknowledgement, hybrid automatic repeat request Acknowledgement).

As an embodiment, the first bit block includes at least one of HARQ-ACK, SR (Scheduling Request ) or CSI (Channel State Information, channel state information).

As an embodiment, the CSI includes at least one of CRI (Channel-state information reference signal Resource Indicator, channel state information reference signal resource identifier), SSBRI (Synchronization Signal/physical broadcast Channel Block Resource Indicator, synchronization/physical broadcast Channel block resource identifier), LI (Layer Indicator, layer identifier), PMI (Precoding Matrix Indicator, precoding matrix identifier), CQI (Channel Quality Indicator, channel quality identifier), L1-RSRP (Layer 1Reference Signal Received Power, layer 1-reference signal received power), L1-RSRQ (Layer 1Reference Signal Received Quality, layer 1-reference signal received quality), or L1-SINR (Layer 1Signal to Interference and Noise Ratio, layer 1-signal to interference and noise ratio).

As an embodiment, the first set of REs comprises at least one RE.

As an embodiment, the first set of REs consists of all REs occupied by one PUCCH (Physical Uplink Control CHannel ) resource.

As an embodiment, the first set of REs consists of all REs occupied by one PUCCH resource reserved for the first bit block.

As an embodiment, the meaning of the sentence "the first RE set is reserved for the first bit block" includes: the first set of REs is configured to the first bit block.

As an embodiment, the meaning of the sentence "the first RE set is reserved for the first bit block" includes: the first set of REs is indicated to the first bit block.

As an embodiment, the meaning of the sentence "the first RE set is reserved for the first bit block" includes: at a transmission instant of the first signaling, the first set of REs is scheduled for transmission of the first block of bits.

As an embodiment, the meaning of the sentence "the first RE set is reserved for the first bit block" includes: the actual transmission of the first block of bits occupies some or all of the REs in the first set of REs.

As an embodiment, the meaning of the sentence "the first RE set is reserved for the first bit block" includes: the actual transmission of the first block of bits does not occupy the first set of REs.

As an embodiment, the meaning of the sentence "the first RE set is reserved for the first bit block" includes: in effect, the first bit block is discarded from transmission.

As an embodiment, the first signaling explicitly indicates a first RE (Resource Element) set.

As an embodiment, the first signaling implicitly indicates the first RE set.

As an embodiment, the first signaling indicates a symbol occupied by the first set of REs in a time domain and a subcarrier occupied by the first set of REs in a frequency domain.

As an embodiment, the first signaling indicates a symbol occupied by the first RE set in a time domain and an RB (Resource Block) occupied by the first RE set in a frequency domain.

As an embodiment, the first signaling includes a first field (field), the first field in the first signaling being used to indicate the first set of REs; the first field includes at least one bit.

As a sub-embodiment of the above embodiment, the first field in the first signaling indicates an index of the first RE set in a reference RE pool, the reference RE pool comprising at least one RE set, the first RE set being one RE set in the reference RE pool, one of the RE sets comprising at least one RE.

As a sub-embodiment of the foregoing embodiment, the first field in the first signaling indicates an index of a first air-interface resource set in a reference air-interface resource pool, where the reference air-interface resource pool includes at least one air-interface resource set, and the first air-interface resource set is one air-interface resource set in the reference air-interface resource pool, and the first RE set is composed of all REs occupied by the first air-interface resource set in a time-frequency domain, and one air-interface resource set includes at least one RE in the time-frequency domain.

As a sub-embodiment of the above embodiment, the first field in the first signaling indicates an index of a first PUCCH resource in one PUCCH resource set, the one PUCCH resource set including at least one PUCCH resource, the first PUCCH resource being one PUCCH resource in the one PUCCH resource set, the first RE set being composed of all REs occupied by the first PUCCH resource in a time-frequency domain, and the one PUCCH resource including at least one RE in the time-frequency domain.

As a sub-embodiment of the above embodiment, the first domain is a PUCCH resource indicator domain.

As one example, the phrase "used to indicate" refers to: an explicit indication.

As one example, the phrase "used to indicate" refers to: implicit indication.

As one example, the phrase "used to indicate" refers to: direct indication.

As one example, the phrase "used to indicate" refers to: an indirect indication.

For a specific definition of the PUCCH resource indicator domain, see section 7.3.1 of 3gpp ts38.212, for an embodiment.

As an embodiment, one RE occupies one symbol in the time domain and one subcarrier in the frequency domain.

As an embodiment, the symbol is a multicarrier symbol.

As an embodiment, the symbol is a single carrier symbol.

As an embodiment, the multi-carrier symbol is an OFDM (Orthogonal Frequency Division Multiplexing ) symbol.

As an embodiment, the multi-Carrier symbol is an SC-FDMA (Single Carrier-Frequency Division Multiple Access, single Carrier frequency division multiple access) symbol.

As an embodiment, the multi-carrier symbol is a DFT-S-OFDM (Discrete Fourier Transform Spread OFDM, discrete fourier transform orthogonal frequency division multiplexing) symbol.

As an embodiment, the multi-carrier symbol is an FBMC (Filter Bank Multi Carrier, filter bank multi-carrier) symbol.

As an embodiment, the multicarrier symbol includes CP (Cyclic Prefix).

As an embodiment, the first bit block includes HARQ-ACK (Hybrid Automatic Repeat reQuest-Acknowledgement, hybrid automatic repeat request Acknowledgement) associated with the first signaling.

As an embodiment, the HARQ-ACK associated with the first signaling comprises a NACK.

As an embodiment, the HARQ-ACK associated with the first signaling comprises an ACK or NACK.

As an embodiment, the HARQ-ACK associated with the first signaling indicates whether each bit in the set of bit blocks scheduled by the first signaling was received correctly.

As a sub-embodiment of the above embodiment, the set of bit blocks scheduled by the first signaling includes one TB (Transport Block).

As a sub-embodiment of the above embodiment, the set of bit blocks scheduled by the first signaling includes at least one TB.

As a sub-embodiment of the above embodiment, the set of bit blocks scheduled by the first signaling includes at least one CB (Code Block).

As a sub-embodiment of the above embodiment, the set of bit blocks scheduled by the first signaling includes at least one CBG (Code Block Group).

As an embodiment, the HARQ-ACK associated with the first signaling indicates whether the first signaling was received correctly.

As an embodiment, the first signaling is used to indicate SPS (Semi-Persistent Scheduling, quasi-persistent scheduling) Release (Release), and the HARQ-ACK associated with the first signaling indicates whether the first signaling is received correctly.

As an embodiment, the first signaling is used to schedule PDSCH (Physical Downlink Shared Channel ), and the HARQ-ACK associated with the first signaling indicates whether the PDSCH scheduled by the first signaling was received correctly.

As one embodiment, the first receiver receives a first signal; wherein the first signaling is used to indicate time-frequency resources occupied by the first signal, and the first bit block includes HARQ-ACKs for the first signal.

As a sub-embodiment of the above embodiment, the first bit block includes HARQ-ACKs associated with the first signaling, the HARQ-ACKs associated with the first signaling being HARQ-ACKs for the first signal.

As a sub-embodiment of the above embodiment, the transmission channel of the first signal is DL-SCH (Downlink Shared Channel ).

As a sub-embodiment of the above embodiment, the first signal is transmitted on PDSCH.

As a sub-embodiment of the above embodiment, the first signal carries a set of blocks of bits.

As a sub-embodiment of the above embodiment, the first signal carries a TB.

As a sub-embodiment of the above embodiment, the first signal carries at least one TB.

As a sub-embodiment of the above embodiment, the first signal carries at least one CB.

As a sub-embodiment of the above embodiment, the first signal carries at least one CBG (Code Block Group).

As a sub-embodiment of the above embodiment, the first signal carries a set of bit blocks scheduled by the first signaling.

As a sub-embodiment of the above embodiment, the first bit block indicates whether each bit block carried by the first signal is received correctly.

As a sub-embodiment of the above embodiment, the first signaling indicates a time domain resource occupied by the first signal and a frequency domain resource occupied by the first signal.

As a sub-embodiment of the above embodiment, the first signaling includes a second domain and a third domain, the second domain in the first signaling indicates a time domain resource occupied by the first signal, and the third domain in the first signaling indicates a frequency domain resource occupied by the first signal.

As a sub-embodiment of the above embodiment, the first signaling includes a second domain and a third domain, the second domain in the first signaling indicates a symbol occupied by the first signal, and the third domain in the first signaling indicates that the first signal occupies an RB.

As an embodiment, one set of bit blocks comprises at least one bit block and one bit block comprises at least one bit.

As an embodiment, the second signaling is physical layer signaling.

As an embodiment, the second signaling is DCI signaling.

As an embodiment, the second signaling is higher layer signaling.

As an embodiment, the second signaling is RRC signaling.

As an embodiment, the second signaling is MAC CE signaling.

As an embodiment, the second set of REs comprises at least K REs.

As an embodiment, the second set of REs comprises a plurality of REs.

As an embodiment, any one of the K RE subsets comprises at least one RE.

As an embodiment, the second set of REs comprises only K RE subsets.

As an embodiment, the second set of REs further comprises at least one RE outside the K RE subsets.

As an embodiment, the K RE subsets belong to K slots (slots) in the time domain, respectively.

As an embodiment, the K RE subsets respectively belong to K consecutive slots (slots) in the time domain.

As an embodiment, the K RE subsets belong to K available slots (slots) in the time domain, respectively.

As an embodiment, the K RE subsets respectively belong to K consecutive available (slots) in the time domain.

As an embodiment, any one of the K RE subsets comprises one symbol or a plurality of consecutive symbols in the time domain.

As an embodiment, the number of symbols respectively included in the K RE subsets in the time domain is the same, and the number of RBs respectively included in the K RE subsets in the frequency domain is the same.

As an embodiment, the number of symbols respectively included in the K RE subsets in the time domain is the same, and the number of subcarriers respectively included in the K RE subsets in the frequency domain is the same.

As an embodiment, any two RE subsets of the K RE subsets do not include one same symbol in the time domain.

As an embodiment, at least one symbol in one of the available slots is an uplink symbol.

As an embodiment, one of the available time slots is an uplink time slot.

As an embodiment, any symbol in one of the available slots is an uplink symbol.

As an embodiment, in the K available slots, symbols occupied by the K RE subsets in the time domain are all uplink symbols.

As an embodiment, the second set of REs consists of all REs occupied by one PUSCH (Physical Uplink Shared CHannel ).

As an embodiment, the second set of REs consists of all REs occupied by one PUSCH reserved for the second bit block.

As an embodiment, the meaning of the sentence "the second RE set is reserved for the second bit block" includes: the second set of REs is configured to the second block of bits.

As an embodiment, the meaning of the sentence "the second RE set is reserved for the second bit block" includes: the second set of REs is indicated to the second block of bits.

As an embodiment, the meaning of the sentence "the second RE set is reserved for the second bit block" includes: at the time of transmission of the second signaling, the second set of REs is scheduled for transmission of the second block of bits.

As an embodiment, the meaning of the sentence "the second RE set is reserved for the second bit block" includes: the actual transmission of the second block of bits occupies some or all of the REs in the second set of REs.

As an embodiment, the second bit block comprises a TB.

As an embodiment, the second bit block comprises at least one TB.

As an embodiment, the second bit block includes at least one CB.

As an embodiment, the second bit block comprises at least one CBG.

As an embodiment, the meaning of the sentence "the second RE set is reserved for the second bit block" includes: the second set of REs are commonly used for transmitting one repetition of the second block of bits.

As an embodiment, the meaning of the sentence "the second signaling is used to indicate the second RE set" includes: the second signaling includes a second domain and a third domain, the second domain in the second signaling indicates time domain resources occupied by the second RE set, and the third domain in the second signaling indicates frequency domain resources occupied by the second RE set.

As an embodiment, the meaning of the sentence "the second signaling is used to indicate the second RE set" includes: the second signaling includes a second domain and a third domain, the second domain in the second signaling indicates time domain resources occupied by an earliest subset of REs in the second set of REs, and the third domain in the second signaling indicates frequency domain resources occupied by the earliest subset of REs in the second set of REs.

As an embodiment, the meaning of the sentence "the second signaling is used to indicate the second RE set" includes: the second signaling includes a second domain and a third domain, the second domain in the second signaling indicates time domain resources occupied by an earliest subset of REs in the second set of REs and the K, and the third domain in the second signaling indicates frequency domain resources occupied by the earliest subset of REs in the second set of REs.

As an embodiment, the meaning of the sentence "the second signaling is used to indicate the second RE set" includes: the second signaling is used to indicate M sets of REs, the second set of REs being one of the M sets of REs, M being a positive integer greater than 1.

As an embodiment, the meaning of the sentence "the second signaling is used to indicate the second RE set" includes: the second signaling includes a second domain and a third domain, the second domain in the second signaling indicates time domain resources occupied by an earliest set of REs of M sets of REs, the second set of REs is one of the M sets of REs, M is a positive integer greater than 1, and the third domain in the second signaling indicates frequency domain resources occupied by the earliest set of REs of the M sets of REs.

As an embodiment, the meaning of the sentence "the second signaling is used to indicate the second RE set" includes: the second signaling includes a second domain and a third domain, the second domain in the second signaling indicates a time domain resource occupied by an earliest set of REs of M sets of REs and M, the second set of REs is one of the M sets of REs, M is a positive integer greater than 1, and the third domain in the second signaling indicates a frequency domain resource occupied by the earliest set of REs of the M sets of REs.

As an embodiment, the meaning of the sentence "the second signaling is used to indicate the second RE set" includes: the second signaling includes a second domain and a third domain, the second domain in the second signaling indicating time domain resources occupied by an earliest subset of REs of M sets of REs, the second set of REs being one of the M sets of REs, M being a positive integer greater than 1, the third domain in the second signaling indicating frequency domain resources occupied by the earliest subset of REs of the M sets of REs.

As an embodiment, the meaning of the sentence "the second signaling is used to indicate the second RE set" includes: the second signaling includes a second domain and a third domain, the second domain in the second signaling indicating time domain resources occupied by an earliest subset of REs in M sets of REs, the K and M, the second set of REs being one of the M sets of REs, the M being a positive integer greater than 1, the third domain in the second signaling indicating frequency domain resources occupied by the earliest subset of REs in the M sets of REs.

As an embodiment, the phrase "occupied time domain resource" refers to: time taken up.

As an embodiment, the phrase "occupied time domain resource" refers to: occupied symbols.

As an embodiment, the phrase "occupied frequency domain resource" refers to: occupied subcarriers.

As an embodiment, the phrase "occupied frequency domain resource" refers to: and occupied RB.

As an embodiment, any two of the M RE sets are orthogonal in the time domain, any one of the M RE sets includes at least one RE subset, and one of the RE subsets includes at least one RE.

As an embodiment, any two of the M RE sets are orthogonal in the time domain, any one of the M RE sets includes at least one RE subset, the number of RE subsets included in any one of the M RE sets is the same, and one of the RE subsets includes at least one RE.

As an embodiment, any one of the M RE sets includes at least one RE subset, the number of RE subsets included in any one of the M RE sets is equal to the K, MK RE subsets in the M RE sets respectively belong to MK slots, and the number of REs included in the MK RE subsets respectively is the same.

As an embodiment, any one of the M RE sets includes at least one RE subset, the number of RE subsets included in any one of the M RE sets is equal to the K, MK RE subsets in the M RE sets respectively belong to MK available timeslots, and the number of REs included in the MK RE subsets respectively is the same.

As an embodiment, the second signaling indicates the K.

As an embodiment, the second signaling includes a second field, the second field in the second signaling indicating the K.

As an embodiment, the second signaling indicates the M and the K.

As an embodiment, the second domain is Time domain resource assignment domain and the third domain is Frequency domain resource assignment domain.

For an embodiment, the specific definition of the Time domain resource assignment domain is described in 3GPP TS38.212 section 7.3, and the specific definition of the Frequency domain resource assignment domain is described in 3GPP TS38.212 section 7.3.

As an embodiment, the second set of REs are commonly used for transmitting one repetition of the second bit block, and the M sets of REs are respectively used for transmitting M repetitions of the second bit block.

As an embodiment, the second set of REs includes at least one symbol that the first set of REs includes in the time domain.

As an embodiment, only a first subset of REs of the first set of REs and the second set of REs overlap in the time domain, the first subset of REs being one of the K subsets of REs.

As an embodiment, the meaning of the sentence "the first bit block is mapped to at least one RE subset of the K RE subsets" means that: the first bit block is mapped to only one of the K RE subsets.

As an embodiment, the meaning of the sentence "the first bit block is mapped to at least one RE subset of the K RE subsets" means that: the first bit block is mapped to a plurality of RE subsets of the K RE subsets.

As an embodiment, the meaning of the sentence "the first bit block is mapped to at least one RE subset of the K RE subsets" means that: the first bit block is mapped to some or all of the K RE subsets.

As an embodiment, the meaning of the sentence "the first bit block is mapped to at least one RE subset of the K RE subsets" means that: the first bit block is rate matched and modulated and then mapped to at least one of the K RE subsets.

As an embodiment, only a first subset of REs of the first set of REs and the second set of REs overlap in the time domain; the first bit block is mapped to only a first subset of REs out of the K subsets of REs, the first subset of REs being one of the K subsets of REs; the number of REs of the K RE subsets to which the first bit block is mapped is the number of REs of the first RE subset to which the first bit block is mapped.

As one embodiment, the first bit block is mapped to a plurality of RE subsets of the K RE subsets; the number of REs of the K RE subsets to which the first bit block is mapped is the number of REs of the plurality of RE subsets to which the first bit block is mapped.

As an embodiment, the first bit block is mapped to only a first subset of REs out of the K subsets of REs, the first subset of REs being one of the K subsets of REs; the number of REs of the K RE subsets to which the first bit block is mapped is the number of REs of the first RE subset to which the first bit block is mapped; the first bit block is mapped to at least one RE in the first RE subset.

As one embodiment, the first bit block is mapped to a plurality of RE subsets of the K RE subsets; the number of REs of the K RE subsets to which the first bit block is mapped is the number of REs of the plurality of RE subsets to which the first bit block is mapped; the first bit block is mapped to at least one RE in each of the plurality of RE subsets.

As an embodiment, the number of REs of the K RE subsets to which the first bit block is mapped is smaller than the total number of REs of the K RE subsets.

As an embodiment, the number of REs of the K RE subsets to which the first bit block is mapped is not greater than a total number of REs of the K RE subsets.

As an embodiment, the number of REs in the first bit block mapped to the second set of REs is not greater than the total number of REs in the second set of REs.

As an embodiment, the number of REs in the first bit block mapped to the second set of REs is less than the total number of REs in the second set of REs.

As an embodiment, the number of REs in the K RE subsets mapped to the first bit block is equal to a minimum of a first constraint value and J reference values, J being a positive integer greater than 1.

As a sub-embodiment of the above embodiment, J is equal to 2.

As a sub-embodiment of the above embodiment, the J is greater than 2.

As a sub-embodiment of the above embodiment, the J is equal to 2, and the first reference value is one of the J reference values.

As a sub-embodiment of the above embodiment, the J is equal to 2, and the J reference values include the first reference value and the second limit value.

As a sub-embodiment of the above embodiment, the J reference values are all non-negative integers.

As a sub-embodiment of the above embodiment, the J reference values are all positive integers.

As an embodiment, the meaning of the sentence "the first bit block is mapped to at least one RE subset of the K RE subsets after rate matching and modulation" includes: the first bit block is mapped to at least one of the K RE subsets after only one rate matching and modulation.

As an embodiment, the meaning of the sentence "the first bit block is mapped to at least one RE subset of the K RE subsets after rate matching and modulation" includes: the first bit block is mapped to at least one of the K RE subsets after at least one rate matching and modulation, respectively.

As an embodiment, the meaning of the sentence "the first bit block is mapped to at least one RE subset of the K RE subsets after rate matching and modulation" includes: the first bit block is mapped to K1 RE subsets among the K RE subsets after rate matching and modulation K1 times, respectively, K1 being a positive integer greater than 1 and not greater than the K.

As an embodiment, the meaning of "the first bit block is mapped to at least one RE subset of the K RE subsets after rate matching and modulation" includes: the first bit block is mapped to at least one of the K RE subsets after at least code block segmentation (Code Block Segmentation), CRC attachment, channel coding, rate matching, code block Concatenation (Concatenation) and modulation.

As an embodiment, the meaning of "the first bit block is mapped to at least one RE subset of the K RE subsets after rate matching and modulation" includes: the first bit block is mapped to at least one of the K RE subsets after at least code block segmentation (Code Block Segmentation), CRC attachment, channel coding, rate matching, code block Concatenation (Concatenation), scrambling and modulation.

As an embodiment, the meaning of "the first bit block is mapped to at least one RE subset of the K RE subsets after rate matching and modulation" includes: the first bit block is mapped to at least one of the K RE subsets after at least code block segmentation (Code Block Segmentation), CRC attachment, channel coding, rate matching, code block Concatenation (Concatenation), scrambling, modulation and antenna port mapping.

As an embodiment, the second bit block is mapped to the second set of REs.

As an embodiment, the number of REs in the second set of REs to which the second block of bits is mapped is not greater than the total number of REs in the second set of REs.

As an embodiment, the number of REs in the second set of REs to which the second block of bits is mapped is less than the total number of REs in the second set of REs.

As an embodiment, the number of all REs in the second set of REs to which the second bit block and the first bit block are mapped is not greater than the total number of REs in the second set of REs.

As an embodiment, the meaning of the sentence "the second bit block is mapped to the second RE set" includes: the second bit block is mapped to each of the K RE subsets.

As an embodiment, the meaning of the sentence "the second bit block is mapped to the second RE set" includes: the second bit block is mapped to at least one of the K RE subsets.

As an embodiment, the second bit block is mapped to the second RE set after rate matching and modulation.

As an embodiment, the meaning of the sentence "the second bit block is mapped to the second RE set after rate matching and modulation" includes: the second bit block is mapped to each of the K RE subsets after rate matching and modulation.

As an embodiment, the meaning of the sentence "the second bit block is mapped to the second RE set after rate matching and modulation" includes: the second bit block is mapped to at least one of the K RE subsets after rate matching and modulation.

As an embodiment, the meaning of the sentence "the second bit block is mapped to the second RE set after rate matching and modulation" includes: the second bit block is mapped to the second set of REs after only one rate matching and modulation.

As an embodiment, the meaning of the sentence "the second bit block is mapped to the second RE set after rate matching and modulation" includes: the second bit block is mapped to the K RE subsets after K times of rate matching and modulation, respectively.

As an embodiment, the rate matching of the sentence "the second bit block is mapped to the second RE set after rate matching and modulation" is performed per slot.

As an embodiment, the rate matching of the sentence "the second bit block is mapped to the second RE set after rate matching and modulation" is performed in the K RE subsets, respectively.

As an embodiment, the rate matching of the sentence "the second bit block is mapped into the second RE set after rate matching and modulation" is per-slot rate matching.

As an embodiment, the meaning of "the second bit block is mapped to the second RE set after rate matching and modulation" includes: the second bit block is mapped to the second RE set after at least CRC (Cyclic Redundancy Check), cyclic Redundancy Check (CRC) attachment, code block segmentation (Code Block Segmentation), code block CRC attachment, channel coding, rate matching, code block Concatenation (Concatenation), scrambling, and modulation.

As an embodiment, the meaning of "the second bit block is mapped to the second RE set after rate matching and modulation" includes: the second bit block is mapped to the second set of REs after at least CRC (Cyclic Redundancy Check ) attachment (attachment), code block segmentation (Code Block Segmentation), code block CRC attachment, channel coding, rate matching, code block Concatenation (Concatenation), scrambling, modulation, layer mapping, and antenna port mapping.

As an embodiment, the meaning of "the second bit block is mapped to the second RE set after rate matching and modulation" includes: the second block of bits is mapped to the second set of REs after at least CRC (Cyclic Redundancy Check ) attachment (attachment), channel coding, rate matching, scrambling, and modulation.

As an embodiment, the meaning of "the second bit block is mapped to the second RE set after rate matching and modulation" includes: the second bit block is mapped to the second RE set after at least CRC (Cyclic Redundancy Check ) attachment (attachment), channel coding, rate matching, scrambling, modulation, layer mapping, and antenna port mapping.

As an embodiment, the meaning of "the second bit block is mapped to the second RE set after rate matching and modulation" includes: the second bit block is subjected to at least CRC (Cyclic Redundancy Check ) attachment (attachment), code block segmentation (Code Block Segmentation), code block CRC attachment, and channel coding to obtain a reference bit block subset; when the K RE subsets are commonly used to transmit one repetition of the second bit block, the reference bit block subset is mapped to the K RE subsets after at least one of rate matching, code block Concatenation (Concatenation), scrambling, and modulation; when the K RE subsets are respectively used for transmitting K repetitions of the second bit block, the reference bit block subsets are respectively mapped to the K RE subsets after K times of at least rate matching, code block Concatenation (Concatenation), scrambling, and modulation.

As an embodiment, the meaning of "the second bit block is mapped to the second RE set after rate matching and modulation" includes: the second bit block is subjected to at least CRC (Cyclic Redundancy Check ) attachment (attachment), code block segmentation (Code Block Segmentation), code block CRC attachment, and channel coding to obtain a reference bit block subset; the reference bit block subsets are mapped to the K RE subsets after K times of at least rate matching, code block Concatenation (Concatenation), scrambling and modulation, respectively.

As an embodiment, the meaning that the sentence "the product of the target value and the number of REs comprised by the target RE subset is used to determine the first limit value" means that: the product of the target value and the number of REs comprised by the target RE subset is given by a rule.

As an embodiment, the meaning that the sentence "the product of the target value and the number of REs comprised by the target RE subset is used to determine the first limit value" means that: the product of the target value and the number of REs comprised by the target RE subset is obtained by looking up a table.

As an embodiment, the meaning that the sentence "the product of the target value and the number of REs comprised by the target RE subset is used to determine the first limit value" means that: the product of the target value and the number of REs comprised by the target RE subset is subjected to a function operation to obtain the first limiting value.

As an embodiment, the meaning that the sentence "the product of the target value and the number of REs comprised by the target RE subset is used to determine the first limit value" means that: the product of the target value and the number of REs comprised by the target RE subset is mapped to the first constraint value.

As an embodiment, the meaning that the sentence "the product of the target value and the number of REs comprised by the target RE subset is used to determine the first limit value" means that: the first constraint value is a smallest integer that is not less than a product of the target value and a number of REs included in the target RE subset.

As an embodiment, the first limiting value is a positive integer.

As an embodiment, the first limiting value is a non-negative integer.

As one embodiment, the number of REs included in the target RE subset is

The target value is alpha and the first limit value is +.>

As an embodiment, the α, the l ₀ The said

Said->

And said

See section 6.3.2.4 of 3gpp ts38.212 for specific definition.

As an embodiment, the target value is the first value or the second value.

As an embodiment, whether the target value is a first value or a second value relates to whether the target RE subset belongs to a plurality of RE subsets of the K RE subsets or only one RE subset.

As an embodiment, whether the target value is a first value or a second value relates to whether the target subset of REs belongs to each of the K subsets of REs or only one subset of REs.

As an embodiment, whether the target value is a first value or a second value relates to whether the target RE subset belongs to only one RE subset of the K RE subsets.

As one embodiment, the first value is a non-negative real number and the second value is a non-negative real number.

As an embodiment, the first value is a non-negative real number not greater than 1 and the second value is a non-negative real number not greater than 1.

As an embodiment, the first value is a positive real number not greater than 1 and the second value is a positive real number not greater than 1.

As an embodiment, the first value is smaller than the second value.

As an embodiment, the first value is smaller than the second value, both the first value and the second value being values in the first set; the first set includes more than one value.

As an embodiment, the first value and the second value are both values in a first set; the first set includes more than one value.

As an embodiment, the second value and the first parameter are used together to determine the first value.

As an embodiment, the second value and the first parameter are obtained by a function operation.

As an embodiment, a ratio of the second value and the first parameter is used to determine the first value.

As an embodiment, the first value is related to a ratio of the second value and the first parameter.

As an embodiment, the first value is linearly related to the second value.

As an embodiment, the first value is a value of the first set closest to a ratio of the second value and the first parameter.

As a sub-embodiment of the above embodiment, the one value in the first set closest to the ratio of the second value to the first parameter is one value in the first set having the smallest absolute value of the difference between the second value and the ratio of the first parameter.

As a sub-embodiment of the above embodiment, the one value in the first set closest to the ratio of the second value and the first parameter is a smallest value in the first set that is not smaller than the ratio of the second value and the first parameter.

As a sub-embodiment of the above embodiment, the one value in the first set closest to the ratio of the second value and the first parameter is a smallest value in the first set that is not greater than the ratio of the second value and the first parameter.

As an embodiment, the ratio of the second value and the first parameter is equal to

As an embodiment, the first parameter is a positive real number.

As an embodiment, the first parameter is a positive integer.

As an embodiment, the first parameter is the K.

As an embodiment, the first parameter is predefined.

As an embodiment, the first parameter is a fixed value.

As an embodiment, the first parameter is indicated by a higher layer parameter.

Example 2

Embodiment 2 illustrates a schematic diagram of a network architecture according to one embodiment of the present application, as shown in fig. 2.

Fig. 2 illustrates a network architecture 200 of LTE (Long-Term Evolution), LTE-a (Long-Term Evolution Advanced, enhanced Long-Term Evolution) and future 5G systems. The network architecture 200 of LTE, LTE-a and future 5G systems is referred to as EPS (Evolved Packet System ) 200. The 5G NR or LTE network architecture 200 may be referred to as a 5GS (5G System)/EPS (Evolved Packet System ) 200 or some other suitable terminology. The 5GS/EPS200 may include one or more UEs (User Equipment) 201, one UE241 in Sidelink (Sidelink) communication with the UE201, NG-RAN (next generation radio access network) 202,5GC (5G CoreNetwork)/EPC (Evolved Packet Core, evolved packet core) 210, hss (Home Subscriber Server )/UDM (Unified Data Management, unified data management) 220, and internet service 230. The 5GS/EPS200 may interconnect with other access networks, but these entities/interfaces are not shown for simplicity. As shown in fig. 2, the 5GS/EPS200 provides packet switched services, however, those skilled in the art will readily appreciate that the various concepts presented throughout this application may be extended to networks providing circuit switched services. The NG-RAN202 includes an NR (New Radio), node B (gNB) 203 and other gnbs 204. The gNB203 provides user and control plane protocol termination towards the UE 201. The gNB203 may be connected to other gnbs 204 via an Xn interface (e.g., backhaul). The gNB203 may also be referred to as a base station, a base transceiver station, a radio base station, a radio transceiver, a transceiver function, a Basic Service Set (BSS), an Extended Service Set (ESS), TRP (transmit-receive point), or some other suitable terminology. The gNB203 provides the UE201 with an access point to the 5GC/EPC210. Examples of UE201 include a cellular telephone, a smart phone, a Session Initiation Protocol (SIP) phone, a laptop, a Personal Digital Assistant (PDA), a satellite radio, a global positioning system, a multimedia device, a video device, a digital audio player (e.g., MP3 player), a camera, a game console, an drone, an aircraft, a narrowband physical network device, a machine-type communication device, a land vehicle, an automobile, a wearable device, or any other similar functional device. Those of skill in the art may also refer to the UE201 as a mobile station, a subscriber station, a mobile unit, a subscriber unit, a wireless unit, a remote unit, a mobile device, a wireless communication device, a remote device, a mobile subscriber station, an access terminal, a mobile terminal, a wireless terminal, a remote terminal, a handset, a user agent, a mobile client, a client, or some other suitable terminology. gNB203 is connected to 5GC/EPC210 through an S1/NG interface. The 5GC/EPC210 includes MME (Mobility Management Entity )/AMF (Authentication Management Field, authentication management domain)/SMF (Session Management Function ) 211, other MME/AMF/SMF214, S-GW (Service Gateway)/UPF (User Plane Function ) 212, and P-GW (Packet Date Network Gateway, packet data network Gateway)/UPF 213. The MME/AMF/SMF211 is a control node that handles signaling between the UE201 and the 5GC/EPC210. The MME/AMF/SMF211 generally provides bearer and connection management. All user IP (Internet Protocal, internet protocol) packets are transported through the S-GW/UPF212, which S-GW/UPF212 itself is connected to the P-GW/UPF213. The P-GW provides UE IP address assignment as well as other functions. The P-GW/UPF213 is connected to the internet service 230. Internet services 230 include operator-corresponding internet protocol services, which may include, in particular, internet, intranet, IMS (IP Multimedia Subsystem ) and Packet switching (Packet switching) services.

As an embodiment, the first node in the present application includes the UE201.

As an embodiment, the first node in the present application includes the UE241.

As an embodiment, the second node in the present application includes the gNB203.

Example 3

Embodiment 3 illustrates a schematic diagram of an embodiment of a wireless protocol architecture of a user plane and a control plane according to one embodiment of the present application, as shown in fig. 3.

Embodiment 3 shows a schematic diagram of an embodiment of a radio protocol architecture according to one user plane and control plane of the present application, as shown in fig. 3. Fig. 3 is a schematic diagram illustrating an embodiment of a radio protocol architecture for a user plane 350 and a control plane 300, fig. 3 shows the radio protocol architecture for the control plane 300 between a first communication node device (RSU in UE, gNB or V2X) and a second communication node device (RSU in gNB, UE or V2X), or between two UEs, in three layers: layer 1, layer 2 and layer 3. Layer 1 (L1 layer) is the lowest layer and implements various PHY (physical layer) signal processing functions. The L1 layer will be referred to herein as PHY301. Layer 2 (L2 layer) 305 is above PHY301 and is responsible for the link between the first communication node device and the second communication node device, or between two UEs. The L2 layer 305 includes a MAC (Medium Access Control ) sublayer 302, an RLC (Radio Link Control, radio link layer control protocol) sublayer 303, and a PDCP (Packet Data Convergence Protocol ) sublayer 304, which terminate at the second communication node device. The PDCP sublayer 304 provides multiplexing between different radio bearers and logical channels. The PDCP sublayer 304 also provides security by ciphering the data packets and handover support for the first communication node device between second communication node devices. The RLC sublayer 303 provides segmentation and reassembly of upper layer data packets, retransmission of lost data packets, and reordering of data packets to compensate for out of order reception due to HARQ. The MAC sublayer 302 provides multiplexing between logical and transport channels. The MAC sublayer 302 is also responsible for allocating the various radio resources (e.g., resource blocks) in one cell among the first communication node devices. The MAC sublayer 302 is also responsible for HARQ operations. The RRC (Radio Resource Control ) sublayer 306 in layer 3 (L3 layer) in the control plane 300 is responsible for obtaining radio resources (i.e., radio bearers) and configuring the lower layers using RRC signaling between the second communication node device and the first communication node device. The radio protocol architecture of the user plane 350 includes layer 1 (L1 layer) and layer 2 (L2 layer), the radio protocol architecture for the first communication node device and the second communication node device in the user plane 350 is substantially the same for the physical layer 351, PDCP sublayer 354 in the L2 layer 355, RLC sublayer 353 in the L2 layer 355 and MAC sublayer 352 in the L2 layer 355 as the corresponding layers and sublayers in the control plane 300, but the PDCP sublayer 354 also provides header compression for upper layer data packets to reduce radio transmission overhead. Also included in the L2 layer 355 in the user plane 350 is an SDAP (Service Data Adaptation Protocol ) sublayer 356, the SDAP sublayer 356 being responsible for mapping between QoS flows and data radio bearers (DRBs, data Radio Bearer) to support diversity of traffic. Although not shown, the first communication node apparatus may have several upper layers above the L2 layer 355, including a network layer (e.g., IP layer) that terminates at the P-GW on the network side and an application layer that terminates at the other end of the connection (e.g., remote UE, server, etc.).

As an embodiment, the radio protocol architecture in fig. 3 is applicable to the first node in the present application.

As an embodiment, the radio protocol architecture in fig. 3 is applicable to the second node in the present application.

As an embodiment, the first signaling is generated in at least one of the PHY301, the PHY351, the RRC sublayer 306, or the MAC sublayer 302.

As an embodiment, the first signaling is generated in the PHY301.

As an embodiment, the first signaling is generated in the PHY351.

As an embodiment, the first signaling is generated in the RRC sublayer 306.

As an embodiment, the first signaling is generated in the MAC sublayer 302.

As an embodiment, the second signaling is generated in the PHY301.

As an embodiment, the second signaling is generated in the PHY351.

As an embodiment, the second signaling is generated in the RRC sublayer 306.

As an embodiment, the second signaling is generated in the MAC sublayer 302.

As an embodiment, signals used to transmit the first bit block and the second bit block in the second RE set are generated at the PHY301.

As an embodiment, the first bit block is generated in the PHY301.

As an embodiment, the first bit block is generated in the PHY351.

As an embodiment, the first bit block is generated in the RRC sublayer 306.

As an embodiment, the first bit block is generated in the MAC sublayer 302.

As an embodiment, the second bit block is generated in the PHY301.

As an embodiment, the second bit block is generated in the PHY351.

As an embodiment, the second bit block is generated in the RRC sublayer 306.

As an embodiment, the second bit block is generated in the MAC sublayer 302.

Example 4

Embodiment 4 illustrates a schematic diagram of a first communication device and a second communication device according to an embodiment of the present application, as shown in fig. 4. Fig. 4 is a block diagram of a first communication device 410 and a second communication device 450 in communication with each other in an access network.

The first communication device 410 includes a controller/processor 475, a memory 476, a receive processor 470, a transmit processor 416, a multi-antenna receive processor 472, a multi-antenna transmit processor 471, a transmitter/receiver 418, and an antenna 420.

The second communication device 450 includes a controller/processor 459, a memory 460, a data source 467, a transmit processor 468, a receive processor 456, a multi-antenna transmit processor 457, a multi-antenna receive processor 458, a transmitter/receiver 454, and an antenna 452.

In the transmission from the first communication device 410 to the second communication device 450, upper layer data packets from the core network are provided to a controller/processor 475 at the first communication device 410. The controller/processor 475 implements the functionality of the L2 layer. In DL, the controller/processor 475 provides header compression, encryption, packet segmentation and reordering, multiplexing between logical and transport channels, and radio resource allocations to the second communication device 450 based on various priority metrics. The controller/processor 475 is also responsible for HARQ operations, retransmission of lost packets, and signaling to the second communication device 450. The transmit processor 416 and the multi-antenna transmit processor 471 implement various signal processing functions for the L1 layer (i.e., physical layer). The transmit processor 416 performs coding and interleaving to facilitate Forward Error Correction (FEC) at the second communication device 450, as well as constellation mapping based on various modulation schemes, e.g., binary Phase Shift Keying (BPSK), quadrature Phase Shift Keying (QPSK), M-phase shift keying (M-PSK), M-quadrature amplitude modulation (M-QAM). The multi-antenna transmit processor 471 digitally space-precodes the coded and modulated symbols, including codebook-based precoding and non-codebook-based precoding, and beamforming processing, to generate one or more parallel streams. A transmit processor 416 then maps each parallel stream to a subcarrier, multiplexes the modulated symbols with a reference signal (e.g., pilot) in the time and/or frequency domain, and then uses an Inverse Fast Fourier Transform (IFFT) to produce a physical channel carrying the time-domain multicarrier symbol stream. The multi-antenna transmit processor 471 then performs transmit analog precoding/beamforming operations on the time domain multi-carrier symbol stream. Each transmitter 418 converts the baseband multicarrier symbol stream provided by the multiple antenna transmit processor 471 to a radio frequency stream and then provides it to a different antenna 420.

In a transmission from the first communication device 410 to the second communication device 450, each receiver 454 receives a signal at the second communication device 450 through its respective antenna 452. Each receiver 454 recovers information modulated onto a radio frequency carrier and converts the radio frequency stream into a baseband multicarrier symbol stream that is provided to a receive processor 456. The receive processor 456 and the multi-antenna receive processor 458 implement various signal processing functions for the L1 layer. A multi-antenna receive processor 458 performs receive analog precoding/beamforming operations on the baseband multi-carrier symbol stream from the receiver 454. The receive processor 456 converts the baseband multicarrier symbol stream after receiving the analog precoding/beamforming operation from the time domain to the frequency domain using a Fast Fourier Transform (FFT). In the frequency domain, the physical layer data signal and the reference signal are demultiplexed by the receive processor 456, wherein the reference signal is to be used for channel estimation, and the data signal is subjected to multi-antenna detection in the multi-antenna receive processor 458 to recover any parallel streams destined for the second communication device 450. The symbols on each parallel stream are demodulated and recovered in a receive processor 456 and soft decisions are generated. The receive processor 456 then decodes and deinterleaves the soft decisions to recover the upper layer data and control signals that were transmitted by the first communication device 410 on the physical channel. The upper layer data and control signals are then provided to the controller/processor 459. The controller/processor 459 implements the functions of the L2 layer. The controller/processor 459 may be associated with a memory 460 that stores program codes and data. Memory 460 may be referred to as a computer-readable medium. In DL, the controller/processor 459 provides demultiplexing between transport and logical channels, packet reassembly, deciphering, header decompression, control signal processing to recover upper layer data packets from the core network. The upper layer packets are then provided to all protocol layers above the L2 layer. Various control signals may also be provided to L3 for L3 processing. The controller/processor 459 is also responsible for error detection using Acknowledgement (ACK) and/or Negative Acknowledgement (NACK) protocols to support HARQ operations.

In the transmission from the second communication device 450 to the first communication device 410, a data source 467 is used at the second communication device 450 to provide upper layer data packets to a controller/processor 459. Data source 467 represents all protocol layers above the L2 layer. Similar to the transmit function at the first communication device 410 described in DL, the controller/processor 459 implements header compression, encryption, packet segmentation and reordering, and multiplexing between logical and transport channels based on radio resource allocations of the first communication device 410, implementing L2 layer functions for the user and control planes. The controller/processor 459 is also responsible for HARQ operations, retransmission of lost packets, and signaling to the first communication device 410. The transmit processor 468 performs modulation mapping, channel coding, and digital multi-antenna spatial precoding, including codebook-based precoding and non-codebook-based precoding, and beamforming, with the multi-antenna transmit processor 457 then modulating the resulting parallel streams into multi-carrier/single-carrier symbol streams, which are analog precoded/beamformed in the multi-antenna transmit processor 457 before being provided to the different antennas 452 via the transmitter 454. Each transmitter 454 first converts the baseband symbol stream provided by the multi-antenna transmit processor 457 into a radio frequency symbol stream and provides it to an antenna 452.

In the transmission from the second communication device 450 to the first communication device 410, the function at the first communication device 410 is similar to the receiving function at the second communication device 450 described in the transmission from the first communication device 410 to the second communication device 450. Each receiver 418 receives radio frequency signals through its corresponding antenna 420, converts the received radio frequency signals to baseband signals, and provides the baseband signals to a multi-antenna receive processor 472 and a receive processor 470. The receive processor 470 and the multi-antenna receive processor 472 collectively implement the functions of the L1 layer. The controller/processor 475 implements L2 layer functions. The controller/processor 475 may be associated with a memory 476 that stores program codes and data. Memory 476 may be referred to as a computer-readable medium. The controller/processor 475 provides demultiplexing between transport and logical channels, packet reassembly, deciphering, header decompression, control signal processing to recover upper layer data packets from the second communication device 450. Upper layer packets from the controller/processor 475 may be provided to the core network. The controller/processor 475 is also responsible for error detection using an ACK and/or NACK protocol to support HARQ operations.

As an embodiment, the second communication device 450 includes: at least one processor and at least one memory including computer program code; the at least one memory and the computer program code are configured for use with the at least one processor. The second communication device 450 means at least: receiving first signaling, the first signaling being used to indicate a first set of REs; receiving second signaling, the second signaling being used to indicate a second set of REs; transmitting a first bit block and a second bit block in the second RE set; wherein the first RE set is reserved for the first bit block, the second RE set is reserved for the second bit block, and the first RE set and the second RE set overlap in the time domain; the second set of REs comprises K subsets of REs, K being a positive integer greater than 1; any two RE subsets of the K RE subsets are orthogonal in the time domain, and the first bit block is mapped to at least one RE subset of the K RE subsets; the first bit block is mapped to a number of REs in the K RE subsets not greater than a first constraint value, a product of a target value and a number of REs included in a target RE subset is used to determine the first constraint value, and the second RE set includes the target RE subset; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the target value is a first value; the target value is a second value when the target RE subset belongs to only one of the K RE subsets.

As an embodiment, the second communication device 450 includes: a memory storing a program of computer-readable instructions that, when executed by at least one processor, produce acts comprising: receiving first signaling, the first signaling being used to indicate a first set of REs; receiving second signaling, the second signaling being used to indicate a second set of REs; transmitting a first bit block and a second bit block in the second RE set; wherein the first RE set is reserved for the first bit block, the second RE set is reserved for the second bit block, and the first RE set and the second RE set overlap in the time domain; the second set of REs comprises K subsets of REs, K being a positive integer greater than 1; any two RE subsets of the K RE subsets are orthogonal in the time domain, and the first bit block is mapped to at least one RE subset of the K RE subsets; the first bit block is mapped to a number of REs in the K RE subsets not greater than a first constraint value, a product of a target value and a number of REs included in a target RE subset is used to determine the first constraint value, and the second RE set includes the target RE subset; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the target value is a first value; the target value is a second value when the target RE subset belongs to only one of the K RE subsets.

As one embodiment, the first communication device 410 includes: at least one processor and at least one memory including computer program code; the at least one memory and the computer program code are configured for use with the at least one processor. The first communication device 410 means at least: transmitting first signaling, the first signaling being used to indicate a first set of REs; transmitting second signaling, the second signaling being used to indicate a second set of REs; receiving a first block of bits and a second block of bits in the second set of REs; wherein the first RE set is reserved for the first bit block, the second RE set is reserved for the second bit block, and the first RE set and the second RE set overlap in the time domain; the second set of REs comprises K subsets of REs, K being a positive integer greater than 1; any two RE subsets of the K RE subsets are orthogonal in the time domain, and the first bit block is mapped to at least one RE subset of the K RE subsets; the first bit block is mapped to a number of REs in the K RE subsets not greater than a first constraint value, a product of a target value and a number of REs included in a target RE subset is used to determine the first constraint value, and the second RE set includes the target RE subset; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the target value is a first value; the target value is a second value when the target RE subset belongs to only one of the K RE subsets.

As one embodiment, the first communication device 410 includes: a memory storing a program of computer-readable instructions that, when executed by at least one processor, produce acts comprising: transmitting first signaling, the first signaling being used to indicate a first set of REs; transmitting second signaling, the second signaling being used to indicate a second set of REs; receiving a first block of bits and a second block of bits in the second set of REs; wherein the first RE set is reserved for the first bit block, the second RE set is reserved for the second bit block, and the first RE set and the second RE set overlap in the time domain; the second set of REs comprises K subsets of REs, K being a positive integer greater than 1; any two RE subsets of the K RE subsets are orthogonal in the time domain, and the first bit block is mapped to at least one RE subset of the K RE subsets; the first bit block is mapped to a number of REs in the K RE subsets not greater than a first constraint value, a product of a target value and a number of REs included in a target RE subset is used to determine the first constraint value, and the second RE set includes the target RE subset; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the target value is a first value; the target value is a second value when the target RE subset belongs to only one of the K RE subsets.

As an embodiment, the first node in the present application includes the second communication device 450.

As an embodiment, the second node in the present application comprises the first communication device 410.

As an embodiment, at least one of the antenna 452, the receiver 454, the receive processor 456, the multi-antenna receive processor 458, the controller/processor 459, the memory 460, the data source 467 is used for receiving the first signaling in the present application; at least one of { the antenna 420, the transmitter 418, the transmit processor 416, the multi-antenna transmit processor 471, the controller/processor 475, the memory 476} is used to transmit the first signaling in this application.

As an embodiment, at least one of the antenna 452, the receiver 454, the receive processor 456, the multi-antenna receive processor 458, the controller/processor 459, the memory 460, the data source 467 is used for receiving the second signaling in the present application; at least one of { the antenna 420, the transmitter 418, the transmit processor 416, the multi-antenna transmit processor 471, the controller/processor 475, the memory 476} is used to transmit the second signaling in the present application.

As an embodiment, at least one of { the antenna 452, the transmitter 454, the transmit processor 468, the multi-antenna transmit processor 457, the controller/processor 459, the memory 460} is used to transmit the first bit block and the second bit block in the second set of REs in this application; at least one of { the antenna 420, the receiver 418, the receive processor 470, the multi-antenna receive processor 472, the controller/processor 475, the memory 476} is used to receive the first bit block and the second bit block in the second set of REs in this application.

Example 5

Embodiment 5 illustrates a flow chart of wireless transmission according to one embodiment of the present application, as shown in fig. 5. In fig. 5, the first node U01 and the second node N02 are respectively two communication nodes transmitting over the air interface.

For the followingFirst node U01Receiving a first signaling in step S5101; receiving a second signaling in step S5102; transmitting the first bit block and the second bit block in the second RE set in step S5103;

for the followingSecond node N02Transmitting a first signaling in step S5201; transmitting a second signaling in step S5202; the first bit block and the second bit block are received in the second RE set in step S5203.

In embodiment 5, the first set of REs is reserved for the first bit block and the second set of REs is reserved for the second bit block, the first set of REs and the second set of REs overlapping in the time domain; the second set of REs comprises K subsets of REs, K being a positive integer greater than 1; any two RE subsets of the K RE subsets are orthogonal in the time domain, and the first bit block is mapped to at least one RE subset of the K RE subsets; the first bit block is mapped to a number of REs in the K RE subsets not greater than a first constraint value, a product of a target value and a number of REs included in a target RE subset is used to determine the first constraint value, and the second RE set includes the target RE subset; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the target value is a first value; the target value is a second value when the target RE subset belongs to only one of the K RE subsets.

As an embodiment, the sentence "the first class RE subset belongs to a plurality of RE subsets among the K RE subsets" means that: the first class RE subset is composed of at least one RE included by each RE subset of the plurality of RE subsets; the sentence "the first class RE subset belongs to only one RE subset of the K RE subsets" means that: the first class RE subset consists of at least one RE comprised by only one RE subset of the K RE subsets.

As an embodiment, the sentence "the first class RE subset belongs to a plurality of RE subsets among the K RE subsets" means that: the first class RE subset is composed of partial REs included in each RE subset of the plurality of RE subsets; the sentence "the first class RE subset belongs to only one RE subset of the K RE subsets" means that: the first class RE subset consists of partial REs comprised by only one RE subset of the K RE subsets.

As an embodiment, the sentence "the first class RE subset belongs to only one RE subset of the K RE subsets" means that: a first class RE subset belongs to only the first one of the K RE subsets.

As an embodiment, the sentence "the first class RE subset belongs to only one RE subset of the K RE subsets" means that: the first class RE subset belongs to only the earliest RE subset of the K RE subsets.

As an embodiment, the sentence "the first class RE subset belongs to a plurality of RE subsets among the K RE subsets" means that: the first class RE subset is composed of at least one RE included in each of the K RE subsets.

As an embodiment, the sentence "the first class RE subset belongs to a plurality of RE subsets among the K RE subsets" means that: the first class RE subset is composed of partial REs included in each of the K RE subsets.

As an embodiment, the first class RE subset is the reference RE subset in the present application.

As an embodiment, the first class RE subset is the target RE subset in the present application.

As an embodiment, the first transmitter transmits demodulation reference signals in the second RE set; any symbol occupied by the demodulation reference signal sent in the second RE set is orthogonal to any symbol occupied by the target RE subset.

As an embodiment, the first transmitter transmits demodulation reference signals in the second RE set; any symbol occupied by the demodulation reference signal sent in the second RE set is different from any symbol occupied by the target RE subset.

As one embodiment, the first transmitter transmits a phase tracking reference signal (PTRS, phase Tracking Reference Signal) in the second set of REs; any RE occupied by the phase tracking reference signal transmitted in the second set of REs is orthogonal to the target subset of REs.

As one embodiment, the first transmitter transmits a phase tracking reference signal in the second set of REs; any RE occupied by the phase tracking reference signal transmitted in the second set of REs is different from the target subset of REs.

As an embodiment, a product of the first offset and a number of REs comprised by a reference RE subset comprising the target RE subset is used to determine the first reference value; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the reference RE subset belongs to only one RE subset of the K RE subsets; when the target RE subset belongs to only one of the K RE subsets, the reference RE subset belongs to only one of the K RE subsets.

As an embodiment, a product of the first offset and a number of REs comprised by a reference RE subset comprising the target RE subset is used to determine the first reference value; only a first subset of REs of the first set of REs and the second set of REs overlap in the time domain, the first subset of REs being one of the K subsets of REs; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the reference RE subset belongs to only one RE subset of the K RE subsets; when the target RE subset belongs to only one RE subset of the K RE subsets, the target RE subset belongs to the first RE subset, and the reference RE subset belongs to the first RE subset.

As an embodiment, a product of the first offset and a number of REs comprised by a reference RE subset comprising the target RE subset is used to determine the first reference value; only a first subset of REs of the first set of REs and the second set of REs overlap in the time domain, the first subset of REs being one of the K subsets of REs; the reference RE subset belongs to the first RE subset.

As an embodiment, a product of the first offset and a number of REs comprised by a reference RE subset comprising the target RE subset is used to determine the first reference value; only a first subset of REs of the first set of REs and the second set of REs overlap in the time domain, the first subset of REs being one of the K subsets of REs; the reference RE subset belongs to the first RE subset, whether the target RE subset belongs to multiple RE subsets of the K RE subsets or only one RE subset.

Example 6

Embodiment 6 illustrates a schematic diagram of the size of a second bit block according to one embodiment of the present application; as shown in fig. 6.

In embodiment 6, when the K RE subsets are collectively used to determine the size of the second bit block, the target RE subset belongs to a plurality of RE subsets of the K RE subsets; when only one of the K RE subsets is used to determine the size of the second bit block, the target RE subset belongs to only one of the K RE subsets.

As an embodiment, the size of the second bit block is TBS (TransportBlock Size ).

As an embodiment, the size of the second bit block is the number of bits the second bit block comprises.

As an embodiment, the meaning of the sentence "the K RE subsets are used together to determine the size of the second bit block" includes: the number of RBs included in the frequency domain by the K RE subsets and the number of symbols included in the time domain by the K RE subsets are used together to determine the size of the second bit block; the meaning of the sentence "only one of the K RE subsets is commonly used for determining the size of the second bit block" includes: the number of RBs included in the frequency domain and the number of symbols included in the time domain of one of the K RE subsets are used together to determine the size of the second bit block.

As one embodiment, the second bit block is a TBS, and the number of RBs included in the frequency domain by the K RE subsets is n _PRB The number of symbols included in the time domain by the K RE subsets is

As one embodiment, the second bit block is a TBS, and the number of RBs included in the frequency domain by only one of the K RE subsets is n _PRB The number of symbols included in the time domain by only one RE subset of the K RE subsets is

As an embodiment, the n _PRB And said

For specific procedures used to determine TBS see section 6.1.4.2 in 3gpp ts 38.214.

Example 7

Embodiment 7 illustrates a schematic diagram of a relationship between K RE subsets and a second bit block according to one embodiment of the present application; as shown in fig. 7.

In embodiment 7, when the K RE subsets are collectively used to determine the size of the second bit block, the K RE subsets are collectively used to transmit one repetition of the second bit block; when only one of the K RE subsets is used to determine the size of the second bit block, the K RE subsets are used to transmit K repetitions of the second bit block, respectively.

As an embodiment, one repetition of the second bit block is transmitted on one PUSCH, and K repetitions of the second bit block are transmitted on K PUSCHs, respectively.

As an embodiment, when the K RE subsets are commonly used to determine the size of the second bit block, the signals carried in the K RE subsets correspond to the same RV (Redundancy Version ); when only one of the K RE subsets is used to determine the size of the second bit block, signals carried by at least two of the K RE subsets, respectively, correspond to different RVs.

Example 8

Embodiment 8 illustrates a schematic diagram of a first value and a second value according to one embodiment of the present application; as shown in fig. 8.

In embodiment 8, the first value is one value in a first set and the second value is one value in a second set, the first set and the second set being different; the first set includes more than one value and the second set includes more than one value.

As an embodiment, any value in the first set and the second set is a non-negative real number.

As an embodiment, any one of the values in the first set and the second set is a positive real number.

As one embodiment, any one of the values in the first set and the second set is a non-negative real number not greater than 1.

As an embodiment, any one of the values in the first set and the second set is a positive real number not greater than 1.

As an embodiment, the minimum value in the first set is smaller than the minimum value in the second set.

As an embodiment, at least one value in the first set is smaller than any value in the second set.

As one embodiment, the second set includes 0.5, 0.65, 0.8, and 1.

As an embodiment, at least one value in the first set does not belong to the second set.

As an embodiment, the first value is indicated by a higher layer parameter.

As an embodiment, the second value is indicated by a higher layer parameter.

As an embodiment, the first set is fixed.

As an embodiment, the second set is fixed.

As an embodiment, the first set is predefined.

As an embodiment, the second set is predefined.

Example 9

Embodiment 9 illustrates a schematic diagram of a first bit block being mapped to the number of REs in K RE subsets according to one embodiment of the present application; as shown in fig. 9.

In embodiment 9, the first bit block is mapped to a minimum of the first reference value and the first constraint value of the number of REs in the K RE subsets; the second signaling indicates a first offset, which is used to determine the first reference value.

As an embodiment, the number of REs in the K RE subsets to which the first bit block is mapped is equal to the minimum of a first reference value and the first constraint value; the second signaling indicates a first offset, which is used to determine the first reference value.

As an embodiment, the number of REs in the K RE subsets mapped to the first bit block is equal to a minimum of the first reference value, the first constraint value, and a second constraint value.

As one embodiment, the second signaling is used to indicate the first offset from a first set of offsets, the first set of offsets comprising a plurality of non-negative real numbers, the first offset being one non-negative real number in the first set of offsets.

As an embodiment, the second signaling includes a fourth field, the fourth field in the second signaling indicating the first offset.

As a sub-embodiment of the above embodiment, the fourth field in the second signaling comprises a positive integer number of bits.

As a sub-embodiment of the above embodiment, the fourth field includes a beta_offset indicator field (field).

For a specific definition of the beta_offset indicator field, see 3gpp ts38.212.

As one embodiment, the first offset is a non-negative real number.

As an embodiment, the first offset is a positive real number.

As an embodiment, the first offset is a positive real number greater than 1.

As one embodiment, the first offset is a positive real number not less than 1.

As one embodiment, the first offset is

As an embodiment, the

Detailed description of the inventionSee section 6.3.2 of 3gpp ts 38.212.

As one embodiment, the first offset is

As an embodiment, the

See section 6.3.2 of 3gpp ts38.212 for specific definition.

As one embodiment, the first offset is

As an embodiment, the

See section 6.3.2 of 3gpp ts38.212 for specific definition.

As one embodiment, the first offset is

As an embodiment, the

See section 6.3.2 of 3gpp ts38.212 for specific definition.

As one embodiment, the first offset is

As an embodiment, the

See section 5.2 of 3gpp ts36.212 (V15.3.0).

As one embodiment, the first offset is

As an embodiment, the

See section 6.3.2 of 3GPP TS38.212 for detailed definition of (A) and (B)

As an embodiment, the meaning of the sentence "the first offset is used to determine the first reference value" means that: and the first offset is used for obtaining the first reference value through a certain rule.

As an embodiment, the meaning of the sentence "the first offset is used to determine the first reference value" means that: the first offset is obtained by looking up a table to obtain the first reference value.

As an embodiment, the meaning of the sentence "the first offset is used to determine the first reference value" means that: the first offset is calculated by a function to obtain the first reference value.

As an embodiment, the meaning of the sentence "the first offset is used to determine the first reference value" means that: the first offset is mapped to the first reference value.

As an embodiment, the meaning of the sentence "the first offset is used to determine the first reference value" means that: the first bit block includes a number of bits and the first offset is used together to determine the first reference value.

As an embodiment, the meaning of the sentence "the first offset is used to determine the first reference value" means that: a product of a number of bits included in a target block of bits including the first block of bits and the first offset is used to determine the first reference value.

As an embodiment, the meaning of the sentence "the first offset is used to determine the first reference value" means that: a product of a number of bits included in a target bit block and the first offset is used to determine a second reference value, the target bit block including the first bit block; the first reference value is a minimum integer not less than the second reference value.

As an embodiment, the meaning of the sentence "the first offset is used to determine the first reference value" means that: the product of the first offset and the number of REs comprised by a reference RE subset comprising the target RE subset is used to determine a second reference value; the first reference value is a minimum integer not less than the second reference value.

As an embodiment, the meaning of the sentence "the first offset is used to determine the first reference value" means that: a product of a number of bits included in a target block of bits, the first offset, and a number of REs included in a reference RE subset, the target block of bits including the first block of bits, the reference RE subset including the target RE subset, is used to determine a second reference value; the first reference value is a minimum integer not less than the second reference value.

As an embodiment, the target bit block further comprises at least one bit other than the first bit block, and the target bit block comprises a number of bits greater than the number of bits comprised by the first bit block.

As an embodiment, the target bit block further comprises CRC bits of the first bit block, the target bit block comprising a greater number of bits than the first bit block.

As an embodiment, the second reference value is linearly related to the product of the number of bits comprised by the target block of bits and the first offset.

Example 10

Embodiment 10 illustrates a schematic diagram of a first reference value according to one embodiment of the present application; as shown in fig. 10.

In embodiment 10, a product of the first offset and a number of REs comprised by a reference RE subset comprising the target RE subset is used to determine the first reference value; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the reference RE subset belongs to a plurality of RE subsets of the K RE subsets; when the target RE subset belongs to only one of the K RE subsets, the reference RE subset belongs to only one of the K RE subsets.

As an embodiment, whether the reference RE subset belongs to a plurality of RE subsets of the K RE subsets or only one RE subset relates to whether the target RE subset belongs to a plurality of RE subsets of the K RE subsets or only one RE subset.

As an embodiment, the reference RE subset comprises only the target RE subset.

As an embodiment, the reference RE subset further comprises at least one RE outside the target RE subset.

As an embodiment, the subset of REs to which the reference subset of REs belongs is different from the subset of REs to which the target subset of REs belongs.

As an embodiment, the subset of REs to which the reference subset of REs belongs is the same as the subset of REs to which the target subset of REs belongs.

As an embodiment, when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the reference RE subset belongs to the plurality of RE subsets to which the target RE subset belongs; when the target RE subset belongs to only one RE subset of the K RE subsets, the reference RE subset belongs to the one RE subset to which the target RE subset belongs.

As an embodiment, a product of the first offset and a number of REs comprised by a reference RE subset comprising the target RE subset is used to determine a second reference value; the first reference value is a minimum integer not less than the second reference value.

As an embodiment, a product of a number of bits comprised by a target block of bits, the first offset, and a number of REs comprised by a reference RE subset, the target block of bits comprising the first block of bits, the reference RE subset comprising the target RE subset, is used to determine a second reference value; the first reference value is a minimum integer not less than the second reference value.

As an embodiment, the second reference value is linearly related to the product of the first offset and the number of REs comprised by the reference RE subset.

As an embodiment, the second reference value is equal to a value obtained by multiplying the number of bits included in the target bit block, the first offset, and the number of REs included in the reference RE subset by the number of bits included in the second bit block.

As an embodiment, the second reference value is equal to a value obtained by multiplying the number of bits included in the target bit block, the first offset, and the number of REs included in the reference RE subset, and dividing the value by a sum of all code block sizes (code block sizes) in the second bit block.

As an embodiment, the size of one code block is equal to the number of bits comprised by said one code block.

As one embodiment, the target bit block includes a number of bits O _ACK +L _ACK The first offset is

The reference RE subset comprises RE number +.>

K _r Is the number of bits included in the r-th code block in the second bit block, and the sum of all code block sizes (code block sizes) in the second bit block is

The second reference value is +.>

The first reference value is +.>

As an embodiment, the O _ACK The L is _ACK The said

Said->

Said->

The C is _UL-SCH The K is _r See section 6.3.2.4 of 3gpp ts38.212 for specific definition.

Example 11

Embodiment 11 illustrates a schematic diagram of a first bit block being mapped to a number of REs in a first RE subset according to one embodiment of the present application; as shown in fig. 11.

In embodiment 11, the first bit block is mapped to only a first subset of REs of the K subsets of REs, the first subset of REs being one of the K subsets of REs, the number of REs of the K subsets of REs to which the first bit block is mapped being the number of REs of the first subset of REs to which the first bit block is mapped; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the number of REs in the first bit block mapped to the first RE subset is equal to a minimum of the first reference value, the first constraint value, and a second constraint value; the second constraint value is not greater than a number of REs included in the first subset of REs.

As an embodiment, the second constraint value is equal to a number of REs comprised by the first subset of REs.

As an embodiment, the second constraint value is smaller than the number of REs comprised by the first subset of REs.

As an embodiment, the second limiting value is a positive integer.

As an embodiment, the second limiting value is a non-negative integer.

As an embodiment, the second limit value is not greater than the first limit value.

As an embodiment, the second limit value is smaller than the first limit value.

As an embodiment, the number of REs comprised by the first subset of REs is used to determine the second constraint value.

As an embodiment, the number of REs comprised by the first subset of REs is a rule to obtain the second constraint value.

As an embodiment, the number of REs included in the first RE subset is obtained by looking up a table to obtain the second constraint value.

As an embodiment, the number of REs included in the first RE subset is calculated by a function to obtain the second constraint value.

As an embodiment, the number of REs comprised by the first subset of REs is mapped to the second constraint value.

As an embodiment, the second constraint value is equal to a product of a number of REs included in the first subset of REs and a second offset.

As one embodiment, the second offset is a non-negative real number.

As one embodiment, the second offset is a positive real number.

As one embodiment, the second offset is a non-negative real number not greater than 1.

As one embodiment, the second offset is a non-negative real number less than 1.

As an embodiment, the second offset is a positive real number not greater than 1.

As an embodiment, the second offset is a positive real number less than 1.

As an embodiment, the second offset is indicated by a higher layer parameter.

Example 12

Embodiment 12 illustrates a block diagram of a processing apparatus for use in a first node device according to one embodiment of the present application; as shown in fig. 12. In fig. 12, the processing means 1200 in the first node device comprises a first receiver 1201 and a first transmitter 1202.

As an embodiment, the first node device is a user equipment.

As an embodiment, the first node device is a relay node device.

As an example, the first receiver 1201 includes at least one of { antenna 452, receiver 454, receive processor 456, multi-antenna receive processor 458, controller/processor 459, memory 460, data source 467} in example 4.

As an example, the first transmitter 1202 includes at least one of { antenna 452, transmitter 454, transmit processor 468, multi-antenna transmit processor 457, controller/processor 459, memory 460, data source 467} in example 4.

A first receiver 1201 receiving first signaling, the first signaling being used to indicate a first set of REs; receiving second signaling, the second signaling being used to indicate a second set of REs;

a first transmitter 1202 that transmits a first bit block and a second bit block in the second RE set;

in embodiment 12, the first set of REs is reserved for the first bit block and the second set of REs is reserved for the second bit block, the first set of REs and the second set of REs overlapping in the time domain; the second set of REs comprises K subsets of REs, K being a positive integer greater than 1; any two RE subsets of the K RE subsets are orthogonal in the time domain, and the first bit block is mapped to at least one RE subset of the K RE subsets; the first bit block is mapped to a number of REs in the K RE subsets not greater than a first constraint value, a product of a target value and a number of REs included in a target RE subset is used to determine the first constraint value, and the second RE set includes the target RE subset; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the target value is a first value; the target value is a second value when the target RE subset belongs to only one of the K RE subsets.

As an embodiment, when the K RE subsets are commonly used to determine the size of the second bit block, the target RE subset belongs to a plurality of RE subsets of the K RE subsets; when only one of the K RE subsets is used to determine the size of the second bit block, the target RE subset belongs to only one of the K RE subsets.

As one embodiment, when the K RE subsets are collectively used to determine the size of the second bit block, the K RE subsets are collectively used to transmit one repetition of the second bit block; when only one of the K RE subsets is used to determine the size of the second bit block, the K RE subsets are used to transmit K repetitions of the second bit block, respectively.

As an embodiment, the first value is one value in a first set and the second value is one value in a second set, the first set and the second set being different; the first set includes more than one value and the second set includes more than one value.

As an embodiment, the number of REs in the K RE subsets mapped to the first bit block is not greater than a minimum of a first reference value and the first constraint value; the second signaling indicates a first offset, which is used to determine the first reference value.

As an embodiment, a product of the first offset and a number of REs comprised by a reference RE subset comprising the target RE subset is used to determine the first reference value; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the reference RE subset belongs to a plurality of RE subsets of the K RE subsets; when the target RE subset belongs to only one of the K RE subsets, the reference RE subset belongs to only one of the K RE subsets.

As an embodiment, the first bit block is mapped to only a first subset of REs out of the K subsets of REs, the first subset of REs being one of the K subsets of REs, the number of REs of the K subsets of REs to which the first bit block is mapped being the number of REs of the first subset of REs to which the first bit block is mapped; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the number of REs in the first bit block mapped to the first RE subset is equal to a minimum of the first reference value, the first constraint value, and a second constraint value; the second constraint value is not greater than a number of REs included in the first subset of REs.

Example 13

Embodiment 13 illustrates a block diagram of a processing apparatus for use in a second node device according to one embodiment of the present application; as shown in fig. 13. In fig. 13, the processing means 1300 in the second node device comprises a second transmitter 1301 and a second receiver 1302.

As an embodiment, the second node device is a base station device.

As an embodiment, the second node device is a user equipment.

As an embodiment, the second node device is a relay node device.

As an example, the second transmitter 1301 includes at least one of { antenna 420, transmitter 418, transmit processor 416, multi-antenna transmit processor 471, controller/processor 475, memory 476} in example 4.

As an example, the second receiver 1302 includes at least one of { antenna 420, receiver 418, receive processor 470, multi-antenna receive processor 472, controller/processor 475, memory 476} in example 4.

A second transmitter 1301 that transmits first signaling, which is used to indicate a first set of REs; transmitting second signaling, the second signaling being used to indicate a second set of REs;

A second receiver 1302 that receives a first block of bits and a second block of bits in the second set of REs;

in embodiment 13, the first set of REs is reserved for the first bit block and the second set of REs is reserved for the second bit block, the first set of REs and the second set of REs overlapping in the time domain; the second set of REs comprises K subsets of REs, K being a positive integer greater than 1; any two RE subsets of the K RE subsets are orthogonal in the time domain, and the first bit block is mapped to at least one RE subset of the K RE subsets; the first bit block is mapped to a number of REs in the K RE subsets not greater than a first constraint value, a product of a target value and a number of REs included in a target RE subset is used to determine the first constraint value, and the second RE set includes the target RE subset; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the target value is a first value; the target value is a second value when the target RE subset belongs to only one of the K RE subsets.

As an embodiment, when the K RE subsets are commonly used to determine the size of the second bit block, the target RE subset belongs to a plurality of RE subsets of the K RE subsets; when only one of the K RE subsets is used to determine the size of the second bit block, the target RE subset belongs to only one of the K RE subsets.

As one embodiment, when the K RE subsets are collectively used to determine the size of the second bit block, the K RE subsets are collectively used to transmit one repetition of the second bit block; when only one of the K RE subsets is used to determine the size of the second bit block, the K RE subsets are used to transmit K repetitions of the second bit block, respectively.

As an embodiment, the first value is one value in a first set and the second value is one value in a second set, the first set and the second set being different; the first set includes more than one value and the second set includes more than one value.

As an embodiment, the number of REs in the K RE subsets mapped to the first bit block is not greater than a minimum of a first reference value and the first constraint value; the second signaling indicates a first offset, which is used to determine the first reference value.

As an embodiment, a product of the first offset and a number of REs comprised by a reference RE subset comprising the target RE subset is used to determine the first reference value; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the reference RE subset belongs to a plurality of RE subsets of the K RE subsets; when the target RE subset belongs to only one of the K RE subsets, the reference RE subset belongs to only one of the K RE subsets.

As an embodiment, the first bit block is mapped to only a first subset of REs out of the K subsets of REs, the first subset of REs being one of the K subsets of REs, the number of REs of the K subsets of REs to which the first bit block is mapped being the number of REs of the first subset of REs to which the first bit block is mapped; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the number of REs in the first bit block mapped to the first RE subset is equal to a minimum of the first reference value, the first constraint value, and a second constraint value; the second constraint value is not greater than a number of REs included in the first subset of REs.

Those of ordinary skill in the art will appreciate that all or a portion of the steps of the above-described methods may be implemented by a program that instructs associated hardware, and the program may be stored on a computer readable storage medium, such as a read-only memory, a hard disk or an optical disk. Alternatively, all or part of the steps of the above embodiments may be implemented using one or more integrated circuits. Accordingly, each module unit in the above embodiment may be implemented in a hardware form or may be implemented in a software functional module form, and the application is not limited to any specific combination of software and hardware. User equipment, terminals and UEs in the present application include, but are not limited to, unmanned aerial vehicles, communication modules on unmanned aerial vehicles, remote control airplanes, aircraft, mini-planes, mobile phones, tablet computers, notebooks, vehicle-mounted communication devices, wireless sensors, network cards, internet of things terminals, RFID terminals, NB-IOT terminals, MTC (Machine Type Communication ) terminals, eMTC (enhanced MTC) terminals, data cards, network cards, vehicle-mounted communication devices, low cost mobile phones, low cost tablet computers, and other wireless communication devices. The base station or system device in the present application includes, but is not limited to, a macro cell base station, a micro cell base station, a home base station, a relay base station, a gNB (NR node B) NR node B, a TRP (Transmitter Receiver Point, transmitting and receiving node), and other wireless communication devices.

The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the scope of the present application. Any changes and modifications made based on the embodiments described in the specification should be considered obvious and within the scope of the present invention if similar partial or full technical effects can be obtained.

Claims (10)

1. A first node device for wireless communication, comprising:

a first receiver that receives first signaling, the first signaling being used to indicate a first set of REs; receiving second signaling, the second signaling being used to indicate a second set of REs;

a first transmitter transmitting a first bit block and a second bit block in the second RE set;

wherein the first RE set is reserved for the first bit block, the second RE set is reserved for the second bit block, and the first RE set and the second RE set overlap in the time domain; the second set of REs comprises K subsets of REs, K being a positive integer greater than 1; any two RE subsets of the K RE subsets are orthogonal in the time domain, and the first bit block is mapped to at least one RE subset of the K RE subsets; the first bit block is mapped to a number of REs in the K RE subsets not greater than a first constraint value, a product of a target value and a number of REs included in a target RE subset is used to determine the first constraint value, and the second RE set includes the target RE subset; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the target value is a first value; the target value is a second value when the target RE subset belongs to only one of the K RE subsets.

2. The first node device of claim 1, wherein the target subset of REs belongs to a plurality of subsets of REs among the K subsets of REs when the K subsets of REs are collectively used to determine the size of the second bit block; when only one of the K RE subsets is used to determine the size of the second bit block, the target RE subset belongs to only one of the K RE subsets.

3. The first node device of claim 1 or 2, wherein when the K RE subsets are collectively used to determine the size of the second bit block, the K RE subsets are collectively used to transmit one repetition of the second bit block; when only one of the K RE subsets is used to determine the size of the second bit block, the K RE subsets are used to transmit K repetitions of the second bit block, respectively.

4. A first node device according to any of claims 1-3, characterized in that the first value is one value of a first set and the second value is one value of a second set, the first set and the second set being different; the first set includes more than one value and the second set includes more than one value.

5. The first node device of any of claims 1-4, wherein the number of REs in the K RE subsets to which the first bit block is mapped is not greater than a minimum of a first reference value and the first constraint value; the second signaling indicates a first offset, which is used to determine the first reference value.

6. The first node device of claim 5, wherein a product of the first offset and a number of REs included in a reference RE subset, the reference RE subset including the target RE subset, is used to determine the first reference value; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the reference RE subset belongs to a plurality of RE subsets of the K RE subsets; when the target RE subset belongs to only one of the K RE subsets, the reference RE subset belongs to only one of the K RE subsets.

7. The first node device of claim 5 or 6, wherein the first bit block is mapped to only a first subset of REs out of the K subsets of REs, the first subset of REs being one of the K subsets of REs, the number of REs of the first bit block mapped to the K subsets of REs being the number of REs of the first bit block mapped to the first subset of REs; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the number of REs in the first bit block mapped to the first RE subset is equal to a minimum of the first reference value, the first constraint value, and a second constraint value; the second constraint value is not greater than a number of REs included in the first subset of REs.

8. A second node device for wireless communication, comprising:

a second transmitter that receives first signaling, the first signaling being used to indicate a first set of REs; receiving second signaling, the second signaling being used to indicate a second set of REs;

a second receiver transmitting a first bit block and a second bit block in the second RE set;

wherein the first RE set is reserved for the first bit block, the second RE set is reserved for the second bit block, and the first RE set and the second RE set overlap in the time domain; the second set of REs comprises K subsets of REs, K being a positive integer greater than 1; any two RE subsets of the K RE subsets are orthogonal in the time domain, and the first bit block is mapped to at least one RE subset of the K RE subsets; the first bit block is mapped to a number of REs in the K RE subsets not greater than a first constraint value, a product of a target value and a number of REs included in a target RE subset is used to determine the first constraint value, and the second RE set includes the target RE subset; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the target value is a first value; the target value is a second value when the target RE subset belongs to only one of the K RE subsets.

9. A method in a first node for wireless communication, comprising:

receiving first signaling, the first signaling being used to indicate a first set of REs;

receiving second signaling, the second signaling being used to indicate a second set of REs;

transmitting a first bit block and a second bit block in the second RE set;

wherein the first RE set is reserved for the first bit block, the second RE set is reserved for the second bit block, and the first RE set and the second RE set overlap in the time domain; the second set of REs comprises K subsets of REs, K being a positive integer greater than 1; any two RE subsets of the K RE subsets are orthogonal in the time domain, and the first bit block is mapped to at least one RE subset of the K RE subsets; the first bit block is mapped to a number of REs in the K RE subsets not greater than a first constraint value, a product of a target value and a number of REs included in a target RE subset is used to determine the first constraint value, and the second RE set includes the target RE subset; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the target value is a first value; the target value is a second value when the target RE subset belongs to only one of the K RE subsets.

10. A method in a second node for wireless communication, comprising:

transmitting first signaling, the first signaling being used to indicate a first set of REs;

transmitting second signaling, the second signaling being used to indicate a second set of REs;

receiving a first block of bits and a second block of bits in the second set of REs;

wherein the first RE set is reserved for the first bit block, the second RE set is reserved for the second bit block, and the first RE set and the second RE set overlap in the time domain; the second set of REs comprises K subsets of REs, K being a positive integer greater than 1; any two RE subsets of the K RE subsets are orthogonal in the time domain, and the first bit block is mapped to at least one RE subset of the K RE subsets; the first bit block is mapped to a number of REs in the K RE subsets not greater than a first constraint value, a product of a target value and a number of REs included in a target RE subset is used to determine the first constraint value, and the second RE set includes the target RE subset; when the target RE subset belongs to a plurality of RE subsets of the K RE subsets, the target value is a first value; the target value is a second value when the target RE subset belongs to only one of the K RE subsets.

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