CN116112042A - Demodulation circuit, electronic tag and electronic tag system - Google Patents
Demodulation circuit, electronic tag and electronic tag system Download PDFInfo
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- CN116112042A CN116112042A CN202310097201.7A CN202310097201A CN116112042A CN 116112042 A CN116112042 A CN 116112042A CN 202310097201 A CN202310097201 A CN 202310097201A CN 116112042 A CN116112042 A CN 116112042A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W4/00—Services specially adapted for wireless communication networks; Facilities therefor
- H04W4/80—Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention discloses a demodulation circuit, an electronic tag and an electronic tag system. The demodulation circuit includes: the system comprises a first envelope detection link, a second envelope detection link, a link selection module and a multiplexer; the output end of the first envelope detection link and the output end of the second envelope detection link are electrically connected with the input end of the multiplexer in a one-to-one correspondence manner; the first envelope detection link comprises a first envelope detector, the second envelope detection link comprises a second envelope detector, the sensitivity of the first envelope detector is higher than a first preset value, and the sensitivity of the second envelope detector is lower than a second preset value, wherein the first preset value is larger than or equal to the second preset value; the link selection module is used for outputting a control signal to the control end of the multiplexer according to the level of the first end of the link selection module; the output of the multiplexer is used as the output of the demodulation circuit. The invention can improve the power range of the signal which can be demodulated by the demodulation circuit.
Description
Technical Field
The present invention relates to the field of electronic tags, and in particular, to a demodulation circuit, an electronic tag, and an electronic tag system.
Background
Electronic tags are widely used in the fields of modern electronic technology, such as the Internet of things. The direct communication mode between the communication base station and the electronic tag is also one of the popular directions for research and application.
Compared with the communication mode of the common reader-electronic tag, the communication mode of the base station reader-electronic tag has a longer communication distance (hundreds of meters), the energy range obtained by the electronic tag is very large, the electromagnetic field power which can be obtained by the electronic tag at the far end (about 300m from the base station) is about-50 dbm, and the electromagnetic field power which can be obtained by the electronic tag at the near end (about 40m from the base station) can be up to-10 dbm, which means that the requirement on the input dynamic range of the electronic tag is at least-50 dbm to-10 dbm.
However, it is difficult for the demodulation circuit in the existing electronic tag to cover such a wide input power range.
Disclosure of Invention
The invention provides a demodulation circuit, an electronic tag and an electronic tag system, which are used for improving the power range of a signal which can be demodulated by the demodulation circuit.
According to an aspect of the present invention, there is provided a demodulation circuit including:
the system comprises a first envelope detection link, a second envelope detection link, a link selection module and a multiplexer;
the input end of the first envelope detection link is electrically connected with the input end of the second envelope detection link and then used as the signal input end of the demodulation circuit, and the output end of the first envelope detection link and the output end of the second envelope detection link are electrically connected with the input end of the multiplexer in a one-to-one correspondence manner; the first envelope detection link comprises a first envelope detector, the second envelope detection link comprises a second envelope detector, the sensitivity of the first envelope detector is higher than a first preset value, and the sensitivity of the second envelope detector is lower than a second preset value, wherein the first preset value is larger than or equal to the second preset value;
the first end of the link selection module is electrically connected with the output end of the first envelope detector or the output end of the second envelope detector, the second end of the link selection module is electrically connected with the control end of the multiplexer, and the link selection module is used for outputting a control signal to the control end of the multiplexer according to the level of the first end of the link selection module;
the output end of the multiplexer is used as the output end of the demodulation circuit.
Optionally, the link selection module includes:
a first comparator, a first input end of which is used as a first end of the link selection module, and a second end of which is connected with a reference voltage;
the input end of the trigger is electrically connected with the output end of the first comparator, the clock end of the trigger is connected with a power detection enabling signal, the setting end of the trigger is connected with a demodulation enabling signal, and the output end of the trigger is used as the second end of the link selection module.
Optionally, the start time of the active level of the demodulation enable signal is earlier than or equal to the start time of the active level of the power detection enable signal; and the active level of the power detection enable signal continues for a preset time.
Optionally, the first envelope detection link further includes:
a baseband amplifier, a first low pass filter, and a second comparator;
the input end of the first envelope detector is used as the input end of the first envelope detection link, the output end of the first envelope detector is electrically connected with the input end of the baseband amplifier, and the output end of the baseband amplifier is electrically connected with the first input end of the second comparator;
the input end of the first low-pass filter is electrically connected with the output end of the baseband amplifier, and the output end of the first low-pass filter is electrically connected with the second input end of the second comparator;
the output end of the second comparator is used as the output end of the first envelope detection link.
Optionally, the first envelope detection link further includes a first buffer, and an output terminal of the first envelope detector is electrically connected to an input terminal of the baseband amplifier through the first buffer.
Optionally, the second packet detection link further includes: a second low pass filter and a third comparator;
the input end of the second envelope detector is used as the input end of the second envelope detection link, and the output end of the second envelope detector is electrically connected with the first input end of the third comparator;
the input end of the second low-pass filter is electrically connected with the output end of the second envelope detector, and the output end of the second low-pass filter is electrically connected with the second input end of the third comparator;
the output end of the third comparator is used as the output end of the second envelope detection link.
Optionally, the second envelope detection link further includes a second buffer, and an output end of the second envelope detector is electrically connected to the first input end of the third comparator through the second buffer.
Optionally, the first envelope detector comprises a subthreshold biased single tube amplifier and the second envelope detector comprises a diode-connected transistor.
According to another aspect of the present invention, there is provided an electronic tag including the demodulation circuit described above.
According to another aspect of the present invention, there is provided an electronic tag system comprising the electronic tag described above and a reader for transmitting a radio frequency signal, wherein the radio frequency signal comprises an unmodulated portion and a modulated portion arranged in sequence.
According to the technical scheme of the embodiment of the invention, the adopted demodulation circuit comprises: the system comprises a first envelope detection link, a second envelope detection link, a link selection module and a multiplexer; the input end of the first envelope detection link is electrically connected with the input end of the second envelope detection link and then used as the signal input end of the demodulation circuit, and the output end of the first envelope detection link and the output end of the second envelope detection link are correspondingly and electrically connected with the input end of the multiplexer one by one; the first envelope detection link comprises a first envelope detector, the second envelope detection link comprises a second envelope detector, the sensitivity of the first envelope detector is higher than a first preset value, and the sensitivity of the second envelope detector is lower than a second preset value, wherein the first preset value is larger than or equal to the second preset value; the first end of the link selection module is electrically connected with the output end of the first envelope detector or the output end of the second envelope detector, the second end of the link selection module is electrically connected with the control end of the multiplexer, and the link selection module is used for outputting a control signal to the control end of the multiplexer according to the level of the first end of the link selection module; the output of the multiplexer is used as the output of the demodulation circuit. According to the embodiment, the demodulated envelope detection link can be automatically selected according to the power of the radio frequency signal, so that the power range of the signal which can be demodulated by the demodulation circuit can be improved.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic circuit diagram of a demodulation circuit according to a first embodiment of the present invention;
fig. 2 is a schematic circuit diagram of a demodulation circuit according to a second embodiment of the present invention;
fig. 3 is a schematic circuit diagram of a demodulation circuit according to a third embodiment of the present invention;
fig. 4 is a schematic structural diagram of an electronic tag according to a fourth embodiment of the present invention;
fig. 5 is a schematic structural diagram of an electronic tag system according to a fifth embodiment of the present invention;
fig. 6 is a timing chart of a radio frequency signal according to a fifth embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example 1
Fig. 1 is a schematic circuit diagram of a demodulation circuit according to a first embodiment of the present invention, and referring to fig. 1, the demodulation circuit includes: a first envelope detection link 11, a second envelope detection link 12, a link selection module 13, and a multiplexer 14; the input end of the first envelope detection link 11 is electrically connected with the input end of the second envelope detection link 12 and then used as the signal input end Vin of the demodulation circuit, and the output end of the first envelope detection link 11 and the output end of the second envelope detection link 12 are electrically connected with the input end of the multiplexer 14 in a one-to-one correspondence manner; wherein the first envelope detection link 11 comprises a first envelope detector 111, the second envelope detection link 12 comprises a second envelope detector 121, the sensitivity of the first envelope detector 111 is higher than a first preset value, and the sensitivity of the second envelope detector 121 is lower than a second preset value, wherein the first preset value is greater than or equal to the second preset value; the first end of the link selection module 13 is electrically connected with the output end of the first envelope detector 111 or the output end of the second envelope detector 121, the second end of the link selection module 13 is electrically connected with the control end of the multiplexer 14, and the link selection module 13 is used for outputting a control signal to the output end of the multiplexer 14 according to the level of the first end; the output of the multiplexer 14 serves as the output of the demodulation circuit.
Optionally, the input terminal Vin of the demodulation circuit is used for inputting a radio frequency signal, and the radio frequency signal has a larger power range. The sensitivity of the envelope detector represents the sensitivity to the magnitude of the input signal power. The higher sensitivity of the envelope detector means that an undistorted envelope waveform can be obtained at the time of lower power radio frequency signal input; the lower sensitivity of the envelope detector means that an undistorted envelope waveform can be obtained at the input of the higher power radio frequency signal. The sensitivity of the first envelope detector 111 is higher than a first preset value, and the sensitivity of the second envelope detector 121 is lower than a second preset value, so that the first envelope detection link can match the radio frequency signal with lower power, i.e. can demodulate the radio frequency signal with lower power without distortion; the second envelope detection link is capable of matching, i.e. demodulating, the higher power radio frequency signal without distortion. It should be noted that, the first preset value and the second preset value may be specifically set according to an application environment of the demodulation circuit, which is not specifically limited in this embodiment.
The envelope detector outputs the detected envelope to the link selection module, the link selection module judges the power of the radio frequency signal according to the signal at the first end of the link selection module, if the judging power is smaller, a first control signal is generated, the output end of the multipath selector is electrically connected with the first input end of the multipath selector, at the moment, the radio frequency signal is demodulated through the first envelope detection link, and the low-power signal is guaranteed not to be distorted after demodulation. If the power is judged to be larger, a second control signal is generated, so that the output end of the multi-path selector is electrically connected with the second input end of the multi-path selector, and at the moment, the radio frequency signal is demodulated through a second envelope detection link, so that the high-power signal is ensured not to be distorted after demodulation. That is, the present embodiment may automatically select the demodulated link according to the power of the radio frequency signal, so as to increase the power range of the signal that the demodulation circuit can demodulate.
According to the technical scheme of the embodiment, the adopted demodulation circuit comprises: the system comprises a first envelope detection link, a second envelope detection link, a link selection module and a multiplexer; the input end of the first envelope detection link is electrically connected with the input end of the second envelope detection link and then used as the signal input end of the demodulation circuit, and the output end of the first envelope detection link and the output end of the second envelope detection link are correspondingly and electrically connected with the input end of the multiplexer one by one; the first envelope detection link comprises a first envelope detector, the second envelope detection link comprises a second envelope detector, the sensitivity of the first envelope detector is higher than a first preset value, and the sensitivity of the second envelope detector is lower than a second preset value, wherein the first preset value is larger than or equal to the second preset value; the first end of the link selection module is electrically connected with the output end of the first envelope detector or the output end of the second envelope detector, the second end of the link selection module is electrically connected with the control end of the multiplexer, and the link selection module is used for outputting a control signal to the control end of the multiplexer according to the level of the first end of the link selection module; the output of the multiplexer is used as the output of the demodulation circuit. According to the embodiment, the demodulated envelope detection link can be automatically selected according to the power of the radio frequency signal, so that the power range of the signal which can be demodulated by the demodulation circuit can be improved.
Example two
Fig. 2 is a schematic circuit diagram of a demodulation circuit according to a second embodiment of the present invention, and referring to fig. 2, in this embodiment, a first end of a link selection module 13 is electrically connected to an output end of a first envelope detector 111.
The first envelope detector 111 is illustratively a square law device, the lower the signal level output by its output when the signal power input by its input is higher. Conversely, the lower the signal power input at its input, the higher the signal level output at its output.
When the radio frequency signal input by the signal input end Vin of the demodulation circuit is low, the signal level output by the first envelope detector 111 is high, the signal level of the first end of the link selection module 13 is also high, and the link selection module generates a first control signal according to the received high level to control the output end of the multiplexer to be conducted with the first input end of the multiplexer. When the radio frequency signal input by the signal input end Vin of the demodulation circuit is higher, the signal level output by the first envelope detector 111 is lower, the signal level of the first end of the link selection module 13 is also lower, and the link selection module generates a second control signal according to the received lower level, so as to control the output end of the multiplexer to be conducted with the second input end of the multiplexer.
Alternatively, as shown in fig. 2, the link selection module 13 includes: a first comparator 131, wherein a first input end of the first comparator 131 is used as a first end of the link selection module 13, and a second end of the first comparator 131 is connected with a reference voltage Vref; the input end of the trigger 132 is electrically connected to the output end of the first comparator 131, the clock end Clk of the trigger 132 is connected to the power detection enable signal Vgl, the set end Rst of the trigger 132 is connected to the demodulation enable signal Vjt, and the output end of the trigger 132 is used as the second end of the link selection module 13.
Specifically, when the power of the radio frequency signal is low, the signal level output by the first envelope detector 111 is high, and when the power is higher than the reference voltage Vref, the first comparator Vref outputs a first comparison signal, and the trigger 132 transmits the first comparison signal to the multiplexer according to the power detection enable signal Vgl and the demodulation enable signal Vjt, so that the multiplexer turns on its first input terminal and its output terminal. The first comparison signal may be 0 or 1, which is not specifically limited in this embodiment. When the power of the radio frequency signal is high, the signal level output by the first envelope detector 111 is low, and when the power is lower than the reference voltage Vref, the first comparator Vref outputs a second comparison signal, and the trigger 132 transmits the second comparison signal to the multiplexer according to the power detection enable signal Vgl and the demodulation enable signal Vjt, so that the multiplexer turns on the second input terminal thereof with the output terminal thereof.
Preferably, as shown in fig. 2, the start timing of the active level of the demodulation enable signal Vjt is earlier than or equal to the start timing of the active level of the power detection enable signal Vgl; and the active level of the power detection enable signal Vgl continues for a preset time.
Specifically, the flip-flop 132 is an edge D flip-flop, and the demodulation enable signal Vjt and the power detection enable signal Vgl may be active high. On the falling edge of the power sense enable signal Vgl, the input signal of the flip-flop is transmitted to the output of the flip-flop 132. In this embodiment, the demodulation enable signal Vjt is always in an active state during demodulation, and the power detection enable signal Vgl is a pulse signal. By setting the starting time of the effective level of the demodulation enabling signal Vjt to be earlier than or equal to the starting time of the effective level of the power detection enabling signal Vgl, power detection can be performed every time the demodulation function is started, and the detection result can be transmitted to the output end of the trigger, so that the correct envelope detection link can be selected for demodulation. Preferably, the start time of the active level of the demodulation enable signal Vjt is equal to the start time of the active level of the power detection enable signal Vgl, ensuring that the power detection is enabled first time each demodulation starts. It should be noted that, the active level of the power detection enable signal Vgl only needs to last for a short period of time, for example, within 1 ms.
Note that, when the demodulation enable signal Vjt is at an inactive level, the output terminal of the flip-flop 132 may output the first control signal or the second control signal.
Optionally, with continued reference to fig. 2, the first envelope detection link 11 further includes: a baseband amplifier 112, a first low-pass filter 113, and a second comparator 114; the input end of the first envelope detector 111 serves as the input end of the first envelope detection link 11, the output end of the first envelope detector 111 is electrically connected with the input end of the baseband amplifier 112, and the output end of the baseband amplifier 112 is electrically connected with the first input end of the second comparator 114; an input end of the first low-pass filter 113 is electrically connected to an output end of the baseband amplifier 112, and an output end of the first low-pass filter 113 is electrically connected to a second input end of the second comparator 114; the output of the second comparator 114 serves as the output of the first envelope detection link 11.
Specifically, since the first envelope detection link 11 is used for demodulating a radio frequency signal with smaller power, the amplitude of the radio frequency signal may not reach the threshold value processed by the second comparator 114, and therefore the output signal of the first envelope detector 111 may be amplified by the baseband amplifier 112 and then input to the second comparator 114, so as to reach the threshold value processed by the second comparator 114. The first low-pass filter 113 is configured to low-pass filter the output signal of the first envelope detector 111, so that a low-frequency signal is output to the second comparator 114. The second comparator 114 is configured to compare the low frequency signal of the first low pass filter 113 with the output signal of the first envelope detector 111, thereby recovering modulation information in the radio frequency signal.
Optionally, with continued reference to fig. 2, the first envelope detection link 11 further comprises a first buffer 115, and the output of the first envelope detector 111 is electrically connected to the input of the baseband amplifier 112 via the first buffer 115.
Specifically, the first buffer 115 is used to enhance the driving capability so that the output signal of the first envelope detector 111 can be transmitted to the baseband amplifier 112 without distortion.
Optionally, with continued reference to fig. 2, the second packet detection link 12 further includes: a second low-pass filter 122 and a third comparator 123; the input end of the second envelope detector 121 is used as the input end of the second envelope detection link 12, and the output end of the second envelope detector 121 is electrically connected with the first input end of the third comparator 123; an input end of the second low-pass filter 122 is electrically connected to an output end of the second envelope detector 121, and an output end of the second low-pass filter 122 is electrically connected to a second input end of the third comparator 123; the output of the third comparator 123 serves as the output of the second envelope detection link 12.
Specifically, the second low-pass filter 122 is configured to low-pass filter the output signal of the second envelope detector 121, so that the low-frequency signal is output to the third comparator 123. The third comparator 123 is configured to compare the low frequency signal of the second low pass filter 122 with the output signal of the second envelope detector 121, thereby recovering the modulation information in the radio frequency signal.
Optionally, with continued reference to fig. 2, the second packet detection link 12 further includes a second buffer 124, and an output terminal of the second packet detector 121 is electrically connected to the first input terminal of the third comparator 123 through the second buffer 124.
Specifically, the second buffer 124 is used to enhance driving capability so that the output signal of the second envelope detector 121 can be transmitted to the third comparator 123 and the second low-pass filter 122 without distortion.
Illustratively, the first envelope detector 111 comprises a subthreshold biased single tube amplifier and the second envelope detector 121 comprises a diode-connected transistor.
Specifically, when the envelope detection is performed by using a diode-connected transistor, the envelope detector can normally operate only when the amplitude of the radio frequency signal is greater than the threshold voltage of the transistor, and thus the reception sensitivity thereof is low. When the subthreshold biased single-tube amplifier is used for envelope detection, the normal working voltage is lower, so that the sensitivity is higher. Of course, in other embodiments, the first envelope detector and the second envelope detector may be in other circuit forms as long as the sensitivity requirement is met.
Example III
Fig. 3 is a schematic circuit diagram of a demodulation circuit according to a third embodiment of the present invention, and referring to fig. 3, in this embodiment, the first end of the link selection module 13 is electrically connected to the output end of the second envelope detector 121.
The second envelope detector 121 is illustratively a square law device, and the higher the signal power input at its input, the lower the signal level output at its output. Conversely, the lower the signal power input at its input, the higher the signal level output at its output.
When the radio frequency signal input by the signal input end Vin of the demodulation circuit is low, the signal level output by the second envelope detector 121 is high, the signal level of the first end of the link selection module 13 is also high, and the link selection module generates a first control signal according to the received high level to control the output end of the multiplexer to be conducted with the first input end of the multiplexer. When the radio frequency signal input by the signal input end Vin of the demodulation circuit is higher, the signal level output by the second envelope detector 121 is lower, the signal level of the first end of the link selection module 13 is also lower, and the link selection module generates a second control signal according to the received lower level, so as to control the output end of the multiplexer to be conducted with the second input end of the multiplexer.
Alternatively, as shown in fig. 3, the link selection module 13 includes: a first comparator 131, wherein a first input end of the first comparator 131 is used as a first end of the link selection module 13, and a second end of the first comparator 131 is connected with a reference voltage Vref; the input end of the trigger 132 is electrically connected to the output end of the first comparator 131, the clock end Clk of the trigger 132 is connected to the power detection enable signal Vgl, the set end Rst of the trigger 132 is connected to the demodulation enable signal Vjt, and the output end of the trigger 132 is used as the second end of the link selection module 13.
Specifically, when the power of the radio frequency signal is low, the signal level output by the second envelope detector 121 is high, and when the power is higher than the reference voltage Vref, the first comparator Vref outputs the first comparison signal, and the flip-flop 132 transmits the first comparison signal to the multiplexer according to the power detection enable signal Vgl and the demodulation enable signal Vjt, so that the multiplexer turns on the first input terminal thereof from the output terminal thereof. The first comparison signal may be 0 or 1, which is not specifically limited in this embodiment. When the power of the radio frequency signal is high, the signal level output by the second envelope detector 121 is low, and when the power is lower than the reference voltage Vref, the first comparator Vref outputs a second comparison signal, and the trigger 132 transmits the second comparison signal to the multiplexer according to the power detection enable signal Vgl and the demodulation enable signal Vjt, so that the multiplexer turns on the second input terminal thereof with the output terminal thereof.
Preferably, as shown in fig. 3, the start timing of the active level of the demodulation enable signal Vjt is earlier than or equal to the start timing of the active level of the power detection enable signal Vgl; and the active level of the power detection enable signal Vgl continues for a preset time.
Specifically, the flip-flop 132 is an edge D flip-flop, and the demodulation enable signal Vjt and the power detection enable signal Vgl may be active high. On the falling edge of the power sense enable signal Vgl, the input signal of the flip-flop is transmitted to the output of the flip-flop 132. In this embodiment, the demodulation enable signal Vjt is always in an active state during demodulation, and the power detection enable signal Vgl is a pulse signal. By setting the starting time of the effective level of the demodulation enabling signal Vjt to be earlier than or equal to the starting time of the effective level of the power detection enabling signal Vgl, power detection can be performed every time the demodulation function is started, and the detection result can be transmitted to the output end of the trigger, so that the correct envelope detection link can be selected for demodulation. Preferably, the start time of the active level of the demodulation enable signal Vjt is equal to the start time of the active level of the power detection enable signal Vgl, ensuring that the power detection is enabled first time each demodulation starts. It should be noted that, the active level of the power detection enable signal Vgl only needs to last for a short period of time, for example, within 1 ms.
Note that, when the demodulation enable signal Vjt is at an inactive level, the output terminal of the flip-flop 132 may output the first control signal or the second control signal.
Optionally, with continued reference to fig. 3, the first envelope detection link 11 further includes: a baseband amplifier 112, a first low-pass filter 113, and a second comparator 114; the input end of the first envelope detector 111 serves as the input end of the first envelope detection link 11, the output end of the first envelope detector 111 is electrically connected with the input end of the baseband amplifier 112, and the output end of the baseband amplifier 112 is electrically connected with the first input end of the second comparator 114; an input end of the first low-pass filter 113 is electrically connected to an output end of the baseband amplifier 112, and an output end of the first low-pass filter 113 is electrically connected to a second input end of the second comparator 114; the output of the second comparator 114 serves as the output of the first envelope detection link 11.
Specifically, since the first envelope detection link 11 is used for demodulating a radio frequency signal with smaller power, the amplitude of the radio frequency signal may not reach the threshold value processed by the second comparator 114, and therefore the output signal of the first envelope detector 111 may be amplified by the baseband amplifier 112 and then input to the second comparator 114, so as to reach the threshold value processed by the second comparator 114. The first low-pass filter 113 is configured to low-pass filter the output signal of the first envelope detector 111, so that a low-frequency signal is output to the second comparator 114. The second comparator 114 is configured to compare the low frequency signal of the first low pass filter 113 with the output signal of the first envelope detector 111, thereby recovering modulation information in the radio frequency signal.
Optionally, with continued reference to fig. 3, the first envelope detection link 11 further comprises a first buffer 115, and the output of the first envelope detector 111 is electrically connected to the input of the baseband amplifier 112 through the first buffer 115.
Specifically, the first buffer 115 is used to enhance the driving capability so that the output signal of the first envelope detector 111 can be transmitted to the baseband amplifier 112 without distortion.
Optionally, with continued reference to fig. 3, the second packet detection link 12 further includes: a second low-pass filter 122 and a third comparator 123; the input end of the second envelope detector 121 is used as the input end of the second envelope detection link 12, and the output end of the second envelope detector 121 is electrically connected with the first input end of the third comparator 123; an input end of the second low-pass filter 122 is electrically connected to an output end of the second envelope detector 121, and an output end of the second low-pass filter 122 is electrically connected to a second input end of the third comparator 123; the output of the third comparator 123 serves as the output of the second envelope detection link 12.
Specifically, the second low-pass filter 122 is configured to low-pass filter the output signal of the second envelope detector 121, so that the low-frequency signal is output to the third comparator 123. The third comparator 123 is configured to compare the low frequency signal of the second low pass filter 122 with the output signal of the second envelope detector 121, thereby recovering the modulation information in the radio frequency signal.
Optionally, with continued reference to fig. 3, the second packet detection link 12 further includes a second buffer 124, and an output terminal of the second packet detector 121 is electrically connected to the first input terminal of the third comparator 123 through the second buffer 124.
Specifically, the second buffer 124 is used to enhance driving capability so that the output signal of the second envelope detector 121 can be transmitted to the third comparator 123 and the second low-pass filter 122 without distortion.
Illustratively, the first envelope detector 111 comprises a subthreshold biased single tube amplifier and the second envelope detector 121 comprises a diode-connected transistor.
Specifically, when the envelope detection is performed by using a diode-connected transistor, the envelope detector can normally operate only when the amplitude of the radio frequency signal is greater than the threshold voltage of the transistor, and thus the reception sensitivity thereof is low. When the subthreshold biased single-tube amplifier is used for envelope detection, the normal working voltage is lower, so that the sensitivity is higher. Of course, in other embodiments, the first envelope detector and the second envelope detector may be in other circuit forms as long as the sensitivity requirement is met.
Example IV
The present invention also provides an electronic tag, as shown in fig. 4, fig. 4 is a schematic structural diagram of an electronic tag provided in the fourth embodiment of the present invention, and the electronic tag 2 includes the demodulation circuit 21 provided in any embodiment of the present invention, so that the electronic tag has the same beneficial effects and is not described herein again.
Example five
The invention also provides an electronic tag system, as shown in fig. 5, fig. 5 is a schematic structural diagram of an electronic tag system provided by a fifth embodiment of the invention, fig. 6 is a timing chart of a radio frequency signal provided by the fifth embodiment of the invention, the electronic tag system comprises an electronic tag 2 and a reader 3 provided by a fourth embodiment of the invention, and the reader 3 is used for transmitting the radio frequency signal; wherein the radio frequency signal comprises an unmodulated portion Rf1 and a modulated portion Rf2 arranged in sequence.
The electronic tag system provided by the embodiment of the invention comprises the electronic tag provided by the embodiment of the invention, so that the electronic tag system has the same beneficial effects and is not described in detail herein.
In addition, the radio frequency signal includes an unmodulated portion Rf1 and a modulated portion Rf2, the unmodulated portion Rf1 preceding the modulated portion Rf2 in time sequence. The demodulation circuit 21 performs power detection during the duration of the modulation portion Rf2, and at this time, the peak-to-peak value of the radio frequency signal is a constant value, so that the output signal of the envelope detector is a constant level, and the result of power detection is not affected by the modulation signal, thereby ensuring the accuracy of power detection.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (10)
1. A demodulation circuit, the demodulation circuit comprising:
the system comprises a first envelope detection link, a second envelope detection link, a link selection module and a multiplexer;
the input end of the first envelope detection link is electrically connected with the input end of the second envelope detection link and then used as the signal input end of the demodulation circuit, and the output end of the first envelope detection link and the output end of the second envelope detection link are electrically connected with the input end of the multiplexer in a one-to-one correspondence manner; the first envelope detection link comprises a first envelope detector, the second envelope detection link comprises a second envelope detector, the sensitivity of the first envelope detector is higher than a first preset value, and the sensitivity of the second envelope detector is lower than a second preset value, wherein the first preset value is larger than or equal to the second preset value;
the first end of the link selection module is electrically connected with the output end of the first envelope detector or the output end of the second envelope detector, the second end of the link selection module is electrically connected with the control end of the multiplexer, and the link selection module is used for outputting a control signal to the control end of the multiplexer according to the level of the first end of the link selection module;
the output end of the multiplexer is used as the output end of the demodulation circuit.
2. The demodulation circuit of claim 1, wherein the link selection module comprises:
a first comparator, a first input end of which is used as a first end of the link selection module, and a second end of which is connected with a reference voltage;
the input end of the trigger is electrically connected with the output end of the first comparator, the clock end of the trigger is connected with a power detection enabling signal, the setting end of the trigger is connected with a demodulation enabling signal, and the output end of the trigger is used as the second end of the link selection module.
3. The demodulation circuit according to claim 2, wherein a start timing of an active level of the demodulation enable signal is earlier than or equal to a start timing of an active level of the power detection enable signal; and the active level of the power detection enable signal continues for a preset time.
4. The demodulation circuit of claim 2, wherein the first envelope detection link further comprises:
a baseband amplifier, a first low pass filter, and a second comparator;
the input end of the first envelope detector is used as the input end of the first envelope detection link, the output end of the first envelope detector is electrically connected with the input end of the baseband amplifier, and the output end of the baseband amplifier is electrically connected with the first input end of the second comparator;
the input end of the first low-pass filter is electrically connected with the output end of the baseband amplifier, and the output end of the first low-pass filter is electrically connected with the second input end of the second comparator;
the output end of the second comparator is used as the output end of the first envelope detection link.
5. The demodulation circuit of claim 4, wherein the first envelope detection link further comprises a first buffer, an output of the first envelope detector being electrically connected to an input of the baseband amplifier through the first buffer.
6. The demodulation circuit of claim 2, wherein the second envelope detection link further comprises: a second low pass filter and a third comparator;
the input end of the second envelope detector is used as the input end of the second envelope detection link, and the output end of the second envelope detector is electrically connected with the first input end of the third comparator;
the input end of the second low-pass filter is electrically connected with the output end of the second envelope detector, and the output end of the second low-pass filter is electrically connected with the second input end of the third comparator;
the output end of the third comparator is used as the output end of the second envelope detection link.
7. The demodulation circuit of claim 6, wherein the second envelope detector link further comprises a second buffer, the output of the second envelope detector being electrically connected to the first input of the third comparator through the second buffer.
8. The demodulation circuit of claim 1, wherein the first envelope detector comprises a subthreshold biased single tube amplifier and the second envelope detector comprises a diode-connected transistor.
9. An electronic tag, characterized in that it comprises a demodulation circuit as claimed in any one of claims 1-8.
10. An electronic tag system comprising a reader for transmitting a radio frequency signal and the electronic tag of claim 9, wherein the radio frequency signal comprises an unmodulated portion and a modulated portion in a sequential arrangement.
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| CN202310097201.7A CN116112042A (en) | 2023-02-08 | 2023-02-08 | Demodulation circuit, electronic tag and electronic tag system |
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| CN202310097201.7A CN116112042A (en) | 2023-02-08 | 2023-02-08 | Demodulation circuit, electronic tag and electronic tag system |
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