CN116111985B - Digital filter device - Google Patents

Digital filter device Download PDF

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Publication number
CN116111985B
CN116111985B CN202310376195.9A CN202310376195A CN116111985B CN 116111985 B CN116111985 B CN 116111985B CN 202310376195 A CN202310376195 A CN 202310376195A CN 116111985 B CN116111985 B CN 116111985B
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gate
input end
output end
adder
output
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CN116111985A (en
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张跃玲
万海军
束克留
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Suzhou Powerlink Microelectronics Inc
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Suzhou Powerlink Microelectronics Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0283—Filters characterised by the filter structure
    • H03H17/0286—Combinations of filter structures
    • H03H17/0291—Digital and sampled data filters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/06—Non-recursive filters
    • H03H17/0621—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
    • H03H17/0635—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies
    • H03H17/0671—Cascaded integrator-comb [CIC] filters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H2017/0072—Theoretical filter design
    • H03H2017/0081—Theoretical filter design of FIR filters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Networks Using Active Elements (AREA)
  • Analogue/Digital Conversion (AREA)
  • Filters That Use Time-Delay Elements (AREA)
  • Complex Calculations (AREA)

Abstract

The invention discloses a digital filter device, comprising: CIC and FIR filters; the CIC filter includes: the filter module of self-down counter, first downsampling signal generation circuit, second downsampling signal generation circuit, multistage cascade, the FIR filter includes: the third downsampled signal generating circuit, M adders, a weighting coefficient generating circuit, and a filter circuit. The digital filter device according to the embodiment of the invention can be realized as digital hardware in a digital signal processing algorithm circuit; the digital filter device is provided with an IP module which can be configured to realize digital signal processing of a digital decimation filtering downsampling frequency conversion algorithm and data processing of a CIC digital filter algorithm and a signed FIR digital filter algorithm; the integrated circuit can be integrated in a communication or semiconductor integrated circuit, and has the advantages of low power consumption, strong universality, small occupied area, instantaneity, accuracy, cost saving and the like.

Description

Digital filter device
Technical Field
The present invention relates to the field of digital filtering technology, and more particularly, to a digital filtering device.
Background
In some digital signal processing fields, particularly digital systems in the fields of digital audio, video, wireless communication, filters for processing digital signals are often required. With the development of wireless intelligent communication, information diversification, voice, image, automatic control, radar, military, aerospace, medical and intelligent household appliances, and integration technology, the development of wireless communication technology, wireless transmission control household and other technologies, the requirements on the real-time performance and rapidness of digital signal processing are higher and higher, and the existing filter cannot meet the requirements.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide a digital filter device which has the characteristics of high stability, accurate precision, flexible design, convenient implementation and the like in digital signal processing.
To achieve the above object, an embodiment of the present invention provides a digital filtering apparatus including: CIC and FIR filters; the CIC filter includes:
a self-decrementing counter for outputting a count value based on the clock signal;
a first down-sampling signal generating circuit that outputs a first down-sampling signal based on a count value, the first down-sampling signal generating circuit including a first not gate, a first nor gate, a second nor gate, a third nor gate, a fourth nor gate, a fifth nor gate, a first or gate, a second or gate, a first and gate, a second and gate, a third and gate, a fourth and gate, a fifth and gate, and a sixth and gate; the input end of the first NOT gate is used for receiving the count value, and the first input end of the first AND gate is connected with the output end of the first NOT gate; the first input end and the second input end of the first NOR gate are used for receiving the count value, and the first input end of the second AND gate is connected with the output end of the first NOR gate; the first input end, the second input end and the third input end of the second NOR gate are used for receiving the count value, and the first input end of the third AND gate is connected with the output end of the second NOR gate; the first input end, the second input end, the third input end and the fourth input end of the third NOR gate are used for receiving the count value, and the first input end of the fourth NOR gate is connected with the output end of the third NOR gate; the first input end, the second input end, the third input end, the fourth input end and the fifth input end of the fourth NOR gate are used for receiving the count value, and the first input end of the fifth AND gate is connected with the output end of the fourth NOR gate; the first input end, the second input end and the third input end of the first OR gate are used for receiving the count value, the first input end, the second input end and the third input end of the second OR gate are used for receiving the count value, the first input end of the fifth NOR gate is connected with the output end of the first OR gate, the second input end of the fifth NOR gate is connected with the output end of the second OR gate, and the first input end of the sixth OR gate is connected with the output end of the fifth NOR gate; the second input end of the first AND gate, the second input end of the second AND gate, the second input end of the third AND gate, the second input end of the fourth AND gate, the second input end of the fifth AND gate and the second input end of the sixth AND gate are used for receiving the enabling signals; the output end of the first AND gate, the output end of the second AND gate, the output end of the third AND gate, the output end of the fourth AND gate, the output end of the fifth AND gate and the output end of the sixth AND gate are used for outputting a first downsampling signal;
A second down-sampling signal generating circuit that outputs a second down-sampling signal based on a count value, the second down-sampling signal generating circuit including a seventh and gate, an eighth and gate, a ninth and gate, a tenth and gate, an eleventh and gate, a twelfth and gate, a thirteenth and gate, a fourteenth and gate, a fifteenth and gate, a sixteenth and gate, a seventeenth and gate, an eighteenth and gate, a nineteenth and gate, a twentieth and gate, a second not gate, a third not gate, a fourth not gate, a fifth not gate, a sixth not gate, a seventh not gate, an eighth not gate, and a ninth not gate; the third input end of the ninth AND gate is connected with the output end of the second NOT gate, the third input end of the eleventh AND gate is connected with the output end of the third NOT gate, the fourth input end of the thirteenth AND gate is connected with the output end of the fourth NOT gate, the fifth input end of the thirteenth AND gate is connected with the output end of the fifth NOT gate, the first input end of the sixteenth AND gate is connected with the output end of the sixth NOT gate, the first input end of the nineteenth AND gate is connected with the input end of the seventh NOT gate, the second input end of the nineteenth AND gate is connected with the output end of the eighth NOT gate, and the fourth input end of the nineteenth AND gate is connected with the output end of the ninth NOT gate;
The first input end and the second input end of the seventh and gate are used for receiving the count value, the first input end and the second input end of the ninth and gate and the input end of the second not gate are used for receiving the count value, the first input end, the second input end and the fourth input end of the eleventh and gate and the input end of the third not gate are used for receiving the count value, the first input end, the second input end and the third input end of the thirteenth and gate and the input end of the fourth not gate and the input end of the fifth and gate are used for receiving the count value, the first input end, the second input end and the third input end of the fifteenth and gate are used for receiving the count value, the second input end and the third input end of the eighth and gate are used for receiving the count value, and the third input end and the input end of the ninth and the input end of the eighth and the ninth not gate are used for receiving the count value; the first input end of the eighth AND gate is connected with the output end of the seventh AND gate, the first input end of the tenth AND gate is connected with the output end of the ninth AND gate, the first input end of the twelfth AND gate is connected with the output end of the eleventh AND gate, the first input end of the fourteenth AND gate is connected with the output end of the thirteenth AND gate, the first input end of the seventeenth AND gate is connected with the output end of the fifteenth AND gate, the second input end of the seventeenth AND gate is connected with the output end of the sixteenth AND gate, the first input end of the twentieth AND gate is connected with the output end of the eighteenth AND gate, and the second input end of the twentieth AND gate is connected with the output end of the nineteenth AND gate. The second input end of the eighth and gate, the second input end of the tenth and gate, the second input end of the twelfth and gate, the second input end of the fourteenth and gate, the third input end of the seventeenth and gate and the third input end of the twentieth and gate are used for receiving the enabling signal; the output end of the eighth and gate, the output end of the tenth and gate, the output end of the twelfth and gate, the output end of the fourteenth and gate, the output end of the seventeenth and gate and the output end of the twentieth and gate are used for outputting a second down-sampling signal;
The multi-stage cascade filtering module is used for filtering an input signal based on a first downsampling signal to output a filtering signal, and the later stage filtering module is used for filtering the filtering signal output by the earlier stage filtering module again based on the first downsampling signal and a second downsampling signal to output a corresponding filtering signal;
the FIR filter includes:
the third downsampling signal generating circuit comprises N cascaded D flip-flops, wherein N is a natural number which is more than or equal to 2, the first stage D flip-flop is used for processing an input signal based on a clock signal to output tap coefficients, and the later stage D flip-flop is used for reprocessing the tap coefficients output by the former stage D flip-flop based on the clock signal to output corresponding tap coefficients;
m adders for carrying out summation logic operation on tap coefficients output by the two symmetrical D flip-flops to output corresponding logic signals, wherein M is an integer part equal to N/2;
a weighting coefficient generation circuit for outputting a weighting coefficient based on a part of the logic signal;
and a filter circuit for filtering based on the weighting coefficients and the partial tap coefficients to output a filtered signal.
In one or more embodiments of the present invention, the filtering module includes a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, a twenty-first and gate, a twenty-second and gate, a twenty-third and gate, a twenty-fourth and gate, a twenty-fifth and gate, a first shift register, a second shift register, a third or gate, a fourth or gate, and a fifth or gate;
The first input end of the twenty-first AND gate is used for receiving 1' b1 or a first downsampling signal, the second input end of the twenty-first AND gate is used for receiving an input signal or is connected with the Q output end of a previous stage D trigger, the D input end of the first D trigger is connected with the output end of the twenty-first AND gate, the first input end of the twenty-second AND gate is used for receiving the first downsampling signal or a second downsampling signal, the second input end of the second AND gate is connected with the Q output end of the first D trigger, the D input end of the second D trigger is connected with the output end of the twenty-second AND gate, the first input end of the third AND gate is used for receiving the first downsampling signal or the second downsampling signal, the second input end of the third AND gate is connected with the Q output end of the second D trigger, and the D input end of the third D trigger is connected with the output end of the third AND gate;
the first input end of the twenty-fourth AND gate is used for receiving a first down-sampling signal or a second down-sampling signal, the second input end of the twenty-fourth AND gate is used for receiving an input signal or is connected with the Q output end of a D trigger of the previous stage, the D input end of the fourth D trigger is connected with the output end of the twenty-fourth AND gate, the first input end of the twenty-fifth AND gate is used for receiving the first down-sampling signal or the second down-sampling signal, the second input end of the twenty-fifth AND gate is connected with the Q output end of the fourth D trigger, and the D input end of the fifth D trigger is connected with the output end of the twenty-fifth AND gate;
The input end of the first shift register is connected with the Q output end of the fifth D trigger, the first input end of the third OR gate is connected with the Q output end of the fourth D trigger, the second input end of the third OR gate is connected with the Q output end of the fifth D trigger, the third input end of the third OR gate is connected with the output end of the first shift register, the input end of the second shift register is connected with the Q output end of the second D trigger, the first input end of the fourth OR gate is connected with the Q output end of the second D trigger, the second input end of the fourth OR gate is connected with the Q output end of the third D trigger, the third input end of the fourth OR gate is connected with the output end of the second shift register, the first input end of the fifth OR gate is connected with the output end of the third OR gate, the second input end of the fifth OR gate is connected with the output end of the fourth OR gate, and the output end of the fifth OR gate is used for outputting filtering signals.
In one or more embodiments of the present invention, the third downsampling signal generating circuit includes a sixth D flip-flop, a seventh D flip-flop, an eighth D flip-flop, a ninth D flip-flop, a tenth D flip-flop, an eleventh D flip-flop, a twelfth D flip-flop, a thirteenth D flip-flop, a fourteenth D flip-flop, a fifteenth D flip-flop, a sixteenth D flip-flop, a seventeenth D flip-flop, an eighteenth D flip-flop, a nineteenth D flip-flop, and a twentieth D flip-flop that are cascaded with each other.
In one or more embodiments of the present invention, the adder includes a first adder, a second adder, a third adder, a fourth adder, a fifth adder, a sixth adder, and a seventh adder;
the first input end of the first adder is connected with the Q output end of a sixth D trigger, the second input end of the first adder is connected with the Q output end of a twenty-first D trigger, the first input end of the second adder is connected with the Q output end of a seventh D trigger, the second input end of the second adder is connected with the Q output end of a nineteenth D trigger, the first input end of the third adder is connected with the Q output end of an eighth D trigger, the second input end of the third adder is connected with the Q output end of an eighteenth D trigger, the first input end of the fourth adder is connected with the Q output end of a ninth D trigger, the second input end of the fourth adder is connected with the Q output end of a seventeenth D trigger, the first input end of the fifth adder is connected with the Q output end of a sixteenth D trigger, the second input end of the fifth adder is connected with the Q output end of the seventeenth D trigger, and the Q output end of the seventeenth D trigger is connected with the Q output end of the seventeenth D trigger;
The output end of the first adder, the output end of the second adder, the output end of the third adder, the output end of the fourth adder, the output end of the fifth adder, the output end of the sixth adder and the output end of the seventh adder are used for outputting logic signals.
In one or more embodiments of the present invention, the weighting factor generating circuit includes a third shift register, a fourth shift register, a fifth shift register, a sixth shift register, a seventh shift register, an eighth shift register, a ninth shift register, a first complement module, a second complement module, a third complement module, an eighth adder, a ninth adder, a tenth adder, and an eleventh adder;
the input end of the third shift register is connected with the output end of the second adder, the input end of the fourth shift register is connected with the output end of the third adder, the first input end of the eighth adder is connected with the output end of the fourth shift register, the second input end of the eighth adder is connected with the output end of the third adder, the input end of the first complementary code taking module is connected with the output end of the eighth adder, the input end of the fifth shift register is connected with the output end of the fourth adder, the first input end of the ninth adder is connected with the output end of the fifth shift register, the second input end of the ninth adder is connected with the output end of the fourth adder, the input end of the second complementary code taking module is connected with the output end of the ninth adder, the input end of the sixth shift register is connected with the output end of the sixth adder, the input end of the seventh complementary code taking module is connected with the output end of the seventh adder, the input end of the seventh shift register is connected with the output end of the eighth adder;
The output end of the third shift register, the output end of the first complement module, the output end of the second complement module, the output end of the tenth adder and the output end of the eleventh adder are used for outputting the weighting coefficient.
In one or more embodiments of the present invention, the filter circuit includes a tenth shift register, an eleventh shift register, a twelfth adder, a thirteenth adder, a fourteenth adder, and a fifteenth adder;
the input end of the tenth shift register, the input end of the eleventh shift register and the input end of the twelfth shift register are connected with the Q output end of the thirteenth D trigger, the first input end of the twelfth adder is connected with the output end of the tenth shift register, the second input end of the twelfth adder is connected with the output end of the eleventh shift register, and the third input end of the twelfth adder is connected with the output end of the twelfth shift register;
the first input end of the thirteenth adder is connected with the output end of the first adder, the second input end of the thirteenth adder is connected with the output end of the first complementary code taking module, the third input end of the thirteenth adder is connected with the output end of the fifth adder, the fourth input end of the thirteenth adder is connected with the output end of the eleventh adder, the first input end of the fourteenth adder is connected with the output end of the third shift register, the second input end of the fourteenth adder is connected with the output end of the second complementary code taking module, the third input end of the fourteenth adder is connected with the output end of the tenth adder, the fourth input end of the fourteenth adder is connected with the output end of the twelfth adder, the first input end of the fifteenth adder is connected with the output end of the thirteenth adder, the second input end of the fifteenth adder is connected with the output end of the fourteenth adder, and the output end of the fifteenth adder is used for outputting filtering signals.
In one or more embodiments of the invention, the self-decrementing counter is used for cycle counting from 7-bit self-decrementing to 0.
The invention also discloses a chip comprising the digital filter device.
Compared with the prior art, the digital filter device provided by the embodiment of the invention can be used as a digital filter circuit with the filtering function characteristic for digital signals, and can be used for carrying out selective transmission of specific frequencies of signal processing and eliminating frequency aliasing and interference of signals.
And performing digital down-conversion decimation filter control according to the digital filter device to complete the control of sampling, correlation, convolution, self-adaptive filtering and the like on the digital signal.
The digital filter device according to the embodiment of the invention can be realized as digital hardware in a digital signal processing algorithm circuit; the digital filter device is provided with an IP module which can be configured to realize digital signal processing of a digital decimation filtering downsampling frequency conversion algorithm and data processing of a CIC digital filter algorithm and a signed FIR digital filter algorithm; the integrated circuit can be integrated in a communication or semiconductor integrated circuit, and has the advantages of low power consumption, strong universality, small occupied area, instantaneity, accuracy, cost saving and the like.
According to the digital filtering device provided by the embodiment of the invention, the digital down-conversion decimation filter is realized through the CIC filter, and according to the configured digital signal processing, the frequency filtering of the digital signal and the frequency spectrum aliasing and interference phenomenon of the audio and video signal are eliminated through the CIC filter; the method can be widely applied to signal processing such as convolution, correlation, self-adaptive filtering, orthogonal interpolation and the like in various digital signal processing systems through the FIR filter.
According to the digital filter device provided by the embodiment of the invention, different filtering characteristics are applied by controlling different filtering transmission structures, the relative proportion of frequency components contained in signals can be changed or certain frequency components can be filtered by designing a digital hardware filter, digital down-conversion extraction is achieved by different digital filter algorithms, the filtering characteristics are selected for the frequencies, and further, the characteristics of low pass, high pass, band elimination, all-pass filters and the like are controlled to be realized by controlling different frequency domain characteristic transmission, the gain characteristics of specific coefficients can be achieved, and the digital filter device has strict linear phase characteristics and has the requirements of high stability, high precision, high flexibility, low cost, instantaneity, accuracy and the like.
Drawings
Fig. 1 is a block diagram of a CIC filter according to the invention.
Fig. 2 is a block diagram of the structure of the self-decrementing counter according to the present invention.
Fig. 3 is a circuit configuration diagram of a first down-sampling signal generating circuit according to the present invention.
Fig. 4 is a circuit configuration diagram of a second down-sampling signal generating circuit according to the present invention.
Fig. 5 is a block diagram of a multi-stage cascaded filter module according to the present invention.
Fig. 6 is a schematic diagram of the structure of a filtering module according to the present invention.
Fig. 7 is a circuit configuration diagram of a third down-sampling signal generating circuit according to the present invention.
Fig. 8 is a schematic diagram of the structure of seven adders according to the present invention.
Fig. 9 is a schematic diagram of the structure of the weight coefficient generation circuit according to the present invention.
Fig. 10 is a schematic diagram of a filter circuit according to the present invention.
Detailed Description
Specific embodiments of the invention will be described in detail below with reference to the drawings, but it should be understood that the scope of the invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations thereof such as "comprises" or "comprising", etc. will be understood to include the stated element or component without excluding other elements or components.
The term "coupled" or "connected" in this specification includes both direct and indirect connections. An indirect connection is a connection made through an intermediary, such as an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connections may also include connections through other active or passive devices, such as through circuits or components such as switches, follower circuits, and the like, that accomplish the same or similar functional objectives. Furthermore, in the present invention, terms such as "first," "second," and the like, are used primarily to distinguish one technical feature from another, and do not necessarily require or imply a certain actual relationship, number or order between the technical features.
A digital filtering apparatus, comprising: CIC and FIR filters.
The CIC filter is antialiased before decimating. In the up-down conversion of communication digital signals, the up-sampling and down-sampling design of the digital signals is often used, and the CIC cascade integration comb filter is obtained by adopting a cascade structure of an integrator and a comb filter. Since the filter coefficient is 1, no coefficient is required to be stored, no multiplier is required, and the overall structure of the filter is not changed when the decimation/interpolation factor is set. The CIC filter includes two structures: the integral structure and the comb structure, each stage of CIC filter is composed of an integrator and a comb filter, the integrator is an accumulator, overflow condition exists in the accumulation process, reasonable calculation bit width is needed, the accumulator bit width of each stage of CIC filter is the number of input bits and a calculation formula used for representing the extraction multiple and cascade number of the prototype filter of the tap after processing. 7 identical CIC cascade comb filters, and the realized digital filters finally realize the following calculation formulas for input data:
TF 1234567 =(1-z -128 /1-z -1 ) 3
Specifically, the first stage CIC filter implements the following algorithm for the input data:
TF 1 =(1+3z -2 )+z -1 (3+z -2 )=1+3z -1 +3z -2 +z -3 =(1+z -1 ) 3
the second-stage CIC filter realizes the input data through downsampling:
TF 2 =(1+3z -4 )+z -2 (3+z -4 )=(1+z -2 ) 3
since the output of the first-stage CIC filter is connected to the input of the second-stage CIC filter, the result of the calculation formula for the change of input data is realized after the output of the first-stage CIC filter passes through the second-stage CIC filter circuit:
TF 12 =(1+z -1 ) 3 (1+z -2 ) 3 =(1+z -1 +z -2 +z -3 ) 3 =(1-z -4 /1-z -1 ) 3
the third-stage CIC filter is realized by downsampling the input data:
TF 3 =(1+3z -8 )+z -4 (3+z -8 )=(1+z -4 ) 3
and the same reason is that the output of the CIC filter of the second stage and the input of the CIC filter of the third stage are cascaded, and after the CIC filter of the third stage is passed through a circuit of the CIC filter, a calculation formula of input data is realized:
TF 123 =(1-z -4 /1-z -1 ) 3 (1+z -4 ) 3 =(1-z -8 /1-z -1 ) 3
similarly, the calculation formula for the input data can be deduced as follows after the input data passes through the seventh-stage CIC filter circuit:
TF 1234567 =(1-z -128 /1-z -1 ) 3
the CIC filter includes: the self-down counter, the first down sampling signal generating circuit, the second down sampling signal generating circuit and the multi-stage cascade filter module.
As shown in fig. 2, the self-decrementing counter is configured to output a count value [6:0] based on the clock signal clk; the self-down counter is used for performing cycle counting from 7-bit self-down counting to 0, and performing filter module extraction control of different stages according to the counting value to realize downsampling of filter modules of different stages.
The first downsampling signal generating circuit outputs first downsampling signals count 1-6 based on a count value [6:0 ].
As shown in fig. 3, the first downsampling signal generating circuit includes a first nor gate, a second nor gate, a third nor gate, a fourth nor gate, a fifth nor gate, a first or gate, a second or gate, a first and gate, a second and gate, a third and gate, a fourth and gate, a fifth and gate, and a sixth and gate.
The input end of the first NOT gate is used for receiving the count value [0], the first input end of the first AND gate is connected with the output end of the first NOT gate, the second input end of the first AND gate is used for receiving the enable signal en, and the output end of the first AND gate is used for outputting a first downsampling signal count 1.
The first input end of the first nor gate is used for receiving the count value [0], the second input end of the first nor gate is used for receiving the count value [1], the first input end of the second nor gate is connected with the output end of the first nor gate, the second input end of the second nor gate is used for receiving the enable signal en, and the output end of the second nor gate is used for outputting the first downsampling signal count 2.
The first input end of the second nor gate is used for receiving the count value [0], the second input end of the second nor gate is used for receiving the count value [1], the third input end of the second nor gate is used for receiving the count value [2], the first input end of the third and gate is connected with the output end of the second nor gate, the second input end of the third and gate is used for receiving the enable signal en, and the output end of the third and gate is used for outputting the first downsampling signal count 3.
The first input end of the third nor gate is used for receiving the count value [0], the second input end of the third nor gate is used for receiving the count value [1], the third input end of the third nor gate is used for receiving the count value [2], the fourth input end of the third nor gate is used for receiving the count value [3], the first input end of the fourth and gate is connected with the output end of the third nor gate, the second input end of the fourth and gate is used for receiving the enable signal en, and the output end of the fourth and gate is used for outputting the first downsampling signal count 4.
The first input end of the fourth nor gate is used for receiving the count value [0], the second input end of the fourth nor gate is used for receiving the count value [1], the third input end of the fourth nor gate is used for receiving the count value [2], the fourth input end of the fourth nor gate is used for receiving the count value [3], the fifth input end of the fourth nor gate is used for receiving the count value [4], the first input end of the fifth and gate is connected with the output end of the fourth nor gate, the second input end of the fifth and gate is used for receiving the enable signal en, and the output end of the fifth and gate is used for outputting the first downsampling signal count 5.
The first input end of the first OR gate is used for receiving the count value [0], the second input end of the first OR gate is used for receiving the count value [1], the third input end of the first OR gate is used for receiving the count value [2], the first input end of the second OR gate is used for receiving the count value [3], the second input end of the second OR gate is used for receiving the count value [4], the third input end of the second OR gate is used for receiving the count value [5], the first input end of the fifth NOR gate is connected with the output end of the first OR gate, the second input end of the fifth NOR gate is connected with the output end of the second OR gate, the first input end of the sixth AND gate is connected with the output end of the fifth NOR gate, the second input end of the sixth AND gate is used for receiving the enable signal en, and the output end of the sixth AND gate is used for outputting the first downsampling signal count 6.
The second down-sampling signal generating circuit outputs second down-sampling signals coup 1-6 based on the count value [6:0 ].
As shown in fig. 4, the second down-sampling signal generating circuit includes a seventh and gate, an eighth and gate, a ninth and gate, a tenth and gate, an eleventh and gate, a twelfth and gate, a thirteenth and gate, a fourteenth and gate, a fifteenth and gate, a sixteenth and gate, a seventeenth and gate, an eighteenth and gate, a nineteenth and gate, a twentieth and gate, a second not gate, a third not gate, a fourth not gate, a fifth not gate, a sixth not gate, a seventh not gate, an eighth not gate, and a ninth not gate.
Specifically, the third input end of the ninth and gate is connected to the output end of the second not gate, the third input end of the eleventh and gate is connected to the output end of the third not gate, the fourth input end of the thirteenth and gate is connected to the output end of the fourth not gate, the fifth input end of the thirteenth and gate is connected to the output end of the fifth not gate, the first input end of the sixteenth and gate is connected to the output end of the sixth not gate, the first input end of the nineteenth and gate is connected to the input end of the seventh not gate, the second input end of the nineteenth and gate is connected to the output end of the eighth not gate, and the fourth input end of the nineteenth and gate is connected to the output end of the ninth not gate.
The first input end and the second input end of the seventh AND gate are used for receiving the count value [6:0], the first input end of the eighth AND gate is connected with the output end of the seventh AND gate, the second input end of the eighth AND gate is used for receiving the enable signal en, and the output end of the eighth AND gate is used for outputting the second downsampling signal coup1.
The first input end and the second input end of the ninth AND gate and the input end of the second NOT gate are used for receiving the count value [6:0], the first input end of the tenth AND gate is connected with the output end of the ninth AND gate, the second input end of the tenth AND gate is used for receiving the enable signal en, and the output end of the tenth AND gate is used for outputting the second downsampling signal coupling 2.
The first input end, the second input end, the fourth input end and the input end of the third NOT gate are used for receiving the count value [6:0], the first input end of the twelfth AND gate is connected with the output end of the eleventh AND gate, the second input end of the twelfth AND gate is used for receiving the enable signal en, and the output end of the twelfth AND gate is used for outputting a second downsampling signal coup3.
The first input end, the second input end, the third input end, the fourth input end and the fourth input end of the thirteenth AND gate, the input end of the fifth AND gate are used for receiving the count value [6:0], the first input end of the fourteenth AND gate is connected with the output end of the thirteenth AND gate, the second input end of the fourteenth AND gate is used for receiving the enable signal en, and the output end of the fourteenth AND gate is used for outputting a second downsampling signal coupling 4.
The first input end, the second input end and the third input end of the fifteenth AND gate are used for receiving a count value [6:0], the second input end and the third input end of the sixteenth AND gate and the input end of the sixth NOT gate are used for receiving the count value [6:0], the first input end of the seventeenth AND gate is connected with the output end of the fifteenth AND gate, the second input end of the seventeenth AND gate is connected with the output end of the sixteenth AND gate, the third input end of the seventeenth AND gate is used for receiving an enable signal en, and the output end of the seventeenth AND gate is used for outputting a second downsampling signal coup5.
The first input end, the second input end and the third input end of the eighteenth AND gate are used for receiving a count value [6:0], the third input end of the nineteenth AND gate, the input end of the seventh NOT gate, the input end of the eighth NOT gate and the input end of the ninth NOT gate are used for receiving the count value [6:0], the first input end of the twentieth AND gate is connected with the output end of the eighteenth AND gate, the second input end of the twentieth AND gate is connected with the output end of the nineteenth AND gate, the third input end of the twentieth AND gate is used for receiving an enable signal en, and the output end of the twentieth AND gate is used for outputting a second downsampling signal coup6.
The first stage filtering module is used for filtering the input signal d_in based on the first downsampled signals count 1-6 to output a filtered signal do1[3:0]. The next stage filtering module is used for filtering the filtering signal output by the previous stage filtering module again based on the first downsampling signals count 1-6 and the second downsampling signals couple 1-6 to output a corresponding filtering signal. The downsampling signals of the filtering modules with different stages are controlled to be adopted and filtered and integrated to be accumulated through the first downsampling signals count 1-6 and the second downsampling signals coup 1-6.
As shown in fig. 5, the filter modules are provided with seven in cascade. As shown in fig. 6, each filtering module includes a first D flip-flop D1, a second D flip-flop D2, a third D flip-flop D3, a fourth D flip-flop D4, a fifth D flip-flop D5, a twenty-first and gate, a twenty-second and gate, a twenty-third and gate, a twenty-fourth and gate, a twenty-fifth and gate, a first shift register, a second shift register, a third or gate, a fourth or gate, and a fifth or gate.
As shown in fig. 6 and 5, if the filtering module is a first stage filtering module, the first input end of the twentieth and gate is used for receiving the 1' b1, the second input end of the twentieth and gate is used for receiving the input signal d_in, and the D input end of the first D flip-flop D1 is connected to the output end of the twentieth and gate.
The first input end of the twenty-second AND gate is used for receiving the first downsampling signal count 1, the second input end of the twenty-second AND gate is connected with the Q output end of the first D trigger D1, and the D input end of the second D trigger D2 is connected with the output end of the twenty-second AND gate.
The first input end of the twenty-third AND gate is used for receiving the first downsampling signal count 1, the second input end of the twenty-third AND gate is connected with the Q output end of the second D trigger D2, and the D input end of the third D trigger D3 is connected with the output end of the twenty-third AND gate.
The first input end of the twenty-fourth AND gate is used for receiving the first downsampling signal count 1, the second input end of the twenty-fourth AND gate is used for receiving the input signal d_in, the D input end of the fourth D trigger D4 is connected with the output end of the twenty-fourth AND gate, the first input end of the twenty-fifth AND gate is used for receiving the first downsampling signal count 1, the second input end of the twenty-fifth AND gate is connected with the Q output end of the fourth D trigger D4, and the D input end of the fifth D trigger D5 is connected with the output end of the twenty-fifth AND gate.
The input end of the first shift register is connected with the Q output end of the fifth D trigger D5, and the first shift register is used for shifting the signal x11_tp output by the Q output end of the fifth D trigger D5 by 1 bit to the right. The first input end of the third OR gate is connected with the Q output end of the fourth D trigger D4, the second input end of the third OR gate is connected with the Q output end of the fifth D trigger D5, and the third input end of the third OR gate is connected with the output end of the first shift register.
The input end of the second shift register is connected with the Q output end of the second D trigger D2, and the second shift register is used for shifting the signal D2 output by the Q output end of the second D trigger D2 by 1 bit to the right. The first input end of the fourth OR gate is connected with the Q output end of the second D trigger D2, the second input end of the fourth OR gate is connected with the Q output end of the third D trigger D3, and the third input end of the fourth OR gate is connected with the output end of the second shift register.
The first input end of the fifth or gate is connected with the output end of the third or gate, the second input end of the fifth or gate is connected with the output end of the fourth or gate, and the output end of the fifth or gate is used for outputting a filtering signal dout.
If the filtering module is a second-stage filtering module, the first input end of the corresponding twenty-first and gate is used for receiving the first downsampling signal count 1, and the second input end of the twenty-first and gate is connected with the output end of the first-stage filtering module. The first input terminal of the twenty-second and gate, the first input terminal of the twenty-fourth and gate, the first input terminal of the twenty-fifth and gate, and the first input terminal of the twenty-third and gate are configured to receive the second down-sampling signal coupling 1. If the filtering modules are a third stage, a fourth stage, a fifth stage, a sixth stage and a seventh stage, the first downsampling signals count 2-6 and the second downsampling signals count 2-6 are sequentially received by analogy.
As shown in FIG. 6, the input/output bit width is defined differently by each stage of the calculation anti-overflow control, and the down-sampling signal interfaces of the AND gates are different in connection signals, so that the single internal logic circuit has the same structural principle. In fig. 6, the control is mainly performed by a D flip-flop of the downsampling control, and the shift control of the shift register is performed according to the downsampling result of the D flip-flop, so as to realize the multiple coefficient and the corresponding addition and realize the corresponding weight coefficient control.
CIC filters can cause a sag in the passband, and the more cascaded the stages, the more serious the problem. Often resulting in passband narrowing and transition band widening, there is a need to concatenate an additional compensation filter after the CIC filter, for which a non-recursive FIR filter needs to be designed to compensate. The FIR filter converts one set of input sequences into another set of output data sequences, thereby effecting a change in signal properties in the time or frequency domain. The principle of operation of a FIR filter is to multiply a series of the latest n data samples by a series of constants (called tap coefficients) and to sum the elements of the resulting array. By varying the weighting (values) of the coefficients and the number of filter taps, the FIR filter can achieve virtually any desired frequency response characteristic. In other embodiments, the CIC filter and FIR filter may be used separately, i.e., both may be used in different two systems.
In this embodiment, correction operation is performed on the signal do7[21:0] output by the multi-stage cascade filtering module, and 14 bits in the signal do7[21:0] are taken as the signal do7[20:7] and input to the input end of the FIR filter; if do7[21] is 1, the corresponding value is 14' h3fff; if the signal do7[20:7] is 14'h3fff, the corresponding value is 14' h3fff, otherwise the value (do 7[20:7] +do 7[6 ]).
The FIR filter includes: the third down-sampling signal generating circuit, M adders and a filter circuit. In the present embodiment, the third down-sampling signal generating circuit is provided with 14 sets corresponding to 14-bit data.
Each third downsampling signal generating circuit comprises N cascaded D flip-flops, N is a natural number which is greater than or equal to 2, the first stage D flip-flop is used for processing an input signal datain based on a clock signal clk to output tap coefficients, and the later stage D flip-flop is used for reprocessing the tap coefficients output by the previous stage D flip-flop based on the clock signal clk to output corresponding tap coefficients.
As shown in fig. 7, in the present embodiment, N is 15, and specifically, the third down-sampling signal generating circuit includes a sixth D-flip-flop D6, a seventh D-flip-flop D7, an eighth D-flip-flop D8, a ninth D-flip-flop D9, a tenth D-flip-flop D10, an eleventh D-flip-flop D11, a twelfth D-flip-flop D12, a thirteenth D-flip-flop D13, a fourteenth D-flip-flop D14, a fifteenth D-flip-flop D15, a sixteenth D-flip-flop D16, a seventeenth D-flip-flop D17, an eighteenth D-flip-flop D18, a nineteenth D-flip-flop D19, and a twentieth D-flip-flop D20, which are cascaded to each other.
The D input of the sixth D flip-flop D6 is for receiving the input signal datain [13:0], in the present embodiment, the input signal datain [13: and 0 is the signal do7[20:7]. The Q output of the sixth D flip-flop D6 is for outputting tap coefficients z_0[13:0], a seventh D flip-flop D7 is used to output tap coefficients z_1[13:0], the eighth D flip-flop D8 is for outputting tap coefficients z_2[13:0], the ninth D flip-flop D9 is for outputting tap coefficients z_3[13:0], the tenth D flip-flop D10 is for outputting tap coefficients z_4[13:0], the eleventh D flip-flop D11 is for outputting tap coefficients z_5[13:0], the twelfth D flip-flop D12 is for outputting tap coefficients z_6[13:0], thirteenth D flip-flop D13 is for outputting tap coefficient z_7[13:0], the fourteenth D flip-flop D14 is for outputting tap coefficients z_8[13:0], the fifteenth D flip-flop D15 is for outputting tap coefficients z_9[13:0], the sixteenth D flip-flop D16 is for outputting tap coefficients z_10[13:0], seventeenth D flip-flop D17 is for outputting tap coefficient z_11[13:0], the eighteenth D flip-flop D18 is for outputting tap coefficients z_12[13:0], the nineteenth D flip-flop D19 is for outputting tap coefficients z_13[13:0], the twentieth D flip-flop D20 is used to output tap coefficients z_14[13:0].
The M adders are used for carrying out summation logic operation on tap coefficients output by the two symmetrical D flip-flops so as to output corresponding logic signals, and M is an integer part equal to N/2.
As shown in fig. 8, M is 7 in the present embodiment, and specifically, the adders include a first adder, a second adder, a third adder, a fourth adder, a fifth adder, a sixth adder, and a seventh adder.
A first input of the first adder is connected to the Q output of the sixth D flip-flop D6 to receive the tap coefficient z_0[13:0], a second input of the first adder being connected to the Q output of the twentieth D flip-flop D20 for receiving the tap coefficient z_14[13:0], the output of the first adder is used for outputting a logic signal z_0_14_sum [14:0].
The first input of the second adder is connected to the Q output of the seventh D flip-flop D7 to receive the tap coefficient z_1[13:0], a second input of the second adder being connected to the Q output of the nineteenth D flip-flop D19 for receiving the tap coefficient z_13[13:0], the output of the second adder is used for outputting a logic signal z_1_13_sum [14:0].
A first input of the third adder is connected to the Q output of the eighth D flip-flop D8 to receive the tap coefficient z_2[13:0], a second input of the third adder being connected to the Q output of the eighteenth D flip-flop for receiving the tap coefficient z_12[13:0], the output terminal of the third adder is used for outputting a logic signal z_2_12_sum [14:0].
A first input of the fourth adder is connected to the Q output of the ninth D flip-flop D9 for receiving tap coefficient z_3[13:0], a second input of the fourth adder being connected to the Q output of the seventeenth D flip-flop D17 for receiving the tap coefficient z_11[13:0], the output terminal of the fourth adder is used for outputting a logic signal z_3_11_sum [14:0].
A first input of the fifth adder is connected to the Q output of the tenth D flip-flop D10 for receiving the tap coefficient z_4[13:0], a second input of the fifth adder being connected to the Q output of the sixteenth D flip-flop D16 for receiving the tap coefficient z_10[13:0], the output terminal of the fifth adder is used for outputting a logic signal z_4_10_sum [14:0].
A first input of the sixth adder is connected to the Q output of the eleventh D flip-flop D11 for receiving the tap coefficient z_5[13:0], a second input of the sixth adder being connected to the Q output of the fifteenth D flip-flop D15 for receiving the tap coefficient z_9[13:0], the output of the sixth adder is used for outputting a logic signal z_5_9_sum [14:0].
A first input of the seventh adder is connected to the Q output of the twelfth D flip-flop D12 for receiving the tap coefficient z_6[13:0], a second input of the seventh adder being connected to the Q output of the fourteenth D flip-flop D14 for receiving tap coefficients z_8[13:0], the output of the seventh adder is for outputting a logic signal z_6_8_sum [14:0].
The weighting coefficient generation circuit is used for outputting weighting coefficients based on part of the logic signals.
As shown in fig. 9, the weighting coefficient generation circuit includes a third shift register, a fourth shift register, a fifth shift register, a sixth shift register, a seventh shift register, an eighth shift register, a ninth shift register, a first complement module, a second complement module, a third complement module, an eighth adder, a ninth adder, a tenth adder, and an eleventh adder.
An input of the third shift register is coupled to an output of the second adder to receive the logic signal z_1_13_sum [14:0], the third shift register is used to shift the logic signal z_1_13_sum [14:0] left shift by 1 bit, and the output end of the third shift register is used for outputting a weighting coefficient x2_z113s [15:0].
An input of the fourth shift register is connected to an output of the third adder to receive the logic signal z_2_12_sum [14:0], the fourth shift register is used to shift the logic signal z_2_12_sum [14:0] left shift by 2 bits, a first input of an eighth adder being connected to the output of the fourth shift register, a second input of the eighth adder being connected to the output of the third adder for receiving the logic signal z_2_12_sum [14:0], the input end of the first complementary code taking module is connected with the output end of the eighth adder, and the output end of the first complementary code taking module is used for outputting a weighting coefficient nx5_z212s [17:0].
An input of the fifth shift register is connected to an output of the fourth adder to receive the logic signal z_3_11_sum [14:0], the fifth shift register is used for driving the logic signal z_3_11_sum [14:0] is shifted left by 3 bits, a first input end of a ninth adder is connected with an output end of a fifth shift register, a second input end of the ninth adder is connected with an output end of a fourth adder, an input end of a second complementary code taking module is connected with an output end of the ninth adder, and an output end of the second complementary code taking module is used for outputting a weighting coefficient nx9_z313s [18:0].
An input of the sixth shift register is coupled to an output of the sixth adder to receive the logic signal z_5_9_sum [14:0], the sixth shift register is used to shift the logic signal z_5_9_sum [14:0] by 5 bits left, the input of the seventh shift register being connected to the output of the sixth adder to receive the logic signal z_5_9_sum [14:0] is shifted 1 bit to the left, the input end of the third code taking and compensating module is connected with the output end of the seventh shift register, the first input end of the tenth adder is connected with the output end of the sixth shift register, the second input end of the tenth adder is connected with the output end of the third code taking and compensating module, and the output end of the tenth adder is used for outputting a weighting coefficient x30_z59s [19:0].
The input of the eighth shift register and the input of the ninth shift register are connected to the output of the seventh adder to receive the logic signal z_6_8_sum [14:0], the eighth shift register is used to shift the logic signal z_6_8_sum [14:0] left shift by 6 bits, the ninth shift register is used for left shift of logic signals by 1 bit, the first input end of the eleventh adder is connected with the output end of the eighth shift register, the second input end of the eleventh adder is connected with the output end of the ninth shift register, and the output end of the eleventh adder is used for outputting a weighting coefficient x66_z68s [21:0].
The filter circuit is configured to filter based on the weighting coefficients and the partial tap coefficients to output a filtered signal.
As shown in fig. 10, the filter circuit includes a tenth shift register, an eleventh shift register, a twelfth adder, a thirteenth adder, a fourteenth adder, and a fifteenth adder.
The input of the tenth shift register, the input of the eleventh shift register, the input of the twelfth shift register are connected to the Q output of the thirteenth D flip-flop D13 to receive the tap coefficient z_713: 0], the first input of the twelfth adder being connected to the output of a tenth shift register for adding tap coefficients z_7[13:0] by 6 bits left, the second input of the twelfth adder being connected to the output of an eleventh shift register for shifting the tap coefficient z_713: 0] by 4 bits left, the third input of the twelfth adder being connected to the output of the twelfth shift register for shifting the tap coefficient z_7[13:0] left-shifted by 1 bit, the output of the twelfth adder being for outputting the signal x82_z7[20:0].
A first input of the thirteenth adder is connected to the output of the first adder for receiving the logic signal z_0_14_sum [14:0] and a second input of the thirteenth adder is connected to the output of the first complementary module for receiving the weighting coefficients nx5_z212s [17:0], the third input of the thirteenth adder being connected to the output of the fifth adder for receiving the logic signal z_4_10_sum [14:0], the fourth input of the thirteenth adder being connected to the output of the eleventh adder for receiving the weighting coefficients x66_z68s [15:0].
A first input of the fourteenth adder is coupled to the output of the third shift register for receiving the weighting factor x2_z113s [15:0], a second input of the fourteenth adder being coupled to an output of the second complementary module for receiving the weighting coefficients nx9_z313s [18:0], a third input of the fourteenth adder being connected to an output of the tenth adder for receiving the weighting coefficients x30_z59s [19:0], a fourth input of the fourteenth adder being connected to an output of the twelfth adder for receiving the output signal x82_z7[20 ] of the twelfth adder: 0], a first input end of the fifteenth adder is connected with an output end of the thirteenth adder, a second input end of the fifteenth adder is connected with an output end of the fourteenth adder, and the output end of the fifteenth adder is used for outputting a filtering signal Y (xn) [21:0].
Fig. 7-10 jointly implement a direct FIR filter, and according to formula weighting coefficients, the corresponding addition structure can be modified to implement FIR filter formula structures with different weighting coefficients, and fig. 7 mainly illustrates implementation of different downsampling coefficients through a D flip-flop. Fig. 8-10 show that the FIR filter for performing symbol number performs sampling complement calculation such as some calculation subtraction by the complement taking module, in addition, the extended symbol bits with symbol number are required to be weighted according to the calculated extended bit width, the weighting of different coefficients is also required to be realized by jointly controlling a shift register and an adder, the result realizes direct FIR digital filter control, and the result is shifted again according to the result, so that the result divided by the weighting coefficient can be realized, and the control logic principles of other weighting coefficients are the same.
The invention also discloses a chip comprising the digital filter device.
The foregoing descriptions of specific exemplary embodiments of the present invention are presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application to thereby enable one skilled in the art to make and utilize the invention in various exemplary embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims (8)

1. A digital filtering apparatus, comprising: CIC and FIR filters; the CIC filter includes:
a self-decrementing counter for outputting a count value based on the clock signal;
a first down-sampling signal generating circuit that outputs a first down-sampling signal based on a count value, the first down-sampling signal generating circuit including a first not gate, a first nor gate, a second nor gate, a third nor gate, a fourth nor gate, a fifth nor gate, a first or gate, a second or gate, a first and gate, a second and gate, a third and gate, a fourth and gate, a fifth and gate, and a sixth and gate; the input end of the first NOT gate is used for receiving the count value, and the first input end of the first AND gate is connected with the output end of the first NOT gate; the first input end and the second input end of the first NOR gate are used for receiving the count value, and the first input end of the second AND gate is connected with the output end of the first NOR gate; the first input end, the second input end and the third input end of the second NOR gate are used for receiving the count value, and the first input end of the third AND gate is connected with the output end of the second NOR gate; the first input end, the second input end, the third input end and the fourth input end of the third NOR gate are used for receiving the count value, and the first input end of the fourth NOR gate is connected with the output end of the third NOR gate; the first input end, the second input end, the third input end, the fourth input end and the fifth input end of the fourth NOR gate are used for receiving the count value, and the first input end of the fifth AND gate is connected with the output end of the fourth NOR gate; the first input end, the second input end and the third input end of the first OR gate are used for receiving the count value, the first input end, the second input end and the third input end of the second OR gate are used for receiving the count value, the first input end of the fifth NOR gate is connected with the output end of the first OR gate, the second input end of the fifth NOR gate is connected with the output end of the second OR gate, and the first input end of the sixth OR gate is connected with the output end of the fifth NOR gate; the second input end of the first AND gate, the second input end of the second AND gate, the second input end of the third AND gate, the second input end of the fourth AND gate, the second input end of the fifth AND gate and the second input end of the sixth AND gate are used for receiving the enabling signals; the output end of the first AND gate, the output end of the second AND gate, the output end of the third AND gate, the output end of the fourth AND gate, the output end of the fifth AND gate and the output end of the sixth AND gate are used for outputting a first downsampling signal;
A second down-sampling signal generating circuit that outputs a second down-sampling signal based on a count value, the second down-sampling signal generating circuit including a seventh and gate, an eighth and gate, a ninth and gate, a tenth and gate, an eleventh and gate, a twelfth and gate, a thirteenth and gate, a fourteenth and gate, a fifteenth and gate, a sixteenth and gate, a seventeenth and gate, an eighteenth and gate, a nineteenth and gate, a twentieth and gate, a second not gate, a third not gate, a fourth not gate, a fifth not gate, a sixth not gate, a seventh not gate, an eighth not gate, and a ninth not gate; the third input end of the ninth AND gate is connected with the output end of the second NOT gate, the third input end of the eleventh AND gate is connected with the output end of the third NOT gate, the fourth input end of the thirteenth AND gate is connected with the output end of the fourth NOT gate, the fifth input end of the thirteenth AND gate is connected with the output end of the fifth NOT gate, the first input end of the sixteenth AND gate is connected with the output end of the sixth NOT gate, the first input end of the nineteenth AND gate is connected with the input end of the seventh NOT gate, the second input end of the nineteenth AND gate is connected with the output end of the eighth NOT gate, and the fourth input end of the nineteenth AND gate is connected with the output end of the ninth NOT gate;
The first input end and the second input end of the seventh and gate are used for receiving the count value, the first input end and the second input end of the ninth and gate and the input end of the second not gate are used for receiving the count value, the first input end, the second input end and the fourth input end of the eleventh and gate and the input end of the third not gate are used for receiving the count value, the first input end, the second input end and the third input end of the thirteenth and gate and the input end of the fourth not gate and the input end of the fifth and gate are used for receiving the count value, the first input end, the second input end and the third input end of the fifteenth and gate are used for receiving the count value, the second input end and the third input end of the eighth and gate are used for receiving the count value, and the third input end and the input end of the ninth and the input end of the eighth and the ninth not gate are used for receiving the count value; the first input end of the eighth AND gate is connected with the output end of the seventh AND gate, the first input end of the tenth AND gate is connected with the output end of the ninth AND gate, the first input end of the twelfth AND gate is connected with the output end of the eleventh AND gate, the first input end of the fourteenth AND gate is connected with the output end of the thirteenth AND gate, the first input end of the seventeenth AND gate is connected with the output end of the fifteenth AND gate, the second input end of the seventeenth AND gate is connected with the output end of the sixteenth AND gate, the first input end of the twentieth AND gate is connected with the output end of the eighteenth AND gate, and the second input end of the twentieth AND gate is connected with the output end of the nineteenth AND gate. The second input end of the eighth and gate, the second input end of the tenth and gate, the second input end of the twelfth and gate, the second input end of the fourteenth and gate, the third input end of the seventeenth and gate and the third input end of the twentieth and gate are used for receiving the enabling signal; the output end of the eighth and gate, the output end of the tenth and gate, the output end of the twelfth and gate, the output end of the fourteenth and gate, the output end of the seventeenth and gate and the output end of the twentieth and gate are used for outputting a second down-sampling signal;
The multi-stage cascade filtering module is used for filtering an input signal based on a first downsampling signal to output a filtering signal, and the later stage filtering module is used for filtering the filtering signal output by the earlier stage filtering module again based on the first downsampling signal and a second downsampling signal to output a corresponding filtering signal;
the FIR filter includes:
the third downsampling signal generating circuit comprises N cascaded D flip-flops, wherein N is a natural number which is more than or equal to 2, the first stage D flip-flop is used for processing an input signal based on a clock signal to output tap coefficients, and the later stage D flip-flop is used for reprocessing the tap coefficients output by the former stage D flip-flop based on the clock signal to output corresponding tap coefficients;
m adders for carrying out summation logic operation on tap coefficients output by the two symmetrical D flip-flops to output corresponding logic signals, wherein M is an integer part equal to N/2;
a weighting coefficient generation circuit for outputting a weighting coefficient based on a part of the logic signal;
and a filter circuit for filtering based on the weighting coefficients and the partial tap coefficients to output a filtered signal.
2. The digital filtering device of claim 1, wherein the filtering module comprises a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, a twenty-first and gate, a twenty-second and gate, a twenty-third and gate, a twenty-fourth and gate, a twenty-fifth and gate, a first shift register, a second shift register, a third or gate, a fourth or gate, and a fifth or gate;
The first input end of the twenty-first AND gate is used for receiving 1' b1 or a first downsampling signal, the second input end of the twenty-first AND gate is used for receiving an input signal or is connected with the Q output end of a previous stage D trigger, the D input end of the first D trigger is connected with the output end of the twenty-first AND gate, the first input end of the twenty-second AND gate is used for receiving the first downsampling signal or a second downsampling signal, the second input end of the second AND gate is connected with the Q output end of the first D trigger, the D input end of the second D trigger is connected with the output end of the twenty-second AND gate, the first input end of the third AND gate is used for receiving the first downsampling signal or the second downsampling signal, the second input end of the third AND gate is connected with the Q output end of the second D trigger, and the D input end of the third D trigger is connected with the output end of the third AND gate;
the first input end of the twenty-fourth AND gate is used for receiving a first down-sampling signal or a second down-sampling signal, the second input end of the twenty-fourth AND gate is used for receiving an input signal or is connected with the Q output end of a D trigger of the previous stage, the D input end of the fourth D trigger is connected with the output end of the twenty-fourth AND gate, the first input end of the twenty-fifth AND gate is used for receiving the first down-sampling signal or the second down-sampling signal, the second input end of the twenty-fifth AND gate is connected with the Q output end of the fourth D trigger, and the D input end of the fifth D trigger is connected with the output end of the twenty-fifth AND gate;
The input end of the first shift register is connected with the Q output end of the fifth D trigger, the first input end of the third OR gate is connected with the Q output end of the fourth D trigger, the second input end of the third OR gate is connected with the Q output end of the fifth D trigger, the third input end of the third OR gate is connected with the output end of the first shift register, the input end of the second shift register is connected with the Q output end of the second D trigger, the first input end of the fourth OR gate is connected with the Q output end of the second D trigger, the second input end of the fourth OR gate is connected with the Q output end of the third D trigger, the third input end of the fourth OR gate is connected with the output end of the second shift register, the first input end of the fifth OR gate is connected with the output end of the third OR gate, the second input end of the fifth OR gate is connected with the output end of the fourth OR gate, and the output end of the fifth OR gate is used for outputting filtering signals.
3. The digital filtering device of claim 1, wherein the third downsampling signal generation circuit comprises a sixth D flip-flop, a seventh D flip-flop, an eighth D flip-flop, a ninth D flip-flop, a tenth D flip-flop, an eleventh D flip-flop, a twelfth D flip-flop, a thirteenth D flip-flop, a fourteenth D flip-flop, a fifteenth D flip-flop, a sixteenth D flip-flop, a seventeenth D flip-flop, an eighteenth D flip-flop, a nineteenth D flip-flop, and a twentieth D flip-flop that are cascaded with each other.
4. The digital filtering device of claim 3, wherein the adders include a first adder, a second adder, a third adder, a fourth adder, a fifth adder, a sixth adder, and a seventh adder;
the first input end of the first adder is connected with the Q output end of a sixth D trigger, the second input end of the first adder is connected with the Q output end of a twenty-first D trigger, the first input end of the second adder is connected with the Q output end of a seventh D trigger, the second input end of the second adder is connected with the Q output end of a nineteenth D trigger, the first input end of the third adder is connected with the Q output end of an eighth D trigger, the second input end of the third adder is connected with the Q output end of an eighteenth D trigger, the first input end of the fourth adder is connected with the Q output end of a ninth D trigger, the second input end of the fourth adder is connected with the Q output end of a seventeenth D trigger, the first input end of the fifth adder is connected with the Q output end of a sixteenth D trigger, the second input end of the fifth adder is connected with the Q output end of the seventeenth D trigger, and the Q output end of the seventeenth D trigger is connected with the Q output end of the seventeenth D trigger;
The output end of the first adder, the output end of the second adder, the output end of the third adder, the output end of the fourth adder, the output end of the fifth adder, the output end of the sixth adder and the output end of the seventh adder are used for outputting logic signals.
5. The digital filter device according to claim 4, wherein the weighting coefficient generation circuit includes a third shift register, a fourth shift register, a fifth shift register, a sixth shift register, a seventh shift register, an eighth shift register, a ninth shift register, a first complement module, a second complement module, a third complement module, an eighth adder, a ninth adder, a tenth adder, and an eleventh adder;
the input end of the third shift register is connected with the output end of the second adder, the input end of the fourth shift register is connected with the output end of the third adder, the first input end of the eighth adder is connected with the output end of the fourth shift register, the second input end of the eighth adder is connected with the output end of the third adder, the input end of the first complementary code taking module is connected with the output end of the eighth adder, the input end of the fifth shift register is connected with the output end of the fourth adder, the first input end of the ninth adder is connected with the output end of the fifth shift register, the second input end of the ninth adder is connected with the output end of the fourth adder, the input end of the second complementary code taking module is connected with the output end of the ninth adder, the input end of the sixth shift register is connected with the output end of the sixth adder, the input end of the seventh complementary code taking module is connected with the output end of the seventh adder, the input end of the seventh shift register is connected with the output end of the eighth adder;
The output end of the third shift register, the output end of the first complement module, the output end of the second complement module, the output end of the tenth adder and the output end of the eleventh adder are used for outputting the weighting coefficient.
6. The digital filtering device according to claim 5, wherein the filter circuit includes a tenth shift register, an eleventh shift register, a twelfth adder, a thirteenth adder, a fourteenth adder, and a fifteenth adder;
the input end of the tenth shift register, the input end of the eleventh shift register and the input end of the twelfth shift register are connected with the Q output end of the thirteenth D trigger, the first input end of the twelfth adder is connected with the output end of the tenth shift register, the second input end of the twelfth adder is connected with the output end of the eleventh shift register, and the third input end of the twelfth adder is connected with the output end of the twelfth shift register;
the first input end of the thirteenth adder is connected with the output end of the first adder, the second input end of the thirteenth adder is connected with the output end of the first complementary code taking module, the third input end of the thirteenth adder is connected with the output end of the fifth adder, the fourth input end of the thirteenth adder is connected with the output end of the eleventh adder, the first input end of the fourteenth adder is connected with the output end of the third shift register, the second input end of the fourteenth adder is connected with the output end of the second complementary code taking module, the third input end of the fourteenth adder is connected with the output end of the tenth adder, the fourth input end of the fourteenth adder is connected with the output end of the twelfth adder, the first input end of the fifteenth adder is connected with the output end of the thirteenth adder, the second input end of the fifteenth adder is connected with the output end of the fourteenth adder, and the output end of the fifteenth adder is used for outputting filtering signals.
7. The digital filtering device of claim 1, wherein the self-decrementing counter is configured to cycle from a 7-bit self-decrementing count to a period count of 0.
8. A chip comprising the digital filter device according to any one of claims 1 to 7.
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