CN116110872A - Low parasitic capacitance bonding pad - Google Patents
Low parasitic capacitance bonding pad Download PDFInfo
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- CN116110872A CN116110872A CN202310385849.4A CN202310385849A CN116110872A CN 116110872 A CN116110872 A CN 116110872A CN 202310385849 A CN202310385849 A CN 202310385849A CN 116110872 A CN116110872 A CN 116110872A
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- 230000003071 parasitic effect Effects 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 28
- 238000002161 passivation Methods 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 239000000956 alloy Substances 0.000 claims abstract description 5
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 5
- 101100207343 Antirrhinum majus 1e20 gene Proteins 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 4
- 239000003990 capacitor Substances 0.000 description 7
- 230000001052 transient effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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Abstract
The invention belongs to the field of semiconductor devices, and discloses a low parasitic capacitance bonding pad which comprises a substrate, a well region layer, a doped layer, a field oxide layer, a metal layer and a passivation layer, wherein the well region layer is sleeved in the substrate, the upper surface of the well region layer is flush with the upper surface of the substrate, the doped layer is arranged in a well region at the topmost layer in the well region layer and flush with the upper surface of the well region layer, the field oxide layer is arranged on the upper surface of the well region layer and covers the well region layer and the doped layer, the metal layer is arranged on the upper surface of the field oxide layer, the passivation layer is circumferentially arranged along the upper surface of the metal layer, and the exposed metal layer is connected with a semiconductor bond alloy wire to form an electrode of the device. According to the invention, the original multiple well region layers with different depths are utilized in the process to form a multi-layer well structure below the bonding pad, so that the capacitance from the bonding pad to the substrate is reduced layer by layer, and finally, the purpose of greatly reducing the parasitic capacitance value of the bonding pad is achieved.
Description
Technical Field
The invention belongs to the field of semiconductor devices, and particularly relates to a low parasitic capacitance bonding pad.
Background
Pads (pads) are an essential structure for electrode extraction of integrated circuits or semiconductor devices, however, non-ideal parameters of the pads can have a significant impact on the performance of the semiconductor device or circuit. For example, in the field of low capacitance transient suppressors (TVS), the total capacitance of a single device is required to be within 0.5 pF, and the parasitic capacitance of individual pads to the substrate can be of this order, so eliminating pad capacitance is particularly important. As the frequency of the integrated circuit signal increases, the parasitic capacitance of the pad structure of the low capacitance transient suppressor will have a significant impact on the chip performance. It is therefore necessary to devise a way to reduce pad placement parasitic capacitance when designing low capacitance transient suppressors.
Conventional pad structures are shown in fig. 1, where an oxide layer is deposited on a substrate, then a metal film of a desired thickness is deposited over the oxide layer, finally a passivation layer is fabricated over the metal film, and the passivation layer in the corresponding region is etched by pad mask lithography, and an external semiconductor bond wire (bonding wire) is connected to the metal film inside the chip. However, this pad structure is prone to generate large parasitic capacitance, which seriously affects the effectiveness of the circuit.
Disclosure of Invention
Aiming at the problems in the prior art, the invention discloses a bonding pad with low parasitic capacitance, which utilizes the original plurality of well layers with different depths in the process to form a multi-layer well structure below the bonding pad, and reduces the capacitance from the bonding pad to the substrate layer by layer, thereby finally achieving the purpose of greatly reducing the parasitic capacitance value of the bonding pad.
The technical aim of the invention is realized by the following technical scheme:
the utility model provides a low parasitic capacitance pad, includes substrate, well region layer, doped layer, field oxide layer, metal layer and passivation layer, wherein, well region layer cover sets up in the substrate, the upper surface of well region layer flushes with the substrate upper surface, doped layer sets up in the well region of topmost layer in the well region layer, and flush with the upper surface of well region layer, field oxide layer sets up at well region layer upper surface, and covers well region layer and doped layer, the metal layer sets up the upper surface of field oxide layer, the passivation layer sets up along metal layer upper surface circumference, and exposes the metal layer links to each other with the semiconductor bond alloy line, forms the electrode of device.
Preferably, the well region layer is sequentially nested from bottom to top and provided with a deep well layer, a first shallow well layer and a second shallow well layer from outside to inside, and the doped layer is arranged on the second shallow well layer.
Preferably, the doping types of the substrate, the doping layer and the first shallow well layer are the same, and the doping types of the deep well layer and the second shallow well layer are the same and opposite to the doping types of the substrate, the doping layer and the first shallow well layer.
Preferably, the well region layer only comprises a shallow well layer, the shallow well layer is arranged in the substrate, and the doping layer is arranged on the shallow well layer.
Preferably, the doping type of the shallow well layer is opposite to that of the substrate, and the doping type of the doping layer is the same as that of the substrate.
Preferably, the doped layer is a high doped layer with a doping concentration of 1e20/cm 3 。
Preferably, the height of the deep well layer is more than or equal to 3 mu m, and the doping concentration is 1e15/cm 3 。
Preferably, the height of the first shallow well layer is 1-2 μm, and the doping concentration is 1e16/cm 3 。
Preferably, the height of the second shallow well layer is 1-2 μm, and the doping concentration is 1e16/cm 3 。
Preferably, the height of the shallow well layer is 1-2 μm, and the doping concentration is 1e16/cm 3 。
The beneficial effects are that: the invention discloses a low parasitic capacitance bonding pad, which has the following advantages:
(1) The bonding pad has a multi-layer well structure, and the parasitic capacitance of the pad structure to the substrate is greatly reduced through the layer-by-layer shielding effect of the junction capacitance, so that the performance of the high-speed TVS device is improved.
(2) The pad capacitance in the invention can be reduced to 1/4-1/3 of the original pad capacitance, and the invention is suitable for the pad design of radio frequency or low parasitic integrated circuits, in particular for the design and manufacture of low capacitance transient suppressors (TVS) and high speed circuits.
Drawings
FIG. 1 is a diagram of a conventional bonding pad structure;
FIG. 2 is a multi-layer well pad structure (over an N-type region) of embodiment 1;
FIG. 3 is a multi-layer well pad structure (over a P-type region) of embodiment 2;
FIG. 4 is a schematic diagram of the integration of different multi-layer well pads in an integrated circuit board;
in the figure: p-type substrate 00, device I01, device II02, device III03, device IV04, N-type deep well layer 11, P-type first shallow well layer 12, N-type second shallow well layer 13, p+ doped layer 14, N-type shallow well layer 15, field oxide layer 21, metal layer 31, passivation layer 41.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Example 1 (taking a P-type substrate as an example)
As shown in fig. 2, the pad is disposed above the N-type region, and has the following specific structure: an N-type deep well layer 11 is arranged on the P-type substrate 00, a P-type first shallow well layer 12 is arranged in the N-type deep well layer 11, an N-type second shallow well layer 13 is arranged in the P-type first shallow well layer 12, a P+ doped layer 14 is arranged in the N-type second shallow well layer 13, wherein the upper surfaces of the N-type deep well layer 11, the P-type first shallow well layer 12, the N-type second shallow well layer 13 and the P+ doped layer 14 are flush with the P-type substrate 00, a field oxide layer 21 is arranged above the P+ doped layer 14, a metal layer 31 is arranged above the field oxide layer 21, a passivation layer 41 is arranged above the metal layer 31, the metal layer 31 is exposed after the passivation layer 41 is subjected to photoetching by using a bonding pad template, and the exposed metal layer is connected with a semiconductor bond alloy line to form an electrode of a device.
In this example 1, the P+ doped layer 14 is a highly doped layer with a doping concentration of 1e20/cm 3 The N-type deep well layer 11 has a height of 3 μm and a doping concentration of 1e15/cm 3 . The height of the P-type first shallow well layer 12 is 1-2 μm, and the doping concentration is 1e16/cm 3 . The height of the N-type second shallow well layer 13 is 1-2 μm, and the doping concentration is 1e16/cm 3 。
Example 2 (taking a P-type substrate as an example)
As shown in fig. 3, the pad is disposed above the P-type region, and has the following specific structure: an N-type shallow well layer 15 is directly arranged on the P-type substrate 00, a P+ doped layer 14 is arranged in the N-type shallow well layer 15, wherein the upper surfaces of the N-type shallow well layer 15 and the P+ doped layer 14 are flush with the P-type substrate 00, a field oxide layer 21 is arranged above the P+ doped layer 14, a metal layer 31 is arranged above the field oxide layer 21, a passivation layer 41 is arranged above the metal layer 31, a pad window is formed in the passivation layer 41 after photoetching and etching by using a pad mask to expose the metal layer 31, and the exposed metal layer 31 is connected with a semiconductor bond alloy wire to form an electrode of the device.
In this example 2, the P+ doped layer 14 is a highly doped layer with a doping concentration of 1e20/cm 3 The N-type shallow well layer 15 has a height of 1-2 μm and a doping concentration of 1e16/cm 3 。
As shown in fig. 4, when two pads disclosed in embodiments 1 and 2 are integrated in the same circuit board, nesting is required to be performed by different layers. As can be seen from fig. 4, the device I01 and the device II02 are connected by the metal layer 31, and the device I01 and the device II02 are both located in the N-type deep well layer 11, the N-type deep well layer 11 is located in the P-type substrate 00, then the opening above the metal (i.e. the pad window) needs to be nested in the p+ doped layer 14, and the periphery of the p+ doped layer 14 is nested with the N-type second shallow well layer 13 and the P-type first shallow well layer 12 sequentially from inside to outside; and the device III03 and the device IV04 are connected through the metal layer 31 and are all positioned in the P-type substrate 00, then the opening above the metal is nested in the P+ doped layer 14, and the periphery of the P+ doped layer 14 is nested with the N-type shallow well layer 15.
The working principle of the invention is as follows:
when a radio frequency signal is loaded on a pad, MIS capacitance, which in conventional devices is made of metal-oxide-semiconductor, will directly affect signal integrity, thereby creating additional attenuation to the signal. After the multi-layer well design of the invention, the metal-oxide-semiconductor capacitor is arranged in the original stateC 1 Based on the above, a plurality of PN junction barrier capacitors are connected in series, for example, embodiment 1 shown in FIG. 2 is taken as an example, such as the P+ doped layer 14/N type second shallow well layer 13 capacitorC 2 N-type second shallow well layer 13/P-type first shallow well layer 12 capacitorC 3 P-type first shallow well layer 12/N-type deep well layer 11 capacitorC 4 N-type deep well layer 11/P-type substrate 00 capacitorC 5 According to the capacitance series formula
After series connection, it can be seen thatThe total capacitance of (2) will be smaller than the smallest one of them, and therefore will greatly reduce the substrate parasitic capacitance and reduce signal attenuation. As can be seen from FIG. 4, the pad capacitance is reduced to 1/4-1/3 of the original pad capacitance due to the fact that the area of the multi-layer well is almost identical to the area of the pad window, and the pad capacitor has obvious effect, simple design and compatible process.
The proposed structure can be implemented by various other processes or substrates besides the embodiments, and the structure thereof should be within the scope of the present invention. For example, when the substrate of the bonding pad is an N-type substrate, the well region layer of the bonding pad is sequentially nested from bottom to top, and the P-type deep well layer, the N-type first shallow well layer and the P-type second shallow well layer are sequentially nested from outside to inside, and the doped layer is an n+ doped layer. Or the well region layer of the bonding pad only comprises a P-type shallow well layer, and the doping layer is an N+ doping layer.
The present embodiment is only for explanation of the present invention and is not to be construed as limiting the present invention, and modifications to the present embodiment, which may not creatively contribute to the present invention as required by those skilled in the art after reading the present specification, are all protected by patent laws within the scope of claims of the present invention.
Claims (10)
1. The low parasitic capacitance bonding pad is characterized by comprising a substrate, a well region layer, a doped layer, a field oxide layer, a metal layer and a passivation layer, wherein the well region layer is sleeved in the substrate, the upper surface of the well region layer is flush with the upper surface of the substrate, the doped layer is arranged in a well region at the topmost layer in the well region layer and flush with the upper surface of the well region layer, the field oxide layer is arranged on the upper surface of the well region layer and covers the well region layer and the doped layer, the metal layer is arranged on the upper surface of the field oxide layer, the passivation layer is circumferentially arranged along the upper surface of the metal layer and exposes the metal layer to be connected with a semiconductor bond alloy wire to form an electrode of a device.
2. The low parasitic capacitance bonding pad of claim 1, wherein the well region layer is sequentially nested from bottom to top with a deep well layer, a first shallow well layer and a second shallow well layer from outside to inside, and the doped layer is disposed on the second shallow well layer.
3. The low parasitic capacitance pad of claim 2, wherein the substrate, doped layer, and first shallow well layer are of the same doping type, and the deep well layer and second shallow well layer are of the same doping type and of opposite doping type to the substrate, doped layer, and first shallow well layer.
4. The low parasitic capacitance pad of claim 1, wherein the well region layer comprises only a shallow well layer disposed within the substrate, the doped layer disposed at the shallow well layer.
5. The low parasitic capacitance pad of claim 4, wherein the shallow well layer is of an opposite doping type to the substrate and the doping layer is of the same doping type as the substrate.
6. The low parasitic capacitance pad of any one of claims 1-5, wherein the doped layer is a highly doped layer having a doping concentration of 1e20/cm 3 。
7. The low parasitic capacitance pad of claim 2 or 3, wherein the deep well layer has a height of 3 μm or more and a doping concentration of 1e15/cm 3 。
8. A low parasitic capacitance pad according to claim 2 or 3, wherein the first shallow well layer has a height of 1-2 μm and a doping concentration of 1e16/cm 3 。
9. A low parasitic capacitance pad as claimed in claim 2 or 3, wherein the second shallow well layer has a height of 1-2 μm and a doping concentration of 1e16/cm 3 。
10. The low parasitic capacitance pad of claim 4 or 5, wherein the height of the shallow well layer is 1-2 μm and is doped withThe impurity concentration is 1e16/cm 3 。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310385849.4A CN116110872A (en) | 2023-04-12 | 2023-04-12 | Low parasitic capacitance bonding pad |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310385849.4A CN116110872A (en) | 2023-04-12 | 2023-04-12 | Low parasitic capacitance bonding pad |
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| CN116110872A true CN116110872A (en) | 2023-05-12 |
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| CN202310385849.4A Pending CN116110872A (en) | 2023-04-12 | 2023-04-12 | Low parasitic capacitance bonding pad |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010010404A1 (en) * | 1999-03-19 | 2001-08-02 | Ming-Dou Ker | Low-capacitance bonding pad for semiconductor device |
| US20050242416A1 (en) * | 2004-04-29 | 2005-11-03 | United Microelectronics Corp. | Low-capacitance bonding pad for semiconductor device |
| CN101656239A (en) * | 2009-07-22 | 2010-02-24 | 上海宏力半导体制造有限公司 | Bonding welding disk lowering parasitic capacitance and preparing method thereof |
| CN102024774A (en) * | 2009-09-16 | 2011-04-20 | 上海宏力半导体制造有限公司 | Contact pad |
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2023
- 2023-04-12 CN CN202310385849.4A patent/CN116110872A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010010404A1 (en) * | 1999-03-19 | 2001-08-02 | Ming-Dou Ker | Low-capacitance bonding pad for semiconductor device |
| US20050242416A1 (en) * | 2004-04-29 | 2005-11-03 | United Microelectronics Corp. | Low-capacitance bonding pad for semiconductor device |
| CN101656239A (en) * | 2009-07-22 | 2010-02-24 | 上海宏力半导体制造有限公司 | Bonding welding disk lowering parasitic capacitance and preparing method thereof |
| CN102024774A (en) * | 2009-09-16 | 2011-04-20 | 上海宏力半导体制造有限公司 | Contact pad |
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Application publication date: 20230512 |