CN116108926B

CN116108926B - Quantum computing method, device, equipment and storage medium

Info

Publication number: CN116108926B
Application number: CN202211197092.8A
Authority: CN
Inventors: 王鑫; 王友乐; 余展; 张磊
Original assignee: Beijing Baidu Netcom Science and Technology Co Ltd
Current assignee: Beijing Baidu Netcom Science and Technology Co Ltd
Priority date: 2022-09-28
Filing date: 2022-09-28
Publication date: 2024-08-09
Anticipated expiration: 2042-09-28
Also published as: CN116108926A

Abstract

The disclosure provides a quantum computing method, a device, equipment and a storage medium, and relates to the technical field of computers, in particular to the field of quantum computing. The specific implementation scheme is as follows: determining a target parameter value of a target adjustable parameter in a sub-circuit of a target quantum circuit within a first error range; the target quantum circuit comprises an auxiliary register and a main register, and the sub-circuit acts on the auxiliary register; the target quantum circuit also comprises a target controlled unitary gate controlled by the auxiliary register and acting on the main register, wherein the target controlled unitary gate is used for acquiring the characteristic phase of the unitary operator U; acquiring state information of an auxiliary register in a target quantum circuit under the condition that a target adjustable parameter is the target parameter value, a first input state of the auxiliary register is a preset initial state and a second input state of a main register is a characteristic state of a unitary operator U; based on the state information of the auxiliary register, the characteristic phase of the unitary operator U in the first error range is estimated.

Description

Quantum computing method, device, equipment and storage medium

Technical Field

The present disclosure relates to the field of computer technology, and in particular, to the field of quantum computing technology.

Background

The recent development of the quantum computing field is rapid, and the quantum computing field from quantum algorithm and quantum hardware equipment to quantum soft and hard integrated platform is advancing towards large-scale and practical stable steps. Among them, solving the actual problem by quantum computing and bringing about quantum advantage is one direction of great interest. In this direction, solving eigenvalues of quantum evolution (such as unitary operators, unitary operator) is a core problem.

Disclosure of Invention

The present disclosure provides a quantum computing method, apparatus, device, and storage medium.

According to an aspect of the present disclosure, there is provided a quantum computing method including:

Determining a target parameter value of a target adjustable parameter in a sub-circuit of a target quantum circuit within a first error range; the target quantum circuit comprises an auxiliary register and a main register, and the sub-circuit acts on the auxiliary register; the target quantum circuit also comprises a target controlled unitary gate which is controlled by the auxiliary register and acts on the main register, and the target controlled unitary gate is used for acquiring the characteristic phase of the unitary operator U; the unitary operator U represents the evolution characteristics of the target quantum system;

Acquiring state information of the auxiliary register in the target quantum circuit under the condition that the target adjustable parameter is the target parameter value, the first input state of the auxiliary register is a preset initial state and the second input state of the main register is the characteristic state of the unitary operator U; and

And estimating and obtaining the characteristic phase of the unitary operator U in the first error range based on the state information of the auxiliary register.

According to another aspect of the present disclosure, there is provided a quantum computing device, comprising:

the parameter processing unit is used for determining a target parameter value of a target adjustable parameter in a sub-circuit of the target quantum circuit within a first error range; the target quantum circuit comprises an auxiliary register and a main register, and the sub-circuit acts on the auxiliary register; the target quantum circuit also comprises a target controlled unitary gate which is controlled by the auxiliary register and acts on the main register, and the target controlled unitary gate is used for acquiring the characteristic phase of the unitary operator U; the unitary operator U represents the evolution characteristics of the target quantum system;

The measuring unit is used for acquiring state information of the auxiliary register in the target quantum circuit under the condition that the target adjustable parameter is the target parameter value, the first input state of the auxiliary register is a preset initial state and the second input state of the main register is a characteristic state of the unitary operator U; and

And the output unit is used for estimating and obtaining the characteristic phase of the unitary operator U in the first error range based on the state information of the auxiliary register.

According to yet another aspect of the present disclosure, there is provided a computing device comprising:

At least one quantum processing unit;

a memory coupled to the at least one QPU and configured to store executable instructions,

The instructions are executed by the at least one quantum processing unit to enable the at least one quantum processing unit to perform the method described above;

Or comprises:

At least one processor; and

A memory communicatively coupled to the at least one processor; wherein,

The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method described above.

According to yet another aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions that, when executed by at least one quantum processing unit, cause the at least one quantum processing unit to perform the method described above;

or the computer instructions for causing the computer to perform the method described above.

According to a further aspect of the present disclosure, there is provided a computer program product comprising a computer program which, when executed by at least one quantum processing unit, implements the method described above;

or which when executed by a processor implements the method described above.

In this way, the scheme provides a novel quantum phase estimation scheme on the aspect of obtaining the characteristic phase problem of the unitary operator; moreover, the scheme does not limit the unitary operator, in other words, the estimation of the characteristic phase of any unitary operator can be realized, and the universality is strong. Further, the scheme disclosed by the invention can be applied to large-scale unitary operators, and therefore, the scheme also has expansibility.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.

Drawings

The drawings are for a better understanding of the present solution and are not to be construed as limiting the present disclosure. Wherein:

FIG. 1 is a schematic diagram of an implementation flow of a quantum computing method according to an embodiment of the present disclosure;

FIG. 2 is a second flow diagram of an implementation of a quantum computing method according to an embodiment of the disclosure;

fig. 3 (a) to 3 (c) are schematic structural diagrams of a preset parameterized quantum circuit according to an embodiment of the present disclosure;

fig. 4 (a) and 4 (b) are schematic structural diagrams of a target quantum circuit according to an embodiment of the present disclosure;

FIG. 5 is a flowchart of an implementation of a preset parameterized quantum circuit training method according to an embodiment of the present disclosure;

FIG. 6 is a schematic flow diagram of an implementation of a quantum computing method in a particular embodiment in accordance with an embodiment of the disclosure;

FIG. 7 is a schematic diagram of a quantum computing device according to an embodiment of the present disclosure;

Fig. 8 is a block diagram of a computing device used to implement quantum computing methods of embodiments of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding, and should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. The term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, e.g., including at least one of A, B, C, may mean including any one or more elements selected from the group consisting of A, B and C. The terms "first" and "second" herein mean a plurality of similar technical terms and distinguishes them, and does not limit the meaning of the order, or only two, for example, a first feature and a second feature, which means that there are two types/classes of features, the first feature may be one or more, and the second feature may be one or more.

In addition, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be appreciated by one skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.

The recent development of the quantum computing field is rapid, and the quantum computing field from quantum algorithm and quantum hardware equipment to quantum soft and hard integrated platform is advancing towards large-scale and practical stable steps. Among them, solving the actual problem by quantum computing and bringing about quantum advantage is one direction of great interest. In this direction, solving eigenvalues of quantum evolution (such as unitary operators, unitary operator) is a core problem, also called quantum phase estimation.

Here, on the one hand, the eigenvalue of unitary operator represents the characteristic of a physical process, and the eigenvalue can be solved for researching the ground state and the excited state energy of the quantum system, which has important significance for scientific research and industrial development. For example, in lithium battery technology, the property of efficiently extracting the ground state may promote the development of lithium battery technology, including improving energy storage, fast charging, and reducing material consumption of the battery.

On the other hand, eigenvalue solution of unitary operator is also a core step of many quantum applications, and in recent years, quantum phase estimation technology is used for eigenvalue estimation of quantum system, solving problems such as linear equation set, principal component analysis, discrete logarithm, etc., it is worth noting that the two problems have many applications in machine learning, and discrete logarithm is a core principle of public key encryption scheme.

In general, it is very difficult to calculate eigenvalues of quantum unitary operators. First, classical computing wants to accomplish such tasks, requiring operations such as chromatography on quantum unitary operators, and facing exponentially growing systems, can be very difficult. The current scheme capable of carrying out quantum characteristic solution has higher requirements in aspects of quantum circuit width and the like. Based on recent quantum equipment, a more efficient and practical quantum characteristic solving scheme is urgently needed, on one hand, the problem of intrinsic energy of a quantum system can be solved, and on the other hand, the quantum characteristic solving scheme can be applied to the aspects of solving chemical problems, machine learning problems, discrete logarithms and the like in a quantum computing mode.

Therefore, the method for solving the eigenvalue of the quantum unitary operator is a practical problem and has a plurality of expansion applications.

Based on the above, the scheme provides a quantum phase estimation scheme, which can efficiently obtain the characteristic phase of the unitary operator U. Specifically, fig. 1 is a schematic diagram of an implementation flow of a quantum computing method according to an embodiment of the present disclosure; the method is optionally applied to a quantum computing device with classical computing capability, and also can be applied to a classical computing device with classical computing capability, or directly applied to an electronic device with classical computing capability, such as a personal computer, a server cluster, and the like, or directly applied to a quantum computer, and the scheme of the disclosure is not limited to this.

Further, the method includes at least part of the following. As shown in fig. 1, the quantum computing processing method includes:

step S101: a target parameter value for a target tunable parameter in a sub-circuit of a target quantum circuit is determined within a first error range.

The target quantum circuit comprises an auxiliary register and a main register, and the sub-circuit acts on the auxiliary register; the target quantum circuit also comprises a target controlled unitary gate which is controlled by the auxiliary register and acts on the main register, and the target controlled unitary gate is used for acquiring the characteristic phase of the unitary operator U; and the unitary operator U represents the evolution characteristics of the target quantum system. Therefore, the characteristic phase of the unitary operator U is conveniently solved by utilizing the target quantum circuit, and the ground state characteristic of the target quantum system is solved.

It will be appreciated that at least some of the sub-circuits are circuits of the target quantum circuit that contain target adjustable parameters, i.e. the sub-circuits are parametric quantum circuits that contain target adjustable parameters.

Step S102: and acquiring state information of the auxiliary register in the target quantum circuit under the condition that the target adjustable parameter is the target parameter value, the first input state of the auxiliary register is a preset initial state and the second input state of the main register is the characteristic state of the unitary operator U.

Here, the second input state may be specifically any one of characteristic states of the unitary operator U.

Step S103: and estimating and obtaining the characteristic phase of the unitary operator U in the first error range based on the state information of the auxiliary register.

In this way, the scheme of the disclosure adopts the target quantum circuit comprising the auxiliary register and the main register, and under the condition that the target adjustable parameter is the target parameter value, the state information of the auxiliary register is obtained by inputting the first input state and the second input state, so that the characteristic phase of the unitary operator U is obtained; in this way, the scheme provides a novel quantum phase estimation scheme on the aspect of obtaining the characteristic phase problem of the unitary operator; moreover, the scheme does not limit the unitary operator, in other words, the estimation of the characteristic phase of any unitary operator can be realized, and the universality is strong. Further, the scheme disclosed by the invention can be applied to large-scale unitary operators, and therefore, the scheme also has expansibility.

In a specific example, the auxiliary register includes at least one qubit, such as one, or two, or more than two qubits. Further, the number of qubits contained in the main register is the same as the number of qubits contained in the target quantum system represented by the unitary operator U.

Here, for convenience of distinction, the qubits contained in the auxiliary registers may be referred to as auxiliary qubits; accordingly, the qubits contained by the master register are referred to as master qubits.

For example, the target quantum system includes n qubits, where in order to obtain the characteristic phase of unitary operator U representing the target qubit, the main register in the target quantum circuit needs to include n main qubits; and n is a positive integer greater than or equal to 1.

In a specific example, the obtaining the state information of the auxiliary register in the target quantum circuit in step S102 may specifically include:

obtaining the observability of the target quantum circuit Is a desired value of (2);

Here, the observability amount The expected value of (a) is the state information of the auxiliary register.

Further, the observability amountIn particular, the measurement operator Z acts on the auxiliary register, while the remaining qubits (i.e. the main register) do not operate, where I represents the identity matrix. Thus, the state information of the auxiliary register can be obtained.

In a specific example, the preset initial state may be specifically, for example, |0>, or |1>. The present disclosure is not particularly limited thereto.

In a specific example of the present disclosure, the following information may also be obtained based on the obtained characteristic phase; specifically, the method further comprises the following steps:

and obtaining the characteristic value of the target quantum system based on the characteristic phase of the unitary operator U.

Here, in an example, the characteristic phase α and the characteristic value λ satisfy the following relationship:

λ＝e^2πiα

based on the formula, after the characteristic phase alpha of the unitary operator U is obtained, the characteristic value of the unitary operator U can be obtained.

Here, in practical application, if the second input state, that is, the characteristic state of the unitary operator U, is the ground state of the target quantum system, at this time, the obtained characteristic value is solved, that is, the characteristic value corresponding to the ground state of the target quantum system.

Further, the characteristic value of the unitary operator U can be obtained based on the state information of the auxiliary register, at this time, the output state of the target quantum circuit is the characteristic state of the unitary operator U, namely the second input state of the main register is the same as the output state of the target quantum circuit, so that the novel quantum phase estimation scheme is provided, the input characteristic state, namely the output state of the target quantum circuit, is not consumed, and the novel quantum phase estimation scheme has important significance for scientific research and industrial development.

Fig. 2 is a second schematic diagram of an implementation flow of a quantum computing method according to an embodiment of the disclosure. The method can be optionally applied to a quantum computing device with classical computing capability, or can be directly applied to a classical computing device with classical computing capability, such as a personal computer, a server cluster and other electronic devices with classical computing capability, or can be directly applied to a quantum computer, and the scheme of the disclosure is not limited to this.

It will be appreciated that the relevant content of the method shown in fig. 1 above may also be applied to this example, and this example will not be repeated for the relevant content.

Further, the method includes at least part of the following. Specifically, as shown in fig. 2, the method includes:

Step S201: and taking the target parameter value of the target adjustable parameter in the trained preset parameterized quantum circuit as the target parameter value of the target adjustable parameter in the sub-circuit within the first error range.

That is, the target adjustable parameter is included in the preset parameterized quantum circuit, so that the target parameter value of the target adjustable parameter in the trained preset parameterized quantum circuit is used as the target parameter value of the target adjustable parameter in the sub-circuit. In other words, in this example, the target parameter value of the target tunable parameter in the sub-circuit is obtained by training other parameterized quantum circuits.

In this example, for the description of the sub-circuit and the target quantum circuit, reference may be made to the above description, and details are not repeated here.

It should be noted that other adjustable parameters may be further included in the preset parameterized quantum circuit, which is not particularly limited in the present disclosure, as long as the preset parameterized quantum circuit includes the target adjustable parameters required by the sub-circuit.

Further, the training-completed preset parameterized quantum circuit is used for simulating an objective function f (x).

Further, the target quantum circuit is based on the following:

Taking the quantum bit in the preset parameterized quantum circuit as an auxiliary register, expanding a main register, and simultaneously replacing a first turnstile acting on the auxiliary register in the preset parameterized quantum circuit with the target controlled unitary gate; that is, the target quantum circuit is extended based on a preset parameterized quantum circuit.

Here, the rotation parameter of the first rotation door is an argument x of the objective function f (x).

Further, the sub-circuit comprises at least part of circuits except the first rotating gate in the preset parameterized quantum circuit.

It can be understood that, since the target quantum circuit is obtained by expanding on the basis of the preset parameterized quantum circuit, the sub-circuit can also be obtained on the basis of the preset parameterized quantum circuit, and the sub-circuit comprises a part of circuit structure corresponding to the target adjustable parameter in the preset parameterized quantum circuit, thus laying a foundation for obtaining the target parameter value of the target adjustable parameter of the sub-circuit by training the preset parameterized quantum circuit.

Step S202: and acquiring state information of the auxiliary register in the target quantum circuit under the condition that the target adjustable parameter is the target parameter value, the first input state of the auxiliary register is a preset initial state and the second input state of the main register is the characteristic state of the unitary operator U.

Step S203: and estimating and obtaining the characteristic phase of the unitary operator U in the first error range based on the state information of the auxiliary register.

It can be appreciated that, because the preset parameterized quantum circuit has a simple circuit structure compared with the target quantum circuit, the calculation amount can be effectively reduced by training the preset parameterized quantum circuit to obtain the target parameter value of the target adjustable parameter, and a foundation is laid for efficiently solving and obtaining the characteristic phase of the unitary operator U.

Further, in practical application, the preset parameterized quantum circuit can be obtained in a classical computing device in a simulation mode, and correspondingly, the target parameter value of the target adjustable parameter obtained through training can also be achieved in the classical computing device, so that the quantum computing resource can not be occupied in the mode of obtaining the target parameter value of the target adjustable parameter in the scheme, and therefore, the computing cost is effectively reduced while a foundation is laid for efficiently solving the characteristic phase of the unitary operator U.

Moreover, the scheme does not limit the unitary operator, in other words, the estimation of the characteristic phase of any unitary operator can be realized, and the universality is strong. Meanwhile, the scheme disclosed by the invention can be applied to large-scale unitary operators, so that the scheme also has expansibility. In summary, the scheme disclosed by the invention has high efficiency, universality and expansibility.

In a specific example, a function analysis method may also be used to obtain a target parameter value of the target adjustable parameter; specifically, a target Fourier series F (x) of the target function is obtained, wherein the target Fourier series F (x) is a Fourier series of the target function in a target definition domain. Further, other Fourier series, such as other Fourier series P (x) and Q (x), are obtained based on the target Fourier series F (x), wherein,

Obtaining a target parameter value of the target adjustable parameter based on a preset relational expression; for example, for the target quantum circuit shown in fig. 4 (b), the preset relation may be specifically:

Here, Q ^* (x) is the complex conjugate of Q (x), and P ^* (x) is the complex conjugate of P (x).

Therefore, the calculated amount can be effectively reduced, and a foundation is laid for obtaining the characteristic phase of the unitary operator U through efficient solving.

In a specific example of the disclosure, the preset parameterized quantum circuit includes L training layers; l is a positive integer greater than or equal to 1; further, the value of L is related to the first error range;

at least one training layer of the L training layers comprises:

the first revolving door is used for carrying out a revolving operation on a first angle by the revolving parameter x;

A second rotation gate for performing a rotation operation on a second angle and acting on a qubit in the preset parameterized quantum circuit;

A third rotation gate for performing a rotation operation on a third angle and acting on a qubit in the preset parameterized quantum circuit;

And the rotation angle phi of the second revolving door and the rotation angle theta of the third revolving door are the target adjustable parameters.

In practical application, the types and the numbers of the revolving doors contained in different training layers in the L training layers may be the same, for example, the revolving doors described above are all included; or may be different, for example, some training layers include at least one of the revolving doors described above, and other training layers include other quantum doors, etc., which is not limited in this disclosure.

In a specific example, the preset parameterized quantum circuit includes a qubit, and in this case, the first turnstile, the second turnstile, and the third turnstile are single-qubit turnstiles acting on the qubit.

Further, in another example, the preset parameterized quantum circuit includes a qubit, and each of the L training layers includes a first turnstile, a second turnstile, and a third turnstile, that is, the first turnstile, the second turnstile, and the third turnstile of each training layer are single qubit turnstiles acting on the qubit.

Therefore, the expression capability of the preset parameterized quantum circuit is effectively improved, and meanwhile, the types and the quantity of the used quantum gates are small, so that a foundation is laid for obtaining the characteristic value of the unitary operator U through efficient solving.

In a specific example of the present disclosure, each angle satisfies one of the following conditions:

the first angle is an angle corresponding to the z-axis;

The second angle is an angle corresponding to the z-axis;

The third angle is an angle corresponding to the y axis.

That is, in an example, the first angle is an angle corresponding to the z-axis; in another example, the second angle is an angle corresponding to the z-axis; in yet another example, the third angle is an angle corresponding to the y-axis; or any two of the above conditions are satisfied, for example, the first angle and the second angle are both angles corresponding to the z-axis, and the like. Or simultaneously meets the three conditions, namely, the first angle and the second angle are both angles corresponding to the z axis, and the third angle is an angle corresponding to the y axis.

For example, in a specific example, at least one of the L training layers includes:

the first revolving door;

the second revolving door is used for carrying out revolving operation on an angle corresponding to the z axis;

and the third revolving door is used for carrying out revolving operation on the angle corresponding to the y axis.

Further, in another specific example, the preset parameterized quantum circuit includes a qubit, and at this time, the first turnstile, the second turnstile, and the third turnstile are single-qubit turnstiles acting on the qubit.

Further, each of the L training layers includes:

A first revolving door;

Therefore, the method and the device effectively improve the expression capacity of the preset parameterized quantum circuit, meanwhile, the types and the quantity of the used quantum gates are small, and the quantity of target adjustable parameters to be trained is small, so that a foundation is laid for efficiently solving and obtaining the characteristic value of the unitary operator U.

In a specific example of the present disclosure, in a case where at least one of the L training layers includes the first revolving door, the second revolving door, and the third revolving door, the revolving door acts in the following order:

the second revolving door, the third revolving door and the first revolving door.

That is, in a specific example, at least one of the L training layers sequentially includes, in order of action of the revolving door:

The third revolving door is used for carrying out revolving operation on the angle corresponding to the y axis;

the first revolving door.

For example, taking the example that the preset parameterized quantum circuit includes one quantum bit, the first rotating gate, the second rotating gate and the third rotating gate are single-quantum bit rotating gates acting on the quantum bit, as shown in fig. 3 (a), the i-th training layer of the L training layers sequentially includes, according to an order of action:

The second rotating door R _Z(φ_i with the rotating angle phi _i being the angle corresponding to the z axis);

The third revolving door R _Y(θ_i with the rotation angle theta _i being the angle corresponding to the y axis);

The rotation parameter x _j is the first rotation door R _Z(x_j of the angle corresponding to the z-axis).

Here, the rotation angle Φ _i of the second rotation door R _Z(φ_i) and the rotation angle θ _i of the third rotation door R _Y(θ_i) are target adjustable parameters in the ith training layer, where i is an integer greater than or equal to 1 and less than or equal to L.

Further, in another specific example, each of the L training layers has a structure as shown in fig. 3 (a), which is not described herein.

In a specific example of the disclosure, after the L training layers of the preset parameterized quantum circuit, other rotating gates are further included.

In a specific example, after the preset L training layers of the parameterized quantum circuit, the method further includes:

a fourth rotation gate for performing a rotation operation on a fourth angle and acting on a qubit in the preset parameterized quantum circuit;

a fifth rotation gate for performing a rotation operation on a fifth angle and acting on a qubit in the preset parameterized quantum circuit;

The rotation angle phi ₀ of the fourth revolving door and the rotation angle theta ₀ of the fifth revolving door are the target adjustable parameters.

In a specific example, the preset parameterized quantum circuit includes a qubit, and in this case, the fourth rotation gate and the fifth rotation gate are both single-qubit rotation gates acting on the qubit.

For example, in one example, as shown in fig. 3 (b), the preset parameterized quantum circuit further includes, after L training layers:

A fourth rotation door R _Z(φ₀ having a rotation angle phi ₀ corresponding to the z-axis);

The rotation angle θ ₀ is the fifth rotation door R _Y(θ₀ of the angle corresponding to the y axis).

Here, the rotation angle Φ ₀ and the rotation angle θ ₀ are also target adjustable parameters.

Based on this, the mathematical expression of the preset parameterized quantum circuit as shown in fig. 3 (b) may be specifically:

A sixth rotation gate for performing a rotation operation on the sixth angle and acting on the qubit in the preset parameterized quantum circuit;

Wherein the rotation angle phi ₀ of the fourth revolving door and the rotation angle theta ₀ of the fifth revolving door are the target adjustable parameters; the rotation angle alpha of the sixth revolving door is a fixed parameter, namely a parameter which does not participate in training. Or the rotation angle phi ₀ of the fourth revolving door, the rotation angle theta ₀ of the fifth revolving door and the rotation angle alpha of the sixth revolving door are all the target adjustable parameters.

In a specific example, the preset parameterized quantum circuit includes a qubit, and in this case, the fourth turngate, the fifth turngate and the sixth turngate are all single-qubit turngates acting on the qubit.

For example, in another example, as shown in fig. 3 (c), the preset parameterized quantum circuit further includes, after L training layers:

A fifth rotating door R _Y(θ₀ having a rotation angle θ ₀ corresponding to the y-axis);

And a sixth rotating door R _Z (α) whose rotation angle α is an angle corresponding to the z-axis.

Here, the rotation angle Φ ₀, the rotation angle θ ₀, and the rotation angle α are all target adjustable parameters.

Based on this, the mathematical expression of the preset parameterized quantum circuit as shown in fig. 3 (c) may be specifically:

Or the rotation angle phi ₀ and the rotation angle theta ₀ are target adjustable parameters, and the rotation angle alpha is a fixed parameter and does not participate in training.

therefore, the method and the device effectively improve the expression capacity of the preset parameterized quantum circuit, meanwhile, the types and the quantity of the used quantum gates are small, and the quantity of target adjustable parameters to be trained is small, so that a foundation is laid for efficiently solving and obtaining the characteristic value of the unitary operator U, and meanwhile, a foundation is laid for improving the accuracy of the result.

In a specific example of the disclosure, the target quantum circuit includes L layers, at least one of the L layers being obtained after replacing a first revolving gate in a training layer with the target controlled unitary gate; the training layer is any training layer in L training layers.

It can be understood that, because the target quantum circuit is obtained by expanding on the basis of the preset parameterized quantum circuit, the target quantum circuit obtained by expanding also comprises an L layer.

In a specific example, at least one training layer (such as the ith training layer) of the L training layers includes: the first revolving door, the second revolving door and the third revolving door are arranged in the target quantum circuit, and at the moment, a layer, such as an ith layer, exists in the target quantum circuit, and is obtained by replacing the first revolving door of the ith training layer with the target controlled unitary door.

Further, in an example, the target quantum circuit is obtained after replacing the first rotation gates in each training layer of the preset parameterized quantum circuit with target controlled unitary gates. That is, the number of target controlled unitary gates in the target quantum circuit is the same as the number of first rotating gates in the preset parameterized quantum circuit.

Specifically, in the case that each training layer in the preset parameterized quantum circuit includes the first revolving door, the second revolving door and the third revolving door, and the acting sequence of each revolving door is shown in fig. 3 (a), the ith layer in the L layers of the target quantum circuit is obtained by replacing the first revolving door in the ith training layer with the target controlled unitary door; specifically, as shown in fig. 4 (a), the ith layer (i takes a value of 1 to L) in the target quantum circuit includes, in order of action of the quantum gates:

Target controlled unitary gates.

Further, the (i+1) th layer in the L layers of the target quantum circuit is obtained by replacing a first revolving gate in the (i+1) th training layer of the preset parameterized quantum circuit with the target controlled unitary gate. Specifically, the (i+1) th layer in the target quantum circuit comprises the following components in the action sequence of quantum gates:

The second rotating door R _Z(φ_i+1 with the rotating angle phi _i+1 being the angle corresponding to the z axis);

The third revolving door R _Y(θ_i+1 with the rotation angle theta _i+1 being the angle corresponding to the y axis);

Target controlled unitary gates.

The auxiliary register acted by the i+1th layer in the target quantum circuit and the auxiliary register acted by the i layer in the L layer in the target quantum circuit are the same auxiliary register; the host register to which the i+1 layer in the target quantum circuit is applied is the same as the host register to which the i layer in the target quantum circuit is applied. That is, in practical application, the qubits in the preset parameterized quantum circuit may be first used as an auxiliary register, and after the main register is extended, the first turnstiles in each training layer in the preset parameterized quantum circuit are replaced with target controlled unitary gates, so that each layer shares the same auxiliary register and main register.

In this way, the scheme of the disclosure constructs the target quantum circuit based on the preset parameterized quantum circuit, the process is low in consumption, and the unitary operator can be controlled through the auxiliary register, so that the characteristic phase of the unitary operator is obtained through solving.

In a specific example of the present disclosure, the target controlled unitary door includes:

And (3) with An equivalent first controlled unitary gate;

And (3) with An equivalent second controlled unitary gate.

In a specific example, according to the order of action, the ith layer in the target quantum circuit includes:

The first controlled unitary gate;

the second controlled unitary gate.

Here, in practical application, when the quantum state of the auxiliary register is |0>, the hollow controlled unitary gate in the target quantum circuit is activatedI.e. the second controlled unitary gate. In the case of the quantum state of the auxiliary register being |1>, the controlled unitary gate with solid is activatedI.e. the first controlled unitary gate. That is, in practical applications, in the case of the current quantum state determination of the auxiliary register, the first controlled unitary gate operates, or the second controlled unitary gate operates, but not both.

In this way, the scheme can control the unitary operator through the auxiliary register, and further solve the characteristic phase of the unitary operator, and compared with the existing scheme, the scheme effectively reduces the required quantum computing resources, and enhances the feasibility of solving the quantum characteristics of the medium-scale quantum computing equipment.

Moreover, the disclosed scheme is applicable to any unitary operator, e.g., to any available preparationAnd thus has a rich application scenario.

In a specific example of the scheme of the disclosure, the target parameter value of the target adjustable parameter in the sub-circuit is obtained by training a preset parameterized quantum circuit in the following manner, and training to obtain the target parameter value of the target adjustable parameter; specifically, as shown in fig. 5, the method further includes:

Step S501: and under the condition that the rotation parameter x of the preset parameterized quantum circuit takes any one data point x _j of N data points, acquiring an actual output result y _j of the preset parameterized quantum circuit.

Here, the actual output result y _j is an output result of the preset parameterized quantum circuit, where the target adjustable parameter in the preset parameterized quantum circuit is at a current parameter value; and N is a positive integer greater than or equal to 1, and j is a positive integer greater than or equal to 1 and less than or equal to N.

Here, the value of N is related to the first error range.

Step S502: n actual output results y _j are obtained.

That is, in the case where j takes a value of 1 to N, N actual output results y _j can be obtained.

Step S503: determining whether an iteration termination condition is satisfied; in the case where it is determined that the iteration termination condition is satisfied, step S504 is performed; otherwise, step S505 is executed.

Here, the iteration termination condition includes at least one of:

Mode one: based on the N actual output results y _j and N target output results Determining that a loss value of a preset loss function meets a convergence condition; the target outputs a result

Mode two: the current iteration number reaches a preset number.

In practical application, as long as one of the above conditions is satisfied, the iteration termination condition may be satisfied.

Step S504: and taking the current parameter value of the target adjustable parameter as the target parameter value of the target adjustable parameter in the preset parameterized quantum circuit after training is completed.

Step S505: and adjusting the parameter value of the target adjustable parameter, and returning to the step S501 to acquire N actual output results y _j after parameter value adjustment again, and determining whether the iteration termination condition is met again until the iteration termination condition is met.

In a specific example, the objective function simulated by the disclosed scheme

It should be noted that, the scheme of the present disclosure is not particularly limited to f (x). For example, the simulated objective function f (x) may be transformed accordingly, e.gEtc., which may be collectively referred to herein asK is a real number of 1 or more. Further, inIn the case of (2), the expected value obtained isAt this time, the characteristic phase can be obtained through corresponding transformation, and then the characteristic value lambda of the unitary operator U is obtained.

Thus, the target parameter value of the target adjustable parameter of the sub-circuit is obtained by training other parameterized quantum circuits; here, because the preset parameterized quantum circuit has a simple circuit structure compared with the target quantum circuit, the calculation amount can be effectively reduced by training the preset parameterized quantum circuit to obtain the target parameter value of the target adjustable parameter, and a foundation is laid for efficiently solving and obtaining the characteristic phase of the unitary operator U.

Based on this, the disclosed solution has the following advantages:

The first, disclosed solution requires a smaller width of the target quantum circuit. Compared with the number of auxiliary quantum bits required by the existing scheme, the number of the auxiliary quantum bits in the target quantum circuit of the scheme can be one, so that compared with the existing scheme, the width of the target quantum circuit used by the scheme is minimum, thereby laying a foundation for effectively reducing the calculated amount and improving the processing efficiency, and meanwhile, the precision is high.

The second, this disclosed solution is easier to implement. The number and variety of quantum gates used in the subject quantum circuits of the present disclosure are fewer in the complexity and number of quantum gates than existing schemes, e.g., single-qubit controlled unitary gates, such as target controlled unitary gates equivalent to the square root of unitary operators, may be used, thus reducing the required quantum computing resources while increasing the feasibility of execution in a mid-scale quantum computing device.

Thirdly, the disclosed solution is more successful. In order to achieve the same success probability, compared with the prior art needing to add more auxiliary quantum bits or circuit depths, the cost of the target quantum circuit constructed by the scheme is smaller, namely, on the basis of the target quantum circuit constructed by the scheme, an estimated value meeting the precision requirement can be obtained with extremely high probability.

The following describes aspects of the present disclosure in further detail, with reference to specific examples; specifically, in this example, U represents a unitary operator of the target quantum system, and i ψ > represents a eigenvector, that is, a eigenvalue, of the unitary operator U to be solved, λ=e ^2πiα represents the eigenvalue of the unitary operator i ψ > to be solved, where α represents the eigenvalue, and based on this, the condition U i ψ > =λ|ψ > =e ^2πiα |ψ > is satisfied. At this time, the scheme of the present disclosure can: and inputting the target controlled unitary gate and a characteristic state |psi > of the unitary operator U, and outputting an estimated value of a characteristic value lambda (or a characteristic phase alpha) of the unitary operator U meeting the precision requirement.

In particular, the object of the disclosed solution is to provide a practical and efficient solution of quantum features, which is mainly divided into two parts, a first part, which simulates an objective function, such as an objective function, based on quantum signal processing or quantum neural networkFor example, a preset parameterized quantum circuit is constructed, and trained in an optimized manner, so that the preset parameterized quantum circuit can simulate an objective function f (x). The second part is a quantum feature solver that uses the target parameter values obtained in the first part to implement an arbitrary unitary operator.

Here, the disclosed scheme utilizes the quantum rotation gate sequence to simulate the capability of any square integrable function (i.e. f (x)), combines the extraction capability of fourier series on the characteristic phase, and obtains the characteristic phase of the unitary operator U efficiently by quantum measurement. See below for specific steps.

The first part, namely program one, is mainly used for calculating or optimizing target adjustable parameters of the revolving door on the auxiliary register; the first program is a subroutine that will be called by the main program.

Step 11: an error tolerance value (i.e., the first error range described above) e >0 is input.

Here, the error tolerance value e can constrain the degree of difference between the actual output result output by the preset parameterized quantum circuit for modeling the objective function f (x) and the target output result.

Step 12: constructing a preset parameterized quantum circuit to be trained, and determining the training layer number of the preset parameterized quantum circuit to be trained according to the error tolerance value epsilon, for example, the training layer number comprises L training layers; further, the number N of training data sets may also be determined based on the error tolerance value e. Here, L is a positive integer of 1 or more; and N is a positive integer greater than or equal to 1.

Here, in this example, the preset parameterized quantum circuit is a parameterized circuit including one qubit (which may be referred to as an auxiliary qubit or an auxiliary register in this example).

It should be noted that, in practical application, a preset parameterized quantum circuit including two or more quantum bits may be further configured to simulate the objective function f (x), which is not limited in the present disclosure, so long as the objective function can be simulated and the objective quantum circuit capable of solving the characteristic phase can be obtained by extension, and the preset parameterized quantum circuit is within the protection scope of the present disclosure.

In this example, each of the L training layers of the preset parameterized quantum circuit includes a quantum rotation gate sequence, and the quantum rotation gate sequences in each training layer are the same.

In practical application, the quantum rotation gate sequences contained in different training layers in the L training layers may be the same or different, or the quantum rotation gate sequences contained in some training layers are the same, or the quantum rotation gate sequences contained in other training layers are different, which is not a specific limitation in the scheme of the present disclosure.

Further, in this example, a quantum rotation gate sequence included in the ith training layer of the L training layers is described as an example. As shown in fig. 3 (a), based on the order of action of the rotation gates in the quantum rotation gate sequence, the quantum rotation gate sequence of the ith training layer sequentially includes:

Further, after the L training layers in the preset parameterized quantum circuit, other revolving gates are further included.

Specifically, in an example, as shown in fig. 3 (b), the preset parameterized quantum circuit further includes, after L training layers:

Or in another example, as shown in fig. 3 (c), the preset parameterized quantum circuit further includes, after L training layers:

The circuit configuration of each of the L training layers may be the configuration shown in fig. 3 (a), and is not shown in fig. 3 (b) and 3 (c).

It should be noted that, since the preset parameterized quantum circuit includes one quantum bit, the classical computing device can be used to effectively and accurately simulate the operation and the expected value of the preset parameterized quantum circuit, that is, the quantum computing resource is not required to be consumed, so that the quantum computing resource is saved, and meanwhile, the processing cost is reduced.

Further, it can be understood that in practical application, when the number of the qubits included in the preset parameterized quantum circuit is small (for example, 20-30 qubits), the target parameter value of the target adjustable parameter can be calculated in the classical computing device by means of an analog circuit, so that the consumption of the quantum computing resource is avoided to the greatest extent within the allowable range of the computing efficiency.

Step 13: preparing a training data set; for example, N training data points are preparedFor training the above-described pre-set parameterized quantum circuits.

This example is illustrated by taking a preset parameterized quantum circuit shown in fig. 3 (c) as an example, where the rotation angle α is a target adjustable parameter, and participates in a subsequent training process. Accordingly, fig. 4 (b) shows a schematic diagram of a target quantum circuit obtained based on the preset parameterized quantum circuit expansion shown in fig. 3 (c).

Step 14: randomly generating L+1 parameter values θ, and L+1 parameter values φ, and 1 parameter value α.

Here, the parameter values θ of L+1 can be respectively denoted as θ ₀ and θ(I is a positive integer of 1 or more and L or less). Here, for ease of recording, vectors may also be usedExpressed as θ= { θ ₀,θ₁,…,θ_i,…,θ_L }.

Similarly, the parameter values of L+1 areCan be respectively marked as phi ₀ and phi ₀ (I is a positive integer of 1 or more and L or less). Similarly, for ease of recording, the vector Φ may also be used to represent, i.e., Φ= { Φ ₀,φ₁,…,φ_i,…φ_L }.

At this time, the preset parameterized quantum circuit may be denoted as U _x (α, θ, Φ).

Step 15: for each rotation parameter x _j, 1.ltoreq.j.ltoreq.N, the following is performed:

(a) Simulating the above-described preset parameterized quantum circuit U _x (α, θ, Φ) containing single qubits using a classical simulator (i.e., on a classical computing device); furthermore, for each x _j, a predetermined parameterized quantum circuit is specifically obtained

(B) Inputting a preset initial state, such as |0>, using a classical simulator to simulate and acquire an expected value for the observables Z, namely obtaining an actual output result of the auxiliary register, and recording the actual output result as y _j.

After the above operation is performed for each x _j, i.e. after the above operation is completed, a set of actual output results are obtainedAnd N in total.

Step 16: will actually output the resultOutput result with targetThe 2-norm in between as a loss function, i.e. the loss function L (α, θ, Φ) is:

here, it is understood that, in practical application, the loss function may be any other metric function for characterizing the distance, for example, a common average absolute error function, a mean square error function, a cross entropy function, and the like. The appropriate loss function may be selected according to factors such as data size, hardware environment, learning accuracy, or convergence speed, which is not particularly limited in the scheme of the present disclosure.

Step 17: calculating a loss value based on the loss function L (alpha, theta, phi) and optimizing, such as by a gradient descent method, the target adjustable parameters alpha, theta and phi to minimize L (alpha, theta, phi);

wherein the target adjustable parameter θ includes θ ₀ and I.e., θ= { θ ₀,θ₁,…,θ_i,…,θ_L }, the target adjustable parameter φ includes φ ₀ andI.e., phi= { phi ₀,φ₁,…,φ_i,…φ_L }.

In practical application, a common gradient descent method can be used on classical computing equipment, and other more scientific and effective optimization methods can also be used, so that the target adjustable parameters alpha, theta ₀,Target adjustable parameters phi ₀ andOptimization is performed so as to minimize the loss value of the loss function, and the specific optimization mode is not limited by the scheme disclosed by the invention.

Step 18: after the target adjustable parameters are adjusted, repeating the steps 15-17 until the loss function L (alpha, theta, phi) converges or the iteration times are reached, and obtaining the optimal parameter values (namely target parameter values) of each target adjustable parameter, which are respectivelyAnd

Here the number of the elements is the number,

It will be appreciated that by repeating the above-described optimization process to minimize the loss value of the loss function, or to achieve a convergence state, or to achieve the number of iterations, the actual output result y _j may be considered to be close to the target output resultCurrent parameter value of target adjustable parameterAndAnd the optimal parameter value is obtained.

Step 19: outputting the optimal parameter value (i.e. the target parameter value),AndA total of 2l+3.

It will be appreciated that in practical applications, the program may be executed in a classical computing device or a quantum computing device without considering the computational cost, and the scheme of the present disclosure is not particularly limited thereto.

In practical applications, the implementation of the first procedure is not unique, for example, in the process of initializing the target adjustable parameters (for example, step 14), the intrinsic properties of the target adjustable parameters can be utilized, or the initial values thereof can be set, so as to improve the optimization efficiency; alternatively, the function analysis method may be used to directly obtain the optimal parameter value of the target adjustable parameter. In other words, in practical applications, an appropriate implementation may be selected based on factors such as a specific application scenario and hardware environment.

For example, the function analysis method is used to calculate the target adjustable angle, which specifically includes:

The input objective function f (x), which may be abbreviated as f. A target fourier series F (x) is calculated that approximates the target function F within the target definition domain. And calculating to obtain other Fourier series P (x) and Q (x); wherein,

The optimal parameter values for the target adjustable parameters α, θ and φ are recursively calculated according to the following equation:

Here, Q ^* (x) is the complex conjugate of Q (x), and P ^* (x) is the complex conjugate of P (x). Finally, outputting the optimal parameter value And

The second part, program two, is the main program, and is mainly used for solving the quantum characteristics of the unitary operator, such as characteristic values.

It can be appreciated that in practical applications, the second program may also be executed in a classical computing device or a quantum computing device without considering the computational cost, which is not particularly limited by the scheme of the present disclosure.

Specifically, as shown in fig. 6, the specific steps of the main program include:

Step 21: and expanding the preset parameterized quantum circuit into a target quantum circuit with n+1 quantum bits, so that the target quantum circuit can acquire the characteristic phase of the unitary operator U. Where the newly added or expanded n qubits are the primary qubits, which may be collectively referred to as the primary register.

That is, the target quantum circuit includes an auxiliary register and a main register; wherein the auxiliary register comprises an auxiliary qubit; the master register includes n master qubits. Here, n is determined based on the unitary operator U to be solved, for example, n is the number of quantum bits contained in the target quantum system represented by the unitary operator U to be solved. In other words, the number of main qubits contained in the main register is the same as the number of qubits contained in the target quantum system.

Specifically, the target quantum circuit is obtained by taking a quantum bit in the preset parameterized quantum circuit as an auxiliary register, expanding a main register, and replacing a first turnstile acting on the auxiliary register in the preset parameterized quantum circuit with the target controlled unitary gate.

Further, since the target quantum circuit is obtained by expanding on the basis of a preset parameterized quantum circuit, in the case that the preset parameterized quantum circuit includes L training layers, the target quantum circuit obtained by expanding also includes L layers.

In this example, the quantum bits included in the preset parameterized quantum circuit are used as an auxiliary register, and at the same time, a main register including n main quantum bits is extended, so that the first turngate R _Z(x_j in each training layer of the preset parameterized quantum circuit is replaced by a target controlled unitary gate, and the target quantum circuit is obtained. Specifically, as shown in fig. 4 (a), the i-th layer in the target quantum circuit specifically includes:

Target controlled unitary gates.

For ease of description, the relevant parameterized quantum circuits of the target quantum circuit that act on the auxiliary qubits may be referred to herein as sub-circuits of the target quantum circuit. It will be appreciated that the sub-circuit also includes an L layer. Further, as shown in fig. 4 (a), each layer in the sub-circuit includes a target adjustable parameter; taking the ith layer in the sub-circuit as an example, the method comprises the following steps:

The second rotating door R _Z(φ_i with the rotating angle phi _i being the angle corresponding to the z axis); and a third rotation door R _Y(θ_i having a rotation angle θ _i corresponding to the y-axis). Here, the rotation angle Φ _i and the rotation angle θ _i are target adjustable parameters.

Further, in this example, the target controlled unitary gate is controlled by the auxiliary register and acts on the main register to obtain the characteristic phase of the unitary operator.

Further, in this example, the target controlled unitary door specifically includes, in order of action:

And (3) with An equivalent first controlled unitary gate;

And (3) with An equivalent second controlled unitary gate.

For example, as shown in fig. 4 (a), after replacing the first rotating gate R _Z(x_j) in the ith training layer of the preset parameterized quantum circuit with the target controlled unitary gate, a schematic structural diagram of the ith layer in the target quantum circuit, that is, the ith layer in the target quantum circuit, sequentially includes, in order of action:

And (3) with An equivalent first controlled unitary gate; here, the first controlled unitary gate can be simply written as

And (3) withAn equivalent second controlled unitary gate; here, the second controlled unitary gate can be simply written as

It will be appreciated that since the target quantum circuit is extended on the basis of the preset parameterized quantum circuit, the target quantum circuit further includes other turnstiles after the L layers, similar to the preset parameterized quantum circuit.

Specifically, in an example, after the L layer in the target quantum circuit, a fourth rotating gate R _Z(φ₀) and a fifth rotating gate R _Y(θ₀ as shown in fig. 3 (b) are further included. Here, the rotation angle Φ ₀ and the rotation angle θ ₀ are both target adjustable parameters.

Or in another example, after the L layer in the target quantum circuit, a fourth rotating gate R _Z(φ₀) and a fifth rotating gate R _Y(θ₀) as shown in fig. 3 (c), and a sixth rotating gate R _Z (α) are further included. Here, the rotation angle Φ ₀ and the rotation angle θ ₀ are target adjustable parameters; and the rotation angle α is a fixed value. Or the rotation angle phi ₀, the rotation angle theta ₀ and the rotation angle alpha are all target adjustable parameters. The details can be found in the above statements and are not repeated here.

Step 22: the input error tolerance value e > 0, and the first input state of the auxiliary register is set to a preset initial state, such as |0> or |1>; the second input state of the main register is set to a eigenstate |ψ > of the unitary operator U.

Here, it can be understood that the first controlled unitary gate in the target quantum circuit isAs shown in fig. 4 (a), for convenience of description, the first controlled unitary gate may also use charactersAnd (3) representing. Further, the second controlled unitary gate in the target quantum circuit isIs transposed of (a)For convenience of description, the second controlled unitary gate may also use charactersAnd (3) representing.

Further, in a specific example, when the quantum state of the auxiliary register is |0>, the hollow controlled unitary gate in the target quantum circuit is activatedI.e. the second controlled unitary gate. In the case of the quantum state of the auxiliary register being |1>, the controlled unitary gate with solid is activatedI.e. the first controlled unitary gate. That is, in practical applications, in the case of the current quantum state determination of the auxiliary register, the first controlled unitary gate operates, or the second controlled unitary gate operates, but not both.

Step 23: inputting the error tolerance value epsilon into the program one, and running the program one to obtain the output optimal parameter value (namely the target parameter value): And

Here, i.e

Step 24: as shown in fig. 4 (b), the optimum parameter value is inputAndAnd a target quantum circuit for applying unitary operator U to n+1 quantum bits, i.e. to be connected withEquivalent first controlled unitary gate, andAn equivalent second controlled unitary gate acts on the target quantum circuit on n+1 quantum bits.

Step 25: obtaining observability of a target quantum circuitIs not shown, is a desired value 2 alpha of (a).

Here, α is a characteristic phase of unitary operator U. That is, the expected value is 2 times the characteristic phase of the unitary operator U.

Further, observableIn particular, the measurement operator Z acts on the auxiliary register, while the remaining qubits (i.e. the main register) are not operated, where I represents the identity matrix. Specifically, the expected value is obtained as follows:

(a) Setting the number of quantum measurements as

(B) Measuring an auxiliary register by using a Brix Z operator, and counting the occurrence times of 0 and 1;

(c) Based on the statistical result, calculating observability amount Is a desired value of (2):

Step 26: the eigenvalue λ=e ^2πiα of the unitary operator U is output.

Here, in practical application, if the characteristic state of the input unitary operator U is the ground state of the target quantum system, at this time, the characteristic value obtained by solving is the characteristic value corresponding to the ground state of the target quantum system.

In a specific example, the objective function simulated by the disclosed scheme

Case display

The following demonstrates the effect of the disclosed solution by way of one specific example. Here, a random quantum gate is selected as a unitary operator, and by running the scheme of the present disclosure, an estimated value of a characteristic phase of the unitary operator can be obtained. Specifically, the matrix expression of the random quantum gate (i.e., unitary operator U) is:

the matrix expression of one of the characteristic states |psi > of the random quantum gate is

Here, a target quantum circuit as shown in fig. 4 (b) is used, in which l=20 is set, and target parameter values, i.e., α, θ ₀,φ₀,AndCan be obtained by a first program; at this time, the error of-0.243660 in the true value (the true characteristic phase (i.e., the target value) corresponding to the characteristic state |ψ > estimated by the above procedure two is only 4.5x ^-5) is-0.243705.

In summary, the solution of the present disclosure can adapt to recent quantum computers, and has the following features:

first, the scheme of the disclosure can solve and obtain the characteristic phase of the unitary operator by using only one auxiliary quantum bit.

Second, the scheme of the disclosure can use a single auxiliary quantum bit to control the unitary operator, i.e. the characteristic phase of the unitary operator can be solved, thus reducing the required quantum computing resources and enhancing the feasibility of the medium-scale quantum computing equipment for solving the quantum characteristics.

Third, the disclosed scheme is applicable to any unitary operator, e.g., to any available preparationHas rich application scenes.

Fourth, the scheme of the present disclosure also has practicality, high efficiency, certainty, expansibility, innovation and reusability; specifically, practicality means that the disclosed solution can be implemented on a recent quantum computer without the need for quantum fourier transform or Block-encoding techniques; high efficiency means that the scheme of the disclosure can construct quantum circuits with low consumption and output estimated values with low consumption; certainty means that the scheme can obtain an estimated value meeting the precision requirement with extremely high probability; expansibility means that the scheme of the present disclosure can be applied to large-scale unitary operators; innovatively, the present disclosure provides novel quantum circuit implementations quantum phase estimation. The reusability refers to the characteristic state which does not consume the input, namely the output state of the target quantum system can be the same as the input characteristic state.

The present disclosure also provides a quantum computing device, as shown in fig. 7, comprising:

A parameter processing unit 701, configured to determine a target parameter value of a target adjustable parameter in a sub-circuit of the target quantum circuit within a first error range; the target quantum circuit comprises an auxiliary register and a main register, and the sub-circuit acts on the auxiliary register; the target quantum circuit also comprises a target controlled unitary gate which is controlled by the auxiliary register and acts on the main register, and the target controlled unitary gate is used for acquiring the characteristic phase of the unitary operator U; the unitary operator U represents the evolution characteristics of the target quantum system;

A measurement unit 702, configured to obtain state information of the auxiliary register in the target quantum circuit when the target adjustable parameter is the target parameter value, the first input state of the auxiliary register is a preset initial state, and the second input state of the main register is a characteristic state of the unitary operator U; and

An output unit 703, configured to estimate, based on the state information of the auxiliary register, a characteristic phase of the unitary operator U within the first error range.

In a specific example of the present disclosure, the output unit is further configured to:

and obtaining the characteristic value of the unitary operator U based on the characteristic phase of the unitary operator U.

In a specific example of the disclosure, the parameter processing unit is specifically configured to:

In the first error range, taking the target parameter value of the target adjustable parameter in the trained preset parameterized quantum circuit as the target parameter value of the target adjustable parameter in the sub-circuit;

The training-completed preset parameterized quantum circuit is used for simulating an objective function f (x); the target quantum circuit is obtained by taking a quantum bit in the preset parameterized quantum circuit as an auxiliary register, expanding a main register, and replacing a first rotating gate acting on the auxiliary register in the preset parameterized quantum circuit with the target controlled unitary gate; the rotation parameter of the first rotation door is an independent variable x of the objective function f (x); the sub-circuit comprises at least part of circuits except the first rotating gate in the preset parameterized quantum circuit.

In a specific example of the disclosure, the parameter processing unit is further configured to:

Acquiring an actual output result y _j of the preset parameterized quantum circuit under the condition that the rotation parameter x of the preset parameterized quantum circuit takes any one data point x _j of N data points; the actual output result y _j is an output result of the preset parameterized quantum circuit when the target adjustable parameter in the preset parameterized quantum circuit is at the current parameter value; the N is a positive integer greater than or equal to 1, and the j is a positive integer greater than or equal to 1 and less than or equal to N;

obtaining N actual output results y _j;

under the condition that the iteration termination condition is met, taking the current parameter value of the target adjustable parameter as the target parameter value of the target adjustable parameter in the preset parameterized quantum circuit after training is completed;

Wherein the iteration termination condition includes at least one of:

Based on the N actual output results y _j and N target output results Determining that a loss value of a preset loss function meets a convergence condition; the target outputs a result

The current iteration number reaches a preset number.

adjusting the parameter value of the target adjustable parameter under the condition that the iteration termination condition is not met;

Obtaining an actual output result y _j of the preset parameterized quantum circuit again under the condition that the rotation parameter x of the preset parameterized quantum circuit takes any one data point x _j of N data points;

And obtaining N actual output results y _j again until the iteration termination condition is met.

In a specific example of the disclosure, the preset parameterized quantum circuit includes L training layers; the value of L is related to the first error range;

at least one training layer of the L training layers comprises:

the first angle is an angle corresponding to the z-axis;

The second angle is an angle corresponding to the z-axis;

The third angle is an angle corresponding to the y axis.

And (3) with An equivalent first controlled unitary gate;

And (3) with An equivalent second controlled unitary gate.

Descriptions of specific functions and examples of each unit of the apparatus in the embodiments of the present disclosure may refer to related descriptions of corresponding steps in the foregoing method embodiments, which are not repeated herein.

The present disclosure also provides a non-transitory computer-readable storage medium storing computer instructions that, when executed by at least one quantum processing unit, cause the at least one quantum processing unit to perform the above method of applying a quantum computing device.

The present disclosure also provides a computer program product comprising a computer program which, when executed by at least one quantum processing unit, implements the method as described for application to a quantum computing device.

The present disclosure also provides a computing device comprising:

At least one quantum processing unit;

The instructions are executed by the at least one quantum processing unit to enable the at least one quantum processing unit to perform the method applied to the quantum computing device.

It will be appreciated that the quantum processing units (quantum processing unit, QPU), also referred to as quantum processors or quantum chips, used in the description of the present disclosure may refer to physical chips comprising a plurality of qubits interconnected in a particular manner.

Moreover, it is to be understood that the qubits described in the present disclosure may refer to the basic information units of a quantum computing device. Qubits are contained in QPUs and the concept of classical digital bits is generalized.

Further, in accordance with embodiments of the present disclosure, the present disclosure also provides a computing device, a readable storage medium, and a computer program product.

FIG. 8 illustrates a schematic block diagram of an example computing device 800 that may be used to implement embodiments of the present disclosure. Computing devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. Computing devices may also represent various forms of mobile apparatuses, such as personal digital assistants, cellular telephones, smartphones, wearable devices, and other similar computing apparatuses. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the disclosure described and/or claimed herein.

As shown in fig. 8, the apparatus 800 includes a computing unit 801 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 802 or a computer program loaded from a storage unit 808 into a Random Access Memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other by a bus 804. An input/output (I/O) interface 805 is also connected to the bus 804.

Various components in device 800 are connected to I/O interface 805, including: an input unit 806 such as a keyboard, mouse, etc.; an output unit 807 such as various types of displays, speakers, and the like; a storage unit 808, such as a magnetic disk, optical disk, etc.; and a communication unit 809, such as a network card, modem, wireless communication transceiver, or the like. The communication unit 809 allows the device 800 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.

The computing unit 801 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 801 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as quantum computing methods, for example, in some embodiments, the quantum computing methods may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program may be loaded and/or installed onto device 800 via ROM 802 and/or communication unit 809. When a computer program is loaded into RAM 803 and executed by computing unit 801, one or more steps of the quantum computing method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform the quantum computing method by any other suitable means (e.g., by means of firmware).

Various implementations of the systems and techniques described here above can be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), complex Programmable Logic Devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the internet.

The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server incorporating a blockchain.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel, sequentially, or in a different order, provided that the desired results of the disclosed aspects are achieved, and are not limited herein.

The above detailed description should not be taken as limiting the scope of the present disclosure. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.

Claims

1. A quantum computing method, comprising:

Determining a target parameter value of a target adjustable parameter in a sub-circuit of a target quantum circuit within a first error range; the first error range is a preset error tolerance value, and is used for constraining the precision of the target parameter value so as to constrain the obtained unitary operator The accuracy of the characteristic phase of (a); the target quantum circuit comprises an auxiliary register formed by one quantum bit and a main register formed by n quantum bits, and the sub circuit acts on the auxiliary register; the target quantum circuit also comprises a target controlled unitary gate which is controlled by the auxiliary register and acts on the main register, and the target controlled unitary gate is used for acquiring a unitary operatorIs a characteristic phase of (2); wherein the target controlled unitary door comprises a unitary body andEquivalent first controlled unitary gate, withAn equivalent second controlled unitary gate; the unitary operatorRepresenting evolution characteristics of a target quantum system; the number n of the quantum bits contained in the main register is the same as the number of the quantum bits contained in the target quantum system;

In the case that the target adjustable parameter is the target parameter value, the first input state of the auxiliary register is a preset initial state, and the second input state of the main register is the unitary operator Under the condition of the characteristic state of the auxiliary register, acquiring state information of the auxiliary register in the target quantum circuit; and

Estimating the unitary operator within the first error range based on the state information of the auxiliary registerIs a characteristic phase of (a) a (b).

2. The method of claim 1, further comprising:

Based on the unitary operator To obtain the eigenphase of the unitary operatorIs a characteristic value of (a).

3. The method of claim 1, wherein determining a target parameter value for a target tunable parameter in a sub-circuit of a target quantum circuit within a first error range comprises:

wherein the training-completed preset parameterized quantum circuit is used for simulating an objective function ; The target quantum circuit is obtained by taking a quantum bit in the preset parameterized quantum circuit as an auxiliary register, expanding a main register, and replacing a first rotating gate acting on the auxiliary register in the preset parameterized quantum circuit with the target controlled unitary gate; the rotation parameter of the first revolving door is the objective functionIndependent variable of (2); The sub-circuit comprises at least part of circuits except the first rotating gate in the preset parameterized quantum circuit.

4. A method according to claim 3, further comprising:

At the rotation parameters of the preset parameterized quantum circuit Take the value of any one of N data pointsUnder the condition of (1) obtaining the actual output result of the preset parameterized quantum circuit; The actual output resultThe output result of the preset parameterized quantum circuit is obtained when the target adjustable parameter in the preset parameterized quantum circuit is at the current parameter value; the N is a positive integer greater than or equal to 1, and the j is a positive integer greater than or equal to 1 and less than or equal to N;

obtaining N actual output results ；

Wherein the iteration termination condition includes at least one of:

based on the N actual output results Output results with N targetsDetermining that a loss value of a preset loss function meets a convergence condition; the target outputs a result；

The current iteration number reaches a preset number.

5. The method of claim 4, further comprising:

resetting the rotation parameters of the preset parameterized quantum circuit Take the value of any one of N data pointsUnder the condition of (1) obtaining the actual output result of the preset parameterized quantum circuit；

Obtaining N actual output results againUntil the iteration termination condition is satisfied.

6. The method of any of claims 3-5, wherein the pre-set parameterized quantum circuit comprises L training layers; the value of L is related to the first error range;

at least one training layer of the L training layers comprises:

the first revolving door, the revolving parameter For performing a rotation operation on the first angle;

Wherein the rotation angle of the second revolving door And the rotation angle of the third revolving doorParameters are adjustable for the target.

7. The method of claim 6, wherein each angle satisfies one of the following conditions:

the first angle is an angle corresponding to the z-axis;

The second angle is an angle corresponding to the z-axis;

The third angle is an angle corresponding to the y axis.

8. The method of claim 6, wherein,

Under the condition that at least one training layer of the L training layers comprises the first revolving door, the second revolving door and the third revolving door, the action sequence of the revolving doors is as follows:

9. The method of claim 6, wherein after the L training layers of the pre-set parameterized quantum circuit, further comprising additional turnstiles.

10. The method of claim 6, wherein the target quantum circuit comprises L layers, at least one of the L layers being a result of replacing a first rotation gate in a training layer with the target controlled unitary gate; the training layer is any training layer in L training layers.

11. A quantum computing device, comprising:

The parameter processing unit is used for determining a target parameter value of a target adjustable parameter in a sub-circuit of the target quantum circuit within a first error range; the first error range is a preset error tolerance value, and is used for constraining the precision of the target parameter value so as to constrain the obtained unitary operator The accuracy of the characteristic phase of (a); the target quantum circuit comprises an auxiliary register formed by one quantum bit and a main register formed by n quantum bits, and the sub circuit acts on the auxiliary register; the target quantum circuit also comprises a target controlled unitary gate which is controlled by the auxiliary register and acts on the main register, and the target controlled unitary gate is used for acquiring a unitary operatorIs a characteristic phase of (2); wherein the target controlled unitary door comprises a unitary body andEquivalent first controlled unitary gate, withAn equivalent second controlled unitary gate; the unitary operatorRepresenting evolution characteristics of a target quantum system; the number n of the quantum bits contained in the main register is the same as the number of the quantum bits contained in the target quantum system;

A measurement unit for determining the target adjustable parameter as the target parameter value, the first input state of the auxiliary register as the preset initial state, and the second input state of the main register as the unitary operator Under the condition of the characteristic state of the auxiliary register, acquiring state information of the auxiliary register in the target quantum circuit; and

An output unit for estimating the unitary operator within the first error range based on the state information of the auxiliary registerIs a characteristic phase of (a) a (b).

12. The apparatus of claim 11, wherein the output unit is further configured to:

13. The apparatus of claim 11, wherein the parameter processing unit is specifically configured to:

14. The apparatus of claim 13, wherein the parameter processing unit is further configured to:

obtaining N actual output results ；

Wherein the iteration termination condition includes at least one of:

The current iteration number reaches a preset number.

15. The apparatus of claim 14, wherein the parameter processing unit is further configured to:

16. The apparatus of any of claims 13-15, wherein the pre-set parameterized quantum circuit comprises L training layers; the value of L is related to the first error range;

at least one training layer of the L training layers comprises:

17. The apparatus of claim 16, wherein each angle satisfies one of the following conditions:

the first angle is an angle corresponding to the z-axis;

The second angle is an angle corresponding to the z-axis;

The third angle is an angle corresponding to the y axis.

18. The apparatus of claim 16, wherein,

19. The apparatus of claim 16, wherein after the L training layers of the pre-set parameterized quantum circuit, further comprising further turnstiles.

20. The apparatus of claim 16, wherein the target quantum circuit comprises L layers, at least one of the L layers being a result of replacing a first rotation gate in a training layer with the target controlled unitary gate; the training layer is any training layer in L training layers.

21. A computing device, comprising:

At least one quantum processing unit;

The instructions being executable by the at least one quantum processing unit to enable the at least one quantum processing unit to perform the method of any one of claims 1 to 10;

Or comprises:

At least one processor; and

A memory communicatively coupled to the at least one processor; wherein,

The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-10.

22. A non-transitory computer-readable storage medium storing computer instructions which, when executed by at least one quantum processing unit, cause the at least one quantum processing unit to perform the method of any one of claims 1 to 10;

or for causing the computer to perform the method according to any one of claims 1-10.

23. A computer program product comprising a computer program which, when executed by at least one quantum processing unit, implements the method according to any of claims 1-10;

Or the computer program when executed by a processor implements the method according to any of claims 1-10.