CN116107378A - Voltage source circuit - Google Patents

Voltage source circuit Download PDF

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Publication number
CN116107378A
CN116107378A CN202310257947.XA CN202310257947A CN116107378A CN 116107378 A CN116107378 A CN 116107378A CN 202310257947 A CN202310257947 A CN 202310257947A CN 116107378 A CN116107378 A CN 116107378A
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current
tube
source
nmos tube
electrode
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CN202310257947.XA
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周宁
陈涛
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Praran Semiconductor Shanghai Co ltd
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Praran Semiconductor Shanghai Co ltd
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Priority to CN202310257947.XA priority Critical patent/CN116107378A/en
Publication of CN116107378A publication Critical patent/CN116107378A/en
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Logic Circuits (AREA)

Abstract

The invention discloses a voltage source circuit, comprising: the first NMOS tube is connected with a first pull-down path between a source electrode and the ground, a grid electrode outputs a driving voltage, and the first pull-down path is provided with a plurality of MOS transistors connected with diodes; the grid electrode of the first NMOS tube is connected with the drain electrode and the first current source; and a driving tube composed of a second NMOS tube, wherein the grid electrode of the driving tube is connected with the driving voltage, the source electrode is an output end for outputting the voltage, and a second pull-down path which is mirror image with the first pull-down circuit is connected between the source electrode and the ground. A negative feedback path comprising: sampling tube for sampling source leakage current of driving tube; the first mirror circuit provides a second input current to be input to the drain electrode of the first NMOS tube; the source leakage current of the first NMOS tube is formed by superposition of the first input current and the second input current, when the load current is increased, the second input current is also increased, the driving voltage is increased, and the output voltage is prevented from being reduced. The invention can prevent the output voltage from decreasing with the increase of the load current.

Description

Voltage source circuit
Technical Field
The present invention relates to semiconductor integrated circuits, and more particularly to a voltage source circuit.
Background
As shown in fig. 1, a current I1 provided by a current source is shown in a conventional voltage source circuit diagram, the current source is connected to a supply voltage VCC, the current I1 flows through an NMOS transistor NM100, a PMOS transistor PM100, and an NMOS transistor NM102 and is grounded VSS, wherein the NMOS transistor NM100 is an intrinsic (active) NMOS transistor, and a clamp (clamp) voltage generated at a node ndr is vgs_n+vgs_p+vgs_nz.
Where vgs_n represents the gate-source voltage of the diode-connected NMOS transistor NM102, vgs_p represents the gate-source voltage of the diode-connected PMOS transistor PM100, and vgs_n represents the gate-source voltage of the diode-connected intrinsic NMOS transistor NM 100.
The NMOS transistor NM101 composed of native NMOS transistors is a driving transistor, the size of which will be generally large, the gate of the NMOS transistor NM103 is connected to the gate of the NMOS transistor NM102, that is, the node nbias, the NMOS transistor NM103 mirrors the current of the NMOS transistor NM102 as the internal load current of the NMOS transistor NM101, the generated output voltage VDD is vgs_n+vgs_p+vgs_nz-vgs_ nzp, and vgs_ nzp represents the gate-source voltage of the diode-connected intrinsic NMOS transistor NM101.
The voltage source shown in fig. 1 is an open loop structure, and when the output voltage VDD is heavy, i.e. the load current connected to the external load is large, the clamp voltage is used as the driving voltage to drive the NMOS NM101. Since the driving voltage at the node ndr is unchanged and the load current is larger, the NMOS transistor NM101 needs a larger Vgs, so the output voltage VDD is pulled down.
Disclosure of Invention
The invention aims to provide a voltage source circuit which can prevent the output voltage from decreasing along with the increase of load current.
In order to solve the above technical problems, the voltage source circuit provided by the present invention includes:
the first NMOS tube, be connected with the first pull-down route between source and the ground of first NMOS tube, the grid output drive voltage of first NMOS tube.
The first pull-down path has a plurality of diode-connected MOS transistors; the grid electrode of the first NMOS tube is connected with the drain electrode, the drain electrode of the first NMOS tube is connected with a first current source, and the first current source provides a first input current with a fixed size.
The grid electrode of the driving tube is connected with the driving voltage, and the source electrode of the driving tube is an output end for outputting the voltage; the drain electrode of the driving tube is connected with a power supply voltage; a second pull-down path is connected between the source electrode of the driving tube and the ground, and the second pull-down path and the first pull-down path are mirror images; the output voltage is used for providing an external load, and the source leakage current of the driving tube increases with the increase of the load current.
A negative feedback path comprising:
the sampling tube is characterized in that the source leakage current of the sampling tube is sampling current, and the sampling current is mirror current of the source leakage current of the driving tube.
The first mirror circuit provides a second input current which is the mirror current of the sampling current, and the second input current is input to the drain electrode of the first NMOS tube;
the source leakage current of the first NMOS tube is formed by superposition of the first input current and the second input current; when the load current increases, the second input current also increases, so that the source-drain current of the first NMOS transistor also increases and the gate-source voltage of the first NMOS transistor increases, thereby increasing the driving voltage output by the gate of the first NMOS transistor, thereby increasing the driving capability of the driving transistor, and preventing the output voltage from decreasing with the increase of the load current.
A further improvement is that the negative feedback path further comprises a second mirror circuit; the second mirror circuit provides a third extraction current, the third extraction current is a mirror current of the sampling current, and the third extraction current is connected to the source electrode of the first NMOS tube.
The first pull-down path comprises a fourth NMOS tube and a first PMOS tube.
The source electrode of the fourth NMOS tube is grounded, and the source electrode of the first PMOS tube is connected with the source electrode of the first NMOS tube.
And the grid electrode and the drain electrode of the fourth NMOS tube are connected with the grid electrode and the drain electrode of the first PMOS tube.
The second pull-down path comprises a fifth NMOS tube, wherein the source electrode of the fifth NMOS tube is grounded, and the drain electrode of the fifth NMOS tube is connected with the source electrode of the second NMOS tube;
and the grid electrode of the fifth NMOS tube is connected with the grid electrode of the fourth NMOS tube.
A further improvement is that the sampling tube comprises a third NMOS tube;
the source electrode of the third NMOS tube is connected with the source electrode of the second NMOS tube;
and the grid electrode of the third NMOS tube is connected with the grid electrode of the second NMOS tube.
The further improvement is that the first mirror circuit comprises a second PMOS tube and a third PMOS tube.
And the drain electrode and the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube are connected with the drain electrode of the third NMOS tube.
And the source electrode of the second PMOS tube and the source electrode of the third PMOS tube are both connected with a power supply voltage.
And the source electrode of the third PMOS tube is connected with the drain electrode of the first NMOS tube.
And the source leakage current of the second PMOS tube is equal to the sampling current, and the source leakage current of the third PMOS tube is the second input current.
The second mirror circuit comprises a fourth PMOS tube, a sixth NMOS tube and a seventh NMOS tube.
And the grid electrode of the fourth PMOS tube is connected with the grid electrode of the second PMOS tube.
And the source electrode of the fourth PMOS tube is connected with a power supply voltage.
The drain electrode of the fourth PMOS tube, the drain electrode and the grid electrode of the sixth NMOS tube and the grid electrode of the seventh NMOS tube are connected together.
And the source electrode of the sixth NMOS tube and the source electrode of the seventh NMOS tube are grounded.
And the drain electrode of the seventh NMOS tube is connected with the source electrode of the first NMOS tube.
And the source leakage current of the fourth PMOS tube is the mirror current of the sampling current and is equal to the source leakage current of the sixth NMOS tube.
The source drain current of the seventh NMOS transistor is the third pumping current and is the mirror current of the source drain current of the sixth NMOS transistor.
In a further improvement, the third extraction current is set to be smaller than or equal to the second input current, so that the current of the first pull-down path is larger than or equal to the first input current.
The further improvement is that a compensation capacitor is connected between the grid electrode of the second NMOS tube and the ground.
The second NMOS tube is an intrinsic NMOS tube.
The first NMOS tube is an intrinsic NMOS tube.
The channel size of the second NMOS tube is larger than that of the first NMOS tube.
Further, the output voltage is less than or equal to a few V.
A further improvement is that the maximum value of the load current amounts to hundreds of microamps.
The invention can adopt load current in real time by setting sampling tube to sample source leakage current of the driving tube, and the obtained sampling current is fed back to increase the driving voltage of the driving tube, after the driving voltage is increased, the source leakage current of the driving tube is determined by the difference between the driving voltage connected with the grid and the output voltage output by the source, namely the grid source voltage, so that the grid source voltage of the driving tube can be increased under the condition that the output voltage is not reduced after the driving voltage is increased, thereby realizing that the output voltage is not reduced when the load current is increased to increase the source leakage current of the driving tube, and the invention can prevent the output voltage from being reduced along with the increase of the load current, and improve the driving capability of the large load current.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIG. 1 is a circuit diagram of a prior art voltage source circuit;
FIG. 2 is a circuit diagram of a voltage source circuit according to an embodiment of the present invention;
fig. 3 is a graph showing output voltage versus load current for an embodiment of the present invention and a prior art voltage source circuit.
Detailed Description
FIG. 2 is a circuit diagram of a voltage source circuit according to an embodiment of the invention; the voltage source circuit of the embodiment of the invention comprises:
the first NMOS transistor NM0, a first pull-down path 102 is connected between a source of the first NMOS transistor NM0 and the ground VSS, and a gate of the first NMOS transistor NM0 outputs a driving voltage, and in fig. 2, a node outputting the driving voltage is a node ndr.
The first pull-down path 102 has a plurality of diode-connected MOS transistors; the gate of the first NMOS transistor NM0 is connected to the drain, the drain of the first NMOS transistor NM0 is connected to the first current source 106, and the first current source 106 provides a first input current I1 with a fixed magnitude.
In the embodiment of the present invention, the second NMOS transistor NM1 is an intrinsic NMOS transistor.
The first NMOS tube NM0 adopts an intrinsic NMOS tube.
The channel size of the second NMOS transistor NM1 is greater than the channel size of the first NMOS transistor NM0, for example, the channel width of the second NMOS transistor NM1 may be greater than the channel width of the first NMOS transistor NM0, the channel length of the second NMOS transistor NM1 may be greater than the channel length of the first NMOS transistor NM0, and the aspect ratio of the channel of the second NMOS transistor NM1 may be greater than the channel width-to-length ratio of the first NMOS transistor NM 0. In this way, the second NMOS transistor NM1 has stronger driving capability and can be adapted to driving a larger load current.
In some embodiments, the first pull-down path 102 includes a fourth NMOS transistor NM2 and a first PMOS transistor PM0.
The source electrode of the fourth NMOS tube NM2 is grounded to VSS, and the source electrode of the first PMOS tube PM0 is connected to the source electrode of the first NMOS tube NM 0.
The gate and the drain of the fourth NMOS transistor NM2 are connected to the gate and the drain of the first PMOS transistor PM0, and in fig. 2, the gate of the fourth NMOS transistor NM2 is a node nbias.
The grid electrode of the driving tube is connected with the driving voltage, and the source electrode of the driving tube is an output end for outputting the voltage VDD; the drain electrode of the driving tube is connected with a power supply voltage VCC; a second pull-down path 103 is connected between the source electrode of the driving tube and the ground VSS, and the second pull-down path 103 and the first pull-down path 102 are mirror images; the output voltage VDD is used to provide an external load, and the source-drain current of the driving tube increases with increasing load current.
In some embodiments, the second pull-down path 103 includes a fifth NMOS transistor NM3, a source of the fifth NMOS transistor NM3 is grounded VSS, and a drain of the fifth NMOS transistor NM3 is connected to a source of the second NMOS transistor NM 1.
The gate of the fifth NMOS transistor NM3 is connected to the gate of the fourth NMOS transistor NM 2.
A negative feedback path comprising:
the sampling tube 101, the source leakage current of the sampling tube 101 is sampling current, and the sampling current is mirror current of the source leakage current of the driving tube.
In the embodiment of the present invention, the sampling tube 101 includes a third NMOS tube NM4.
The source electrode of the third NMOS transistor NM4 is connected to the source electrode of the second NMOS transistor NM 1.
The gate of the third NMOS transistor NM4 is connected to the gate of the second NMOS transistor NM 1.
A first mirror circuit 104, where the first mirror circuit 104 provides a second input current, the second input current being a mirror current of the sampling current, and the second input current being input to the drain of the first NMOS transistor NM 0;
the source leakage current of the first NMOS NM0 is formed by overlapping the first input current I1 and the second input current; when the load current increases, the second input current also increases, so that the source drain current of the first NMOS transistor NM0 also increases and thus the gate source voltage of the first NMOS transistor NM0 increases, thereby increasing the driving voltage output from the gate of the first NMOS transistor NM0, thereby increasing the driving capability of the driving transistor, and preventing the output voltage VDD from decreasing with the increase of the load current.
In the embodiment of the present invention, the first mirror circuit 104 includes a second PMOS tube PM2 and a third PMOS tube PM1.
The drain and the gate of the second PMOS PM2 and the gate of the third PMOS PM1 are connected to the drain of the third NMOS NM4, i.e., the node pb.
The source of the second PMOS tube PM2 and the source of the third PMOS tube PM1 are both connected to the power supply voltage VCC.
And the source electrode of the third PMOS tube PM1 is connected with the drain electrode of the first NMOS tube NM 0.
The source-drain current of the second PMOS PM2 is equal to the sampling current, and the source-drain current of the third PMOS PM1 is the second input current.
In the embodiment of the present invention, the negative feedback path further includes a second mirror circuit 105; the second mirror circuit 105 provides a third extraction current, which is a mirror current of the sampling current, and is connected to the source of the first NMOS transistor NM 0.
The second mirror circuit 105 includes a fourth PMOS transistor PM3, a sixth NMOS transistor NM5, and a seventh NMOS transistor NM6.
And the grid electrode of the fourth PMOS tube PM3 is connected with the grid electrode of the second PMOS tube PM 2.
And the source electrode of the fourth PMOS tube PM3 is connected with a power supply voltage VCC.
The drain electrode of the fourth PMOS PM3, the drain electrode and the gate electrode of the sixth NMOS NM5, and the gate electrode of the seventh NMOS NM6, that is, the node nb, are connected together.
The source of the sixth NMOS transistor NM5 and the source of the seventh NMOS transistor NM6 are both grounded to VSS.
The drain electrode of the seventh NMOS transistor NM6 is connected to the source electrode of the first NMOS transistor NM0, i.e. the node vbias.
The source-drain current of the fourth PMOS PM3 is the mirror current of the sampling current and is equal to the source-drain current of the sixth NMOS NM 5.
The source drain current of the seventh NMOS transistor NM6 is the third extraction current and is the mirror current of the source drain current of the sixth NMOS transistor NM 5.
In some embodiments, a compensation capacitor Cc is connected between the gate of the second NMOS transistor NM1 and ground VSS.
In some embodiments, the third extraction current is set to be less than or equal to the second input current, so that the current of the first pull-down path 102 is greater than or equal to the first input current I1.
In fig. 2, the clamp voltage generated at node ndr is Vgs n + Vgs p + Vgs nz,
where vgs_n represents the gate-source voltage of the diode-connected NMOS transistor NM2, vgs_p represents the gate-source voltage of the diode-connected PMOS transistor PM0, and vgs_n represents the gate-source voltage of the diode-connected intrinsic NMOS transistor NM 0.
The magnitudes of vgs_n and vgs_p will be related to the current magnitude of the first pull-down path 102, and if the current magnitude of the first pull-down path 102 is unchanged or increases, the magnitudes of vgs_n and vgs_p will also be unchanged.
Vgs_nz is then related to the sum of said first input current I1 and said second input current, the larger the sum of said first input current I1 and said second input current is, the larger vgs_nz is.
Therefore, in the embodiment of the present invention, by providing the second input current, vgs_nz can be increased, and finally the clamp voltage generated at the node ndr, i.e., the driving voltage, can be increased.
Meanwhile, after the third extraction current is increased, the current of the first pull-down path 102 can be adjusted, so that the current of the first pull-down path 102 is unchanged, and the magnitudes of vgs_n and vgs_p are unchanged, so that the performance of the main circuit in fig. 2 after the negative feedback circuit is removed is kept consistent with the performance of the main circuit in fig. 1.
In some embodiments, the current of the first pull-down path 102 can be increased by adjusting the third extraction current, so that the driving voltage can be further increased, but since the mirror current is proportional, the current of the first pull-down path 102 increases to increase the current of the second pull-down path 103, so that the performance of the main circuit after the negative feedback circuit is removed in fig. 2 and the performance of the main circuit in fig. 1 are changed to some extent.
In some embodiments, the current of the first pull-down path 102 can also be reduced by adjusting the third extraction current, which is required to ensure that the driving voltage increases overall.
In the embodiment of the invention, the output voltage VDD is less than a few V.
The maximum value of the load current is hundreds of microamps.
According to the embodiment of the invention, the sampling tube 101 is arranged to sample the source leakage current of the driving tube so that the load current can be adopted in real time, the obtained sampling current is fed back to enable the driving voltage of the driving tube to be increased, after the driving voltage is increased, the source leakage current of the driving tube is determined by the difference between the driving voltage connected with the grid electrode and the output voltage VDD output by the source electrode, namely the grid source voltage, so that the grid source voltage of the driving tube can be increased under the condition that the output voltage VDD is not reduced after the driving voltage is increased, and the output voltage VDD is not reduced when the load current is increased so that the output voltage VDD is prevented from being reduced along with the increase of the load current, and the driving capability of the driving current with large load is improved.
As shown in fig. 3, the output voltage of the voltage source circuit according to the embodiment of the present invention and the output voltage of the existing voltage source circuit vary with the load current, the output voltage of the existing voltage source circuit varies with the load current, and the output voltage of the voltage source circuit according to the embodiment of the present invention varies with the load current, which is shown in fig. 201.
The abscissas of curves 201 and 202 are the same, the ordinate of curve 201 being in mV and the ordinate of curve 202 being in V. It can be seen that in curve 201, the output voltage VDD gradually decreases as the load current increases. In curve 202, when the load current is small, the output voltage VDD decreases to a minimum value, and then gradually increases as the load current increases.
As can be seen by comparing the data, the voltage source circuit of the embodiment of the invention has the minimum output voltage of 0.820V when the load is changed within the range of 0.1 uA-500 uA; the output voltage of the existing voltage source circuit is 0.470V at the lowest when the load is changed from 0.1uA to 500 uA.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims (14)

1. A voltage source circuit, comprising:
the first NMOS tube is connected with a first pull-down path between a source electrode and the ground, and a grid electrode of the first NMOS tube outputs a driving voltage;
the first pull-down path has a plurality of diode-connected MOS transistors; the grid electrode of the first NMOS tube is connected with the drain electrode, the drain electrode of the first NMOS tube is connected with a first current source, and the first current source provides a first input current with a fixed size;
the grid electrode of the driving tube is connected with the driving voltage, and the source electrode of the driving tube is an output end for outputting the voltage; the drain electrode of the driving tube is connected with a power supply voltage; a second pull-down path is connected between the source electrode of the driving tube and the ground, and the second pull-down path and the first pull-down path are mirror images; the output voltage is used for providing an external load, and the source leakage current of the driving tube increases along with the increase of the load current;
a negative feedback path comprising:
the sampling tube is used for sampling the source leakage current of the sampling tube, and the sampling current is the mirror current of the source leakage current of the driving tube;
the first mirror circuit provides a second input current which is the mirror current of the sampling current, and the second input current is input to the drain electrode of the first NMOS tube;
the source leakage current of the first NMOS tube is formed by superposition of the first input current and the second input current; when the load current increases, the second input current also increases, so that the source-drain current of the first NMOS transistor also increases and the gate-source voltage of the first NMOS transistor increases, thereby increasing the driving voltage output by the gate of the first NMOS transistor, thereby increasing the driving capability of the driving transistor, and preventing the output voltage from decreasing with the increase of the load current.
2. The voltage source circuit of claim 1, wherein: the negative feedback path further comprises a second mirror circuit; the second mirror circuit provides a third extraction current, the third extraction current is a mirror current of the sampling current, and the third extraction current is connected to the source electrode of the first NMOS tube.
3. The voltage source circuit of claim 2, wherein: the first pull-down path comprises a fourth NMOS tube and a first PMOS tube;
the source electrode of the fourth NMOS tube is grounded, and the source electrode of the first PMOS tube is connected with the source electrode of the first NMOS tube;
and the grid electrode and the drain electrode of the fourth NMOS tube are connected with the grid electrode and the drain electrode of the first PMOS tube.
4. A voltage supply circuit as claimed in claim 3, characterized in that: the second pull-down path comprises a fifth NMOS tube, the source electrode of the fifth NMOS tube is grounded, and the drain electrode of the fifth NMOS tube is connected with the source electrode of the second NMOS tube;
and the grid electrode of the fifth NMOS tube is connected with the grid electrode of the fourth NMOS tube.
5. The voltage source circuit of claim 2, wherein: the sampling tube comprises a third NMOS tube;
the source electrode of the third NMOS tube is connected with the source electrode of the second NMOS tube;
and the grid electrode of the third NMOS tube is connected with the grid electrode of the second NMOS tube.
6. The voltage source circuit of claim 5, wherein: the first mirror circuit comprises a second PMOS tube and a third PMOS tube;
the drain electrode and the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube are connected with the drain electrode of the third NMOS tube;
the source electrode of the second PMOS tube and the source electrode of the third PMOS tube are both connected with a power supply voltage;
the source electrode of the third PMOS tube is connected with the drain electrode of the first NMOS tube;
and the source leakage current of the second PMOS tube is equal to the sampling current, and the source leakage current of the third PMOS tube is the second input current.
7. The voltage source circuit of claim 6, wherein: the second mirror circuit comprises a fourth PMOS tube, a sixth NMOS tube and a seventh NMOS tube;
the grid electrode of the fourth PMOS tube is connected with the grid electrode of the second PMOS tube;
the source electrode of the fourth PMOS tube is connected with a power supply voltage;
the drain electrode of the fourth PMOS tube, the drain electrode and the grid electrode of the sixth NMOS tube and the grid electrode of the seventh NMOS tube are connected together;
the source electrode of the sixth NMOS tube and the source electrode of the seventh NMOS tube are grounded;
the drain electrode of the seventh NMOS tube is connected with the source electrode of the first NMOS tube;
the source leakage current of the fourth PMOS tube is the mirror current of the sampling current and is equal to the source leakage current of the sixth NMOS tube;
the source drain current of the seventh NMOS transistor is the third pumping current and is the mirror current of the source drain current of the sixth NMOS transistor.
8. A voltage supply circuit as claimed in claim 2 or 7, characterized in that: the third extraction current is set to be smaller than or equal to the second input current, so that the current of the first pull-down path is larger than or equal to the first input current.
9. A voltage supply circuit as claimed in claim 2 or 7, characterized in that: and a compensating capacitor is connected between the grid electrode of the second NMOS tube and the ground.
10. The voltage source circuit of claim 1, wherein: and the second NMOS tube adopts an intrinsic NMOS tube.
11. The voltage source circuit of claim 10, wherein: the first NMOS tube adopts an intrinsic NMOS tube.
12. The voltage source circuit of claim 11, wherein: and the channel size of the second NMOS tube is larger than that of the first NMOS tube.
13. The voltage source circuit of claim 1, wherein: the output voltage is less than or equal to a number V.
14. The voltage source circuit of claim 1, wherein: the maximum value of the load current is hundreds of microamps.
CN202310257947.XA 2023-03-16 2023-03-16 Voltage source circuit Pending CN116107378A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310257947.XA CN116107378A (en) 2023-03-16 2023-03-16 Voltage source circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310257947.XA CN116107378A (en) 2023-03-16 2023-03-16 Voltage source circuit

Publications (1)

Publication Number Publication Date
CN116107378A true CN116107378A (en) 2023-05-12

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310257947.XA Pending CN116107378A (en) 2023-03-16 2023-03-16 Voltage source circuit

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