CN116106654A

CN116106654A - Electronic system testing method

Info

Publication number: CN116106654A
Application number: CN202111334735.4A
Authority: CN
Inventors: 蔡涵昀; 王世宏; 吴亭莹
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2021-11-11
Filing date: 2021-11-11
Publication date: 2023-05-12

Abstract

The application discloses an electronic system testing method for testing a target electronic system, comprising the following steps: (a) Inputting a main test waveform to a main signal path of the target electronic system according to a test waveform combination comprising a plurality of test waveforms, and simultaneously inputting a sub-test waveform to at least one sub-signal path of the target electronic system respectively; (b) Obtaining a resulting waveform corresponding to step (a); (c) Changing the main test waveform or the auxiliary test waveform, and repeating the step (a) and the step (b) for a plurality of times until all the test waveforms of the test waveform combination are tested to obtain a plurality of result waveforms, and judging a combination level of the test waveform combination according to the result waveforms.

Description

Electronic system testing method

Technical Field

The present invention relates to an electronic system testing method, and more particularly, to an electronic system testing method capable of obtaining a desired test result with a relatively simple test waveform (test pattern) and testing a plurality of signal paths.

Background

In electronic system testing, an eye diagram (eye diagram) is typically used to determine whether the condition of the entire electronic system is good or bad. But such test methods typically require a test pattern of sufficient length to produce the desired eye pattern. For example, a pseudo-random number binary number array (Pseudo Randomness Binary Sequence; PRBS) is used, a conventional PRBS-7 signal having a length of at least 127 bits. Moreover, the electronic system test in the prior art generally only tests a single signal path, and does not consider crosstalk (Cross talk) caused by other signal paths in the vicinity.

Disclosure of Invention

An object of the present invention is to provide a method for testing an electronic system, which uses a test waveform with a smaller number of bits.

It is another object of the present invention to provide a test apparatus that uses a test waveform with a smaller number of bits.

An embodiment of the invention provides a method for testing an electronic system, which is used for testing a target electronic system and comprises the following steps: (a) Inputting a main test waveform to a main signal path of the target electronic system according to a test waveform combination comprising a plurality of test waveforms, and simultaneously inputting a sub-test waveform to at least one sub-signal path of the target electronic system respectively; (b) Obtaining a resulting waveform corresponding to step (a); (c) Changing the main test waveform or the auxiliary test waveform, and repeating the step (a) and the step (b) for a plurality of times until all the test waveforms of the test waveform combination are tested to obtain a plurality of result waveforms, and judging a combination level of the test waveform combination according to the result waveforms. The main test waveform is an X-bit waveform, the auxiliary test waveform is a Y-bit waveform, and X and Y are positive integers greater than or equal to 3. The electronic system testing method can be realized by a testing device.

According to the above embodiments, the number of bits of the test waveform can be reduced to reduce the data amount of the test process and the required test time. And in addition to problems that may arise from testing signal variations of a single signal path, other signal paths may have an impact on this signal path.

Drawings

FIG. 1 is a block diagram of a testing apparatus for testing a target electronic system according to an embodiment of the invention.

Fig. 2 is a flowchart illustrating a testing method of an electronic device according to an embodiment of the invention.

FIG. 3 is a more detailed flow chart of a testing method of an electronic device according to an embodiment of the invention.

FIG. 4 shows a testing apparatus according to an embodiment of the invention.

Symbol description:

101. target electronic system

103. Eye pattern generating device

105. Test device

401. Processing circuit

403. Storage device

AS1, AS2 secondary signal path

MS main signal path

Detailed Description

In the following, various embodiments of the present invention will be described with the further intention that the components of each embodiment may be implemented in hardware (e.g., devices or circuits) or in firmware (e.g., at least one program written in a microprocessor). Furthermore, the terms "first," "second," and the like in the following description are used merely to define different components, parameters, data, signals, or steps. And are not intended to limit the order in which they are presented.

FIG. 1 is a block diagram of a testing apparatus for testing a target electronic system according to an embodiment of the invention. AS shown in fig. 1, the target electronic system 101 may include at least one electronic device, and includes a main signal path MS and a plurality of sub signal paths (two sub signal paths AS1 and AS2 in the following embodiments, but not limited thereto). In one embodiment, the primary signal path MS and the secondary signal paths AS1 and AS2 are signal transmission lines of the target electronic system 101. During testing, a main test waveform MP is input to the main signal path MS of the target electronic system 101 according to a test waveform combination including a plurality of test waveforms, and sub-test waveforms AP1 and AP2 are input to the sub-signal paths AS1 and AS2 of the target electronic system 101 at the same time. The primary test waveform MP or the secondary test waveform AP1, AP2 may be generated by the test device 105 or by a device other than the test device 105. The main test waveform is an X-bit waveform, the auxiliary test waveform is a Y-bit waveform, X and Y are positive integers greater than or equal to 3, and X and Y can be the same positive integer or different positive integers. By inputting the test waveform to the main signal path MS and the plurality of sub signal paths AS1, AS2 at the same time, not only the influence of the test waveform on the main signal path MS but also the influence of the test waveform on the sub signal paths AS1, AS2 on the main signal path MS can be observed.

The target electronic system 101 generates a result waveform RW corresponding to the test waveforms including the different main test waveforms MP and the sub-test waveforms AP1, AP2. The eye pattern generating device 103 is configured to receive the result waveform RW and generate an eye pattern ED corresponding to the result waveform RW. In one embodiment, the eye pattern generating device 103 generates an eye pattern according to the result waveforms RW corresponding to all the test waveforms in the test waveform combination. The detailed steps will be described in detail in the following examples.

The test device 105 determines the combination level of the test waveform combinations according to the eye ED. Note also that in one embodiment, the determination of whether the eye ED is good or bad may also be determined visually by the tester, rather than being calculated by the testing device 105. The values of X and Y described above may be determined by the desired test data and the desired test time. The larger the values of X and Y, the more test data can be used to generate an eye pattern, and the more accurate the eye pattern is determined, however, the longer the test time is required. Conversely, the smaller the values of X and Y, the less test data corresponds, but the shorter the test time required. It should be noted that, in the embodiment of fig. 1, the combination level is determined by the eye pattern corresponding to the result waveform RW. However, the level of combination may also be determined by other parameters of the resulting waveform RW.

After obtaining the result waveforms RW corresponding to the main test waveform and the sub test waveform, the main test waveform or the sub test waveform is changed, and the steps are repeated to obtain a plurality of result waveforms RW until all the test waveforms in the test waveform combination are tested. For example, the test waveforms of the first input main test waveform and the auxiliary test waveform are (MP, AP1, AP 2), and the resulting waveform is RW1. In the next round of testing, the main test waveform and the sub-test waveform are changed to (MP, AP1, AP 3), and the resulting waveform RW2 is obtained. Then, in the next round of testing, the main test waveform and the sub-test waveform are changed to (MPa, AP1, AP 2), and the resulting waveform RW3 is obtained. Thus, after testing of the different test waveforms of the three main test waveforms and the sub test waveform, three resultant waveforms RW1, RW2, and RW3 can be obtained. An eye pattern is then generated with the resulting waveforms RW1, RW2 and RW3. The better the condition of the eye diagram, e.g., the clearer the eye diagram, the better the response of the representative target electronic system 101 to this combination of test waveforms.

The following table shows an example of a test waveform combination. It should be noted that these combinations are for example only, and the test waveforms may be set according to different requirements.

List one

In the test waveform combinations shown in Table one, 8 test waveforms are included, each of which includes a main test waveform MP and two auxiliary test waveforms AP1, AP2. The first test waveform input to the primary signal path MS and the secondary signal paths AS1, AS2 is test waveform 1. After the result waveform of the test waveform 1 is obtained, the test waveforms input to the main signal path MS and the sub signal paths AS1 and AS2 are switched to the test waveform 2. That is, the sub-test waveforms input to the sub-signal paths AS1 and AS2 are switched from 010 to 101, while the main test waveform input to the main signal path MS is maintained at 010, and the corresponding result waveforms are obtained. The rest of the test waveforms also follow the same rule until all 8 test waveforms are input

The plurality of test waveforms in table one follow at least one of the following rules, but is not limited thereto. In the embodiment of Table one, the same secondary test waveform is input to different secondary signal paths. In one embodiment, the primary and secondary test waveforms are identical, such as test waveform 1 and test waveform 4. According to Table one, the primary test waveform and the secondary test waveform each include one of the following values: 010. 101, 000 and 111. In detail, the main test waveform may include one of the following values: 010. 101, 000, and 111, and the sub-test waveform may include one of the following values: 010 and 101. And according to table one, the primary and secondary test waveforms do not contain values other than 010, 101, 000, and 111 in one embodiment.

As described above, the combination level can be determined according to the eye pattern. Thus, in one embodiment, the test waveforms include those primary and secondary test waveforms determined by the portion of the eye diagram to be observed. Taking table one as an example, if all eye patterns are to be observed, the target electronic system 101 is tested using all test waveforms 1 to 8. If only the internal boundaries of the eye diagram need be observed, then test waveforms 1-4 are used to test target electronic system 101. If the outer boundary of the eye diagram is to be observed, then test waveforms 6-8 are used to test target electronic system 101.

Note also that in the foregoing examples, only the main test waveform or the sub-test waveform is changed to perform a plurality of tests, and the configuration of the main signal path MS and the sub-signal paths AS1, AS2 is not changed. However, in another embodiment, the configuration of the main signal path MS and the sub signal paths AS1, AS2 may be changed to perform a plurality of tests. For example, one of the secondary signal paths AS1, AS2 may be selected AS the primary signal path, while the original primary signal path MS is selected AS the secondary signal path. Furthermore, the number of primary signal paths may be more than one, and the number of secondary signal paths is not limited to two.

In one embodiment, after testing a plurality of sets of test waveform combinations on the target electronic system 101 and obtaining a plurality of combination levels, it is determined whether the signal quality corresponding to the lowest combination level meets a predetermined standard (such as the minimum signal quality required by a circuit or device standard) to determine whether the target electronic system 101 can be used or needs to be adjusted. However, the plurality of combination levels are not limited to such an operation mode. For example, in one embodiment, preferred combination levels are selected from a plurality of combination levels, and the input signal to the target electronic system 101 is limited to the test waveform combinations corresponding to the preferred combination levels. Such variations and application variations are intended to be included within the scope of the present invention.

According to the foregoing embodiments, an electronic device testing method is provided for testing the signal quality of at least one output signal of a target electronic system (e.g., 101). FIG. 2 is a flowchart showing a testing method of an electronic device according to an embodiment of the invention, which comprises the following steps:

step 201

According to a test waveform combination including a plurality of test waveforms, a main test waveform (e.g. MP) is input to a main signal path (e.g. MS) of a target electronic system, and a sub-test waveform (e.g. AP1, AP 2) is input to at least one sub-signal path (e.g. AS1, AS 2) of the target electronic system.

The main test waveform is an X-bit waveform, the auxiliary test waveform is a Y-bit waveform, and X and Y are positive integers greater than or equal to 3.

Step 203

A resulting waveform corresponding to step 201 is obtained.

Step 205

Changing the main test waveform or the auxiliary test waveform, repeating the

steps

201 and 203 for a plurality of times until all the test waveforms of the test waveform combination are tested, and judging a combination level of the test waveform combination according to the result waveforms.

For example, as shown in the example of table one, the test waveform combination includes 8 test waveforms, and after the test of the 8 test waveforms is sequentially performed, 8 result waveforms can be obtained. An eye diagram is then generated based on these 8 resulting waveforms to obtain a combined level.

FIG. 3 is a more detailed flowchart of an electronic device testing method according to an embodiment of the invention, namely one example of the more detailed flowchart of the electronic device testing method shown in FIG. 2. The method for testing an electronic device shown in fig. 3 includes a first stage and a second stage, wherein the first stage includes steps 301-309 and the second stage includes step 311. Steps 301-311 comprise the steps of:

step 301

A test system architecture is established, i.e. it is set with which test system the target electronic system is to be tested. This step may include, but is not limited to: selecting a path to be tested, setting a system channel and setting a load component. The system channel is a transmission path of signals in the system, such as Netlist, S parameter, W-element, etc. And the load components may be IBIS, RLC components.

Step 303

A main test waveform is selected and input to the main signal path.

Step 305

A secondary test waveform is selected and input to the secondary signal path.

Step 307

An eye diagram is generated from the plurality of resulting waveforms.

Steps 303 through 307 may be operated in parallel to reduce test time. Taking table one as an example, 8 kinds of test waveforms can be simultaneously operated, and then the results thereof are combined.

Step 309

After repeated steps 303 to 307, the test waveform combination with the lowest combination level is found.

Step 311

And observing the system condition when the target electronic system uses the test waveform combination of the lowest combination level to judge whether the target electronic system needs to be adjusted.

The testing device 105 shown in fig. 1 may comprise a variety of structures. FIG. 4 shows a testing apparatus according to an embodiment of the invention. As shown in fig. 4, the test device 105 includes a processing circuit 401 and a storage device 403, the storage device 403 includes at least one program, and the processing circuit 401 is configured to execute the stored program to perform the above embodiments. Specifically, the processing circuit 401 may be used to calculate the combination level (e.g. eye pattern ED) in fig. 1, and control the test waveform generating device (not shown) to generate the required test waveform in response to the command of the tester or the automatic generation instruction. The test waveform generation device may be included in the test device 105 or located outside the test device 105. Moreover, the storage device 403 may also be located outside the testing device 105.

The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims

1. An electronic system testing method for testing a target electronic system, comprising:

(a) Inputting a main test waveform to a main signal path of the target electronic system according to a test waveform combination comprising a plurality of test waveforms, and simultaneously inputting a sub-test waveform to at least one sub-signal path of the target electronic system respectively;

(b) Obtaining a resulting waveform corresponding to step (a);

(c) Changing the main test waveform or the auxiliary test waveform, repeating the step (a) and the step (b) for a plurality of times until all the test waveforms of the test waveform combination are tested to obtain a plurality of result waveforms, and judging a combination level of the test waveform combination according to the result waveforms;

2. The electronic system testing method of claim 1, wherein step (a) inputs the same sub-test waveforms to different sub-signal paths.

3. The method of claim 2, wherein the primary test waveform and the secondary test waveform are identical.

4. The electronic system testing method of claim 1, wherein X and Y are each 3 and the number of secondary signal paths is 2.

5. The method of claim 4, wherein the main test waveform comprises one of the following values: 010. 101, 000 and 111.

6. The method of claim 5, wherein the primary test waveform and the secondary test waveform do not include values other than 010, 101, 000, and 111.

7. The method of claim 4, wherein the main test waveform comprises one of the following values: 010. 101, 000, and 111, and the sub-test waveform comprises one of the following values: 010 and 101.

8. The electronic system testing method of claim 7, wherein the primary test waveform and the secondary test waveform do not include values other than 010, 101, 000, and 111.

9. The method of claim 1, wherein step (c) generates an eye pattern according to the waveforms and determines the combination level according to the eye pattern.

10. The electronic system testing method of claim 1, further comprising:

generating a plurality of combination levels according to a plurality of the test waveform combinations;

and judging whether the target electronic system can be used or not or whether the target electronic system needs to be adjusted according to a plurality of result waveforms of the test waveform combination corresponding to the lowest combination level.