CN116105849A - MEMS piezoelectric vector hydrophone chip with double-mass cantilever beam structure and preparation method thereof - Google Patents

Abstract

The invention relates to a MEMS piezoelectric vector hydrophone chip with a double-mass cantilever beam structure and a preparation method thereof, wherein the vector hydrophone chip comprises: the device comprises an upper mass block, a lower mass block, a cantilever beam and a back-shaped substrate supporting structure; one end of the cantilever beam is connected with the inner wall of the back-shaped substrate supporting structure so as to fix the cantilever beam; the other end of the cantilever beam is suspended; the upper mass block and the lower mass block are symmetrically distributed on the upper side and the lower side of the suspension end of the cantilever beam; the piezoelectric sensing unit is positioned on the cantilever beam structure, can sense the stress change of the beam, and converts the stress change into an electric signal to realize acceleration electric measurement. The MEMS piezoelectric vector hydrophone provided by the invention is provided with the upper mass block above the cantilever beam to form a double-mass block structure which is vertically symmetrical, the sensitivity and directivity of the vector hydrophone can be obviously improved, the preparation process is relatively simple, a tiny air gap is not needed, and the MEMS piezoelectric vector hydrophone has the advantages of passive devices, stable work and low noise.

Description

MEMS piezoelectric vector hydrophone chip with double-mass cantilever beam structure and preparation method thereof

Technical Field

The invention relates to the technical field of sensing, in particular to a MEMS piezoelectric vector hydrophone chip with a double-mass cantilever beam structure and a preparation method thereof.

Background

Compared with a scalar hydrophone, the vector hydrophone can measure vector information of an underwater sound field, such as particle displacement, speed, acceleration and the like, and is beneficial to recognition of underwater long-distance and multi-target. The MEMS vector hydrophone can realize the miniaturization, low power consumption and low cost of the hydrophone, is easier to form an array, and is an important direction of the future development of the vector hydrophone. The vector hydrophone has natural 8-shaped (also called cosine-shaped or dipole-shaped) directivity, can suppress isotropic noise in the environment, and can realize localization of a sound source, so that the directivity is an important index of distinguishing the vector hydrophone from a scalar hydrophone.

In the prior art, the cantilever beam structure of the vector hydrophone commonly used single mass block has larger 8-shaped directivity, the current requirement on the hydrophone directivity cannot be met, and the research finds that the directivity is mainly caused by the asymmetry of a sensitive structure. Therefore, designing a MEMS piezoelectric vector hydrophone chip with good directivity and high sensitivity is a technical problem to be solved urgently.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides the MEMS piezoelectric vector hydrophone chip with the double-mass cantilever beam structure, which has the advantages of simple process, good directivity, high sensitivity, low noise, stable operation and no need of a tiny air gap, and the preparation method thereof. The invention provides a vertically symmetrical double-mass cantilever beam structure, which greatly improves the directivity of a hydrophone, and meanwhile, the addition of an upper mass block can also obviously improve the sensitivity of a device. However, the requirements on the preparation and the installation of the upper mass block are higher, and the directivity and the sensitivity of the hydrophone can be seriously reduced due to the deviation of the size or the position. The invention prepares the piezoelectric vector hydrophone chip with the upper mass block and the double-mass block cantilever beam structure by adopting the MEMS technology, and provides a detailed preparation method which is simple and easy to realize.

In order to achieve the above purpose, the present invention is realized by the following technical scheme.

The invention provides an MEMS piezoelectric vector hydrophone chip with a double-mass cantilever beam structure, which comprises: the device comprises an upper mass block, a lower mass block, a cantilever beam and a back-shaped substrate supporting structure; wherein,,

one end of the cantilever beam is connected with the inner wall of one side of the back-shaped substrate supporting structure so as to fix the cantilever beam; the other end of the cantilever beam is suspended in the air;

the upper mass block and the lower mass block are symmetrically distributed on the upper side and the lower side of the suspension end of the cantilever beam;

the other three side inner walls of the 'back' shaped substrate supporting structure, the upper mass block, the lower mass block and the cantilever beam form a U-shaped slit.

As one of the improvements of the technical scheme, the upper mass block and the lower mass block are etched, adhered or bonded to the same positions on the upper side and the lower side of the suspension end of the cantilever beam; the upper mass block and the lower mass block have the same mass.

As one of the improvements of the above technical solutions, the cantilever beam includes, from bottom to top, sequentially stacked: a composite layer and a piezoelectric sensing unit; wherein, the piezoelectricity sensing unit is from bottom to top including stacking gradually: a bottom electrode, a piezoelectric layer, and a top electrode.

As one of the improvements of the above technical solutions, the bottom electrode and the top electrode are aluminum, molybdenum, gold, chromium, platinum, titanium, or a composite film formed of at least two metals thereof;

the piezoelectric layer is a zinc oxide piezoelectric film, an aluminum nitride piezoelectric film, a lead zirconate titanate piezoelectric film, a PMN-PT piezoelectric film, a perovskite piezoelectric film, an organic piezoelectric film, a doped film formed by at least one piezoelectric film and a doping element, a composite film formed by at least two piezoelectric films, or a certain piezoelectric film or a composite film with an isolating layer arranged on the surface; the isolation layer is formed by a silicon nitride layer, a silicon dioxide layer, a polysilicon layer, a phosphosilicate glass layer or a composite film formed by at least two of the silicon nitride layer, the silicon dioxide layer, the polysilicon layer and the phosphosilicate glass layer;

the doping elements are vanadium, iron, chromium, manganese, samarium, indium, lanthanum, praseodymium, cobalt or niobium, and the practical application is not limited to the listed elements.

As one of the improvements of the technical scheme, the 'back' shaped substrate supporting structure comprises the following components stacked in sequence from bottom to top: a silicon substrate layer and a composite layer.

As one of the improvements of the above technical solutions, the composite layer comprises, from bottom to top, sequentially stacked: a silicon layer and an insulating layer.

As one of the improvements of the above technical scheme, the material of the insulating layer is a silicon dioxide layer, a silicon nitride layer, a polysilicon layer, a phosphosilicate glass layer or a composite layer formed by at least two of them.

The invention also provides a preparation method of the MEMS piezoelectric vector hydrophone chip with the double-mass cantilever beam structure, which comprises the following steps:

step 1, preparing a substrate;

step 2, preparing an insulating layer on the upper surface of the silicon wafer layer, and preparing a bulk silicon etching mask layer on the lower surface of the substrate;

step 3, depositing a bottom electrode film layer on the upper surface of the insulating layer, and patterning to form a bottom electrode;

step 4, depositing a piezoelectric layer film layer on the upper surface of the bottom electrode, and patterning to form a piezoelectric layer;

step 5, depositing a top electrode film layer on the upper surface of the piezoelectric layer, and patterning to form a top electrode;

step 6, preparing a mask for etching the U-shaped slit on the front surface of the substrate, patterning the mask to expose the pattern of the U-shaped slit to be etched, and respectively carrying out wet etching or dry etching on the insulating layer and the silicon wafer layer to form the U-shaped slit;

step 7, patterning the bulk silicon etching mask layer to obtain patterns required by the etched first etching cavity and the etched second etching cavity;

step 8, carrying out wet etching or dry etching on the bottom of the substrate to form a first etching cavity and a second etching cavity, and releasing the cantilever beam and the lower mass block; the first etching cavity is opposite to the piezoelectric sensing unit, and a lower mass block is formed between the first etching cavity and the second etching cavity; the piezoelectric sensing unit is formed by a bottom electrode, a piezoelectric layer and a top electrode;

And 9, preparing the upper mass block and determining the installation position: bonding or pasting the upper mass block on the corresponding position of the upper surface of the cantilever beam, and enabling the position of the upper mass block to be vertically symmetrical with that of the lower mass block, wherein the positions are opposite to each other, so that the integral gravity centers of the upper mass block and the lower mass block and the gravity center of the cantilever beam are located on the same horizontal plane, and a MEMS piezoelectric vector hydrophone chip with a double-mass-block cantilever beam structure is obtained;

the lower mass block is manufactured by etching, pasting or bonding.

As one of the improvements of the above technical solutions, in the step 1, an SOI substrate or a silicon substrate is used as a substrate; the SOI substrate comprises a plurality of SOI substrates sequentially stacked from top to bottom: a device silicon layer, an SOI buried oxide layer and a base silicon layer; the silicon substrate comprises the following components sequentially stacked from top to bottom: a device silicon layer and a base silicon layer;

the bulk silicon etching mask layer in the step 2 is a hard mask formed by a silicon dioxide layer, a silicon nitride layer, a polysilicon layer, a phosphosilicate glass layer, metallic aluminum, gold or a composite film formed by at least two materials, or a photoresist layer, or a composite mask layer formed by the hard mask and the photoresist layer;

when the SOI substrate is used as the substrate, in the step 8, wet etching or dry etching is performed on the base silicon layer and the SOI buried oxide layer of the SOI substrate from outside to inside;

When a silicon substrate is used as the substrate, in the step 8, a wet etching or a dry etching is performed on the base silicon layer of the silicon substrate.

As one of the improvements of the above technical solution, in order to ensure that the center of gravity of the whole upper and lower mass blocks and the center of gravity of the cantilever beam are located at the same horizontal plane, the step 9 specifically includes:

modeling the MEMS piezoelectric vector hydrophone chip of the double-mass cantilever beam structure through simulation software, and analyzing and optimizing the size and the placement position of the upper mass block according to the size and the position of the lower mass block so as to ensure that the gravity centers of the whole upper mass block and the whole lower mass block and the gravity center of the cantilever beam are positioned on the same horizontal plane;

preparing an upper mass block: designing a mask according to the optimized size of the upper mass block; a common silicon substrate with double-sided polishing is used as a substrate, a supporting layer is deposited, and thicker photoresist is coated on the surface of the supporting layer; patterning the other surface of the silicon substrate by using a mask plate, and carrying out wet etching or dry etching on bulk silicon; removing the photoresist and the supporting layer to obtain an upper mass block;

bonding or pasting the upper mass block on the optimized position on the cantilever beam, so that the position of the upper mass block is vertically symmetrical with that of the lower mass block, and the positions are opposite to each other, and the integral gravity centers of the upper mass block and the lower mass block are ensured to be positioned on the same horizontal plane with the gravity center of the cantilever beam;

Wherein the supporting layer is aluminum, gold, chromium, platinum, titanium, silicon dioxide, silicon nitride or a composite film formed by at least two of the above. Compared with the prior art, the invention has the advantages that:

1. compared with a cantilever beam structure of a single mass block, the double-mass block structure formed by stacking up and down can effectively improve directivity and sensitivity of a hydrophone, inhibit isotropic interference and better realize positioning of a target;

2. the preparation process is relatively simple, the upper mass block is accurately prepared and installed, the hydrophone chip does not need a tiny air gap, and the hydrophone chip has the advantages of being passive, stable in work and low in noise.

Drawings

FIG. 1 is a schematic diagram of a MEMS piezoelectric vector hydrophone according to an embodiment of the present invention;

FIG. 2 is a top view of a piezoelectric sensing chip of the MEMS piezoelectric vector hydrophone with the double-mass cantilever structure, which is provided by the embodiment of the invention;

FIG. 3 is a three-dimensional schematic diagram of a piezoelectric sensing chip of the MEMS piezoelectric vector hydrophone with a double-mass cantilever structure, which is provided by the embodiment of the invention;

FIG. 4 is a schematic cross-sectional view of an SOI substrate of a piezoelectric sensor chip;

FIG. 5 is a schematic cross-sectional view of a chip after the front and back silicon dioxide layers of an SOI substrate;

FIG. 6 is a schematic cross-sectional view of the chip after front side deposition of the bottom electrode, piezoelectric layer and top electrode;

FIG. 7 is a schematic cross-sectional view of a chip after U-shaped slit etching;

FIG. 8 is a schematic cross-sectional view of the chip after patterning the backside bulk etch mask;

FIG. 9 is a schematic cross-sectional view of a chip after bulk silicon etching (dry bulk etching is taken as an example);

FIG. 10 is a schematic cross-sectional view of a chip after SOI buried oxide layer etching (dry bulk etching is an example);

FIG. 11 is a schematic cross-sectional view of a piezoelectric sensor chip of an SOI silicon substrate after a mass block is attached to the front surface;

fig. 12 is a schematic structural diagram of a piezoelectric sensor chip of a silicon substrate after the completion of the preparation.

Drawing reference numerals

a. Piezoelectric sensing chip b, PCB (printed circuit board) c and packaging shell

1a, an upper mass 2a, a lower mass 3a, a cantilever beam

4a, "back" shaped substrate support structure 5a, U-shaped slit

1. Silicon layer 2, SOI buried oxide layer 3, silicon substrate layer

4. Insulating layer 5, bulk etching mask layer 6, bottom electrode

7. Piezoelectric layer 8, top electrode 9, photoresist layer

10. First etching chamber 11, second etching chamber

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The invention relates to a MEMS piezoelectric vector hydrophone with a double-mass cantilever beam structure, which comprises the following components: a plurality of piezoelectric sensing chips a, a plurality of corresponding PCB circuit boards b with impedance matching and amplification, and a packaging shell c; each piezoelectric sensing chip a is adhered and fixed on a PCB (printed circuit board) b, and is respectively and mutually vertically placed along an X axis, a Y axis and a Z axis of the packaging shell c, and is internally sealed;

each piezoelectric sensing chip a includes: an upper mass 1a, a lower mass 2a, a cantilever beam 3a and a "back" shaped base support structure 4a; one end of the cantilever beam 3a is connected with the inner wall of the 'back' base support structure 4a, and plays a role in fixing the cantilever beam 3 a; the other end of the cantilever beam 3a is suspended; the upper mass block 1a and the lower mass block 2a are symmetrically distributed on the upper side and the lower side of the suspension end of the cantilever beam 3 a; the other three side inner walls of the 'back' shaped substrate support structure 4a and the upper mass block 1a, the lower mass block 2a and the cantilever beam 3a form a U-shaped slit 5a; the package housing c is a metal housing such as aluminum, and can effectively shield electromagnetic interference.

The cantilever beam 3a comprises an upper mass block 1a and a lower mass block 2a, so that the directivity of the vector hydrophone can be effectively improved.

The working frequency range of the hydrophone is below 10 kHz;

etching the composite layer of the other three ends of the non-fixed end of the cantilever beam 3a by adopting an Inductively Coupled Plasma (ICP) etching method on the front surface of the substrate to form a U-shaped slit 5a, and laying a foundation for releasing the cantilever beam 3 a; the width of the U-shaped slit 5a is 0.01-2000 mu m; the size of the U-shaped slit 5a determines the length and width of the cantilever beam 3a structure;

preferably, when acceleration is input, the inertial force acts to enable the 'back' -shaped substrate supporting structure to move relative to the upper and lower double mass blocks, so that the cantilever beam is deformed. The piezoelectric unit on the cantilever beam generates electric charge due to the piezoelectric effect of the piezoelectric material, so that the acceleration can be electrically measured.

Preferably, the substrate thickness may be 10 to 5000 μm; the thickness of the SOI buried oxide layer is 0.01-100 mu m;

preferably, the insulating layer 4 may be a silicon oxide layer, a silicon nitride layer, a polysilicon layer, a phosphosilicate glass layer, or a composite layer formed of at least two thereof; the thickness of the insulating layer is 0.01-100 mu m.

Preferably, the bottom electrode and the top electrode may be aluminum, molybdenum, gold, chromium, platinum, titanium, or a composite film formed of at least two metals thereof; the thickness of the electrode is 1 nm-100 μm.

Preferably, the piezoelectric layer may be a zinc oxide piezoelectric film, an aluminum nitride piezoelectric film, a lead zirconate titanate piezoelectric film, a PMN-PT piezoelectric film, a perovskite type piezoelectric film, an organic piezoelectric film, or a doped film formed of at least one of the piezoelectric films and a doping element, or a composite film formed of at least two of the piezoelectric films, or a certain piezoelectric film or a composite film provided with an isolation layer on the surface; the isolation layer is formed by a silicon nitride layer, a silicon dioxide layer, a polysilicon layer, a phosphosilicate glass layer or a composite film formed by at least two of the silicon nitride layer, the silicon dioxide layer, the polysilicon layer and the phosphosilicate glass layer; the method comprises the steps of carrying out a first treatment on the surface of the The thickness of the piezoelectric layer is 0.01-600 mu m;

preferably, the doping element is vanadium, iron, chromium, manganese, samarium, indium, lanthanum, praseodymium, cobalt or niobium;

preferably, the body etching mask can be a hard mask formed by a silicon dioxide layer, a silicon nitride layer, a polysilicon layer, a phosphosilicate glass layer, metallic aluminum, gold or a composite layer formed by at least two of the silicon dioxide layer, the silicon nitride layer, the polysilicon layer, the phosphosilicate glass layer, the metallic aluminum, the gold or the composite mask layer formed by the hard mask and the photoresist layer; the thickness of the hard mask is 0.01 mu m-100 mu m; the thickness of the photoresist is 0.01 mu m to 100 mu m;

for the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

For the purpose of facilitating an understanding of embodiments of the present invention, reference will now be made in detail to the drawings.

Fig. 1 is a schematic structural diagram of a MEMS piezoelectric vector hydrophone according to an embodiment of the present invention, as shown in fig. 1, the piezoelectric vector hydrophone includes: a plurality of piezoelectric sensing chips a, a plurality of corresponding impedance matching and amplifying circuit boards b and a packaging shell c; each piezoelectric sensing chip a is adhered and welded on a PCB (printed circuit board) b, and is respectively and mutually vertically arranged along the X axis, the Y axis and the Z axis of the packaging shell c, and is internally sealed.

FIG. 2 is a top view of a piezoelectric sensing chip of the MEMS piezoelectric vector hydrophone with the double-mass cantilever structure, which is provided by the embodiment of the invention; FIG. 3 is a three-dimensional schematic diagram of a piezoelectric sensing chip of the MEMS piezoelectric vector hydrophone with a double-mass cantilever structure, which is provided by the embodiment of the invention; as shown in fig. 3, each piezoelectric sensor chip includes: an upper mass 1a, a lower mass 2a, a cantilever beam 3a and a "back" shaped base support structure 4a; one end of the cantilever beam 3a is connected with the inner wall of the 'back' base support structure 4a, and plays a role in fixing the cantilever beam 3 a; the other end of the cantilever beam 3a is suspended; the upper mass block 1a and the lower mass block 2a are symmetrically distributed on the upper side and the lower side of the suspension end of the cantilever beam 3 a; the other three side inner walls of the 'back' shaped substrate support structure 4a, the upper mass block 1a, the lower mass block 2a and the cantilever beam 3a form a U-shaped slit 5a; wherein the cantilever beam 3a comprises a composite layer and a piezoelectric layer, wherein the composite layer comprises a silicon layer 1 and an insulating layer 4; the piezoelectric unit comprises a piezoelectric layer 7, a top electrode 8 and a bottom electrode 6; the "back" shaped substrate support structure 4a comprises a composite layer and a silicon substrate layer 3; below the cantilever beam 3a corresponding to the piezoelectric layer is a first etching chamber 10. When acceleration is input, the inertial force acts on the back-shaped substrate support structure 4a and the upper and lower double mass blocks to generate relative motion, so that the cantilever beam 3a is deformed. The piezoelectric unit on the cantilever beam 3a generates electric charges due to the piezoelectric effect of the piezoelectric material, so that the acceleration can be electrically measured.

The working frequency range of the sensing chip is below 10 kHz. In addition, the sensing chip can keep higher sensitivity below 500Hz, and can be well applied.

The preparation method of the MEMS piezoelectric vector hydrophone is specifically described below with reference to examples 1-4 and the attached drawings.

Example 1

(1) Preparing a substrate SOI silicon wafer

The prepared SOI silicon chip is a no-clean substrate and can be directly used for experiments. Fig. 4 is a cross-sectional view of an SOI wafer of the piezoelectric sense die, as shown in fig. 3, the SOI wafer comprising: an SOI silicon wafer 1, an SOI buried oxide layer 2 and an SOI silicon substrate layer 3; the thickness of the SOI silicon wafer 1 is 50 μm; the thickness of the SOI buried oxide layer 2 is 3.5 μm; the thickness of the SOI silicon substrate layer 3 is 100 μm.

(2) Preparation of thermally oxidized silicon dioxide layer

A silicon dioxide layer with the thickness of 10 mu m is prepared on the upper surface of the SOI silicon wafer 1 and the lower surface of the SOI silicon substrate 3 by using a thermal oxidation furnace, the silicon dioxide layer on the upper surface of the SOI silicon wafer 1 is used as an insulating layer 4, and the silicon dioxide layer on the lower surface of the SOI silicon substrate 3 is used as one of the bulk silicon etching mask layers 5, as shown in FIG. 5.

(3) Preparation of bottom electrode 6

And depositing a platinum/titanium composite layer with the thickness of 0.5 mu m and the thickness of 0.1 mu m on the upper surface of the insulating layer 4 on the front surface of the SOI substrate by utilizing a magnetron sputtering method, and sequentially carrying out the processes of coating photoresist, exposing, developing, corroding the composite layer by corrosive liquid, removing the photoresist by acetone and the like to pattern the composite layer, thereby forming the bottom electrode 6.

(4) Preparation of piezoelectric layer 7

Preparing a zinc oxide piezoelectric layer with the thickness of 0.2 mu m on the upper surface of the bottom electrode 6 by utilizing a magnetron sputtering method, and sequentially coating photoresist, exposing, developing and phosphoric acid with the thickness of 1:10: the zinc oxide piezoelectric layer is patterned by the processes of corroding the zinc oxide piezoelectric layer by water corrosive liquid, removing photoresist by acetone and the like, so that the piezoelectric layer 7 is formed.

(5) Preparation of the top electrode 8 by a stripping process

And (3) coating photoresist on the front surface of the silicon substrate, exposing and developing, forming a reverse pattern of a top electrode on the photoresist, depositing a platinum/titanium composite layer with the thickness of 0.5 mu m and the thickness of 0.1 mu m by using a magnetron sputtering method, and finally removing the photoresist by using acetone to obtain the patterned top electrode 8.

Wherein, a bottom electrode 6, a piezoelectric layer 7 and a top electrode 8 are deposited on the front surface of the silicon substrate to form a piezoelectric unit, and the schematic cross-section of the chip is shown in fig. 6.

(6) Formation of U-shaped slit 5a

And (3) coating photoresist on the front surface of the SOI substrate, exposing and developing, exposing the pattern of the U-shaped slit to be etched on the photoresist, and respectively etching the insulating layer 4 and the SOI silicon wafer 1 by adopting an ICP etching method to form a U-shaped slit 5a with the width of 80 mu m, wherein the etched barrier layer is the SOI buried oxide layer 2, as shown in figure 7.

(7) Patterning of deep silicon etch masks

And depositing a silicon dioxide layer with the thickness of 10 mu m on the surface of the thermal oxidation silicon dioxide layer on the back surface of the SOI substrate by adopting a PECVD method, coating photoresist with the thickness of 100 mu m, exposing patterns of a first etching cavity 10 and a second etching cavity 11 to be etched on the photoresist after double-sided exposure and development of the photoresist, and etching the silicon dioxide layer and the thermal oxide layer under the photoresist by adopting ICP to form a deep silicon etched bulk silicon etching mask layer 5, as shown in figure 8.

(8) Releasing cantilever beam 3a and lower mass 2a

Deep silicon of the SOI silicon substrate layer 3 is etched by a Deep Reactive Ion Etching (DRIE) method, and after etching is completed, the SOI buried oxide layer 2 on the SOI silicon substrate layer 3 is etched by an ICP method to form a first etching cavity 10 and a second etching cavity 11, and the cantilever beam 3a and the lower mass block 2a are released. The first etching chamber 10 is opposite to the piezoelectric unit, and a lower mass 2a is formed between the first etching chamber 10 and the second etching chamber 11, as shown in fig. 9 and 10.

(9) Preparation of upper mass 1a

And analyzing and optimizing the size and the placement position of the upper mass block so as to ensure that the gravity centers of the upper mass block and the lower mass block are positioned on the same horizontal plane. Another common silicon substrate with two-sided polishing is adopted as a substrate, a metal aluminum film with the thickness of 2 mu m is sputtered as a supporting film, and photoresist with the thickness of 20 mu m is coated on the surface of the aluminum film; coating photoresist on the other surface of the silicon substrate, exposing and developing, patterning, and carrying out dry etching on bulk silicon; removing photoresist by adopting acetone and ethanol; the aluminum film was removed by wet etching to obtain an upper mass 1a.

(10) Bonded upper mass 1a

The upper mass block 1a is bonded at the optimized position on the upper surface of the cantilever beam 3a, so that the position of the upper mass block is vertically symmetrical with that of the lower mass block, and the positions of the upper mass block and the lower mass block are opposite, and the integral gravity center of the upper mass block and the integral gravity center of the cantilever beam are ensured to be positioned on the same horizontal plane, as shown in fig. 11.

Subsequently, the silicon wafer is cleaned and dried, and the preparation of the sensor chip is completed, as shown in fig. 11. The working frequency range of the sensing chip is below 10 KHz.

(11) Encapsulation of MEMS vector hydrophone

Fig. 11 is a schematic cross-sectional view of a piezoelectric sensor chip after fabrication is completed. After dicing the sensor chip, a single piezoelectric sensor chip a is formed, as shown in fig. 2. And (3) correspondingly connecting and pasting a plurality of piezoelectric sensing chips a on corresponding PCB circuit boards b by using voltage welding and epoxy resin adhesive, respectively placing the piezoelectric sensing chips in the aluminum shell along the X axis, the Y axis and the Z axis of the aluminum shell c in a mutually perpendicular manner, leading out leads, and sealing the outside of the packaging shell through epoxy resin, polyurethane and the like to finish the preparation of the MEMS vector hydrophone. The MEMS vector hydrophone structure provided in this embodiment is shown in fig. 1.

Example 2

(1) Preparation of silicon substrate

The prepared silicon substrate is a no-clean substrate and can be directly used for experiments. The silicon substrate includes: a silicon layer 1 and a silicon substrate layer 3; the thickness of the silicon layer 1 is 20 μm; the thickness of the silicon substrate layer 3 is 300 μm.

(2) Preparation of thermally oxidized silicon dioxide layer

And preparing a silicon dioxide layer with the thickness of 15 mu m on the upper surface of the silicon wafer 1 and the lower surface of the silicon substrate 3 by using a thermal oxidation furnace, wherein the silicon dioxide layer on the upper surface of the silicon wafer 1 is used as an insulating layer 4, and the silicon dioxide layer on the lower surface of the silicon substrate 3 is used as one of the bulk etching composite mask layers.

(3) Preparation of bottom electrode 6

And depositing a platinum/titanium composite layer with the thickness of 0.4 mu m and the thickness of 0.2 mu m on the upper surface of the insulating layer 4 on the front surface of the silicon substrate by utilizing a magnetron sputtering method, and sequentially carrying out processes of photoresist coating, exposure, development, etching the composite layer by corrosive liquid, photoresist removal by acetone and the like to pattern the composite layer, thereby forming the bottom electrode 6.

(4) Preparation of piezoelectric layer 7

An organic film layer with the thickness of 10 mu m is prepared on the upper surface of the bottom electrode 6 by a sol-gel method, and the processes of coating photoresist, exposing, developing, corroding the organic film layer by corrosive liquid, removing the photoresist by acetone and the like are sequentially carried out, so that the organic film layer is patterned, and the piezoelectric layer 7 is formed.

(5) Preparation of the top electrode 8 by a stripping process

And (3) coating photoresist on the front surface of the silicon substrate, exposing and developing, forming a reverse pattern of a top electrode on the photoresist, depositing a platinum/titanium composite layer with the thickness of 0.5 mu m and the thickness of 0.1 mu m by using a magnetron sputtering method, and finally removing the photoresist by using acetone to obtain the patterned top electrode 8.

Wherein, a bottom electrode 6, a piezoelectric layer 7 and a top electrode 8 are deposited on the front surface of the silicon substrate to form a piezoelectric unit.

(6) Formation of U-shaped slit 5a

And (3) coating photoresist on the front surface of the SOI substrate, exposing and developing, exposing the pattern of the U-shaped slit to be etched on the photoresist, and respectively etching the insulating layer 4 and the silicon wafer 1 by adopting an ICP etching method to form a U-shaped slit 5a with the width of 60 mu m.

(7) Patterning of deep silicon etch masks

And coating 100 mu m thick photoresist 9 on the surface of the bulk silicon etching mask layer 5 on the back surface of the silicon substrate to form a deep silicon etching composite mask layer, and respectively exposing and developing the deep silicon etching composite mask layer to obtain patterns required by the etched first etching cavity 10 and the etched second etching cavity 11.

(8) Releasing cantilever beam 3a and lower mass 2a

And etching the silicon substrate layer 3 by adopting a wet etching method to form a first etching cavity 10 and a second etching cavity 11, and releasing the cantilever beam 3a and the lower mass block 2a. The first etching chamber 10 is opposite to the piezoelectric unit, and a lower mass 2a is formed between the first etching chamber 10 and the second etching chamber 11.

(9) Preparation of upper mass 1a

And analyzing and optimizing the size and the placement position of the upper mass block so as to ensure that the gravity centers of the upper mass block and the lower mass block are positioned on the same horizontal plane. Another common silicon substrate with two-sided polishing is adopted as a substrate, a silicon dioxide film with the thickness of 2 mu m is sputtered as a supporting film, and photoresist with the thickness of 20 mu m is coated on the surface of the silicon dioxide film; coating photoresist on the other surface of the silicon substrate, exposing and developing, patterning, and carrying out dry etching on bulk silicon; removing photoresist by adopting acetone and ethanol; the silica film was removed by dry etching to obtain an upper mass 1a.

(10) Bonded upper mass 1a

The upper mass block 1a is bonded at the optimized position on the upper surface of the cantilever beam 3a, so that the position of the upper mass block is vertically symmetrical with that of the lower mass block, and the positions of the upper mass block and the lower mass block are opposite, and the integral gravity center of the upper mass block and the integral gravity center of the cantilever beam are located on the same horizontal plane.

Subsequently, the silicon wafer is cleaned and dried, and the preparation of the sensor chip is completed, as shown in fig. 12. The working frequency range of the sensing chip is below 10 KHz.

(11) Encapsulation of MEMS vector hydrophone

Fig. 12 is a schematic cross-sectional view of a piezoelectric sensor chip after fabrication is completed. After dicing the sensor chip, a single piezoelectric sensor chip a is formed, as shown in fig. 2. And (3) correspondingly connecting and pasting a plurality of piezoelectric sensing chips a on corresponding PCB circuit boards b by using voltage welding and epoxy resin adhesive, respectively placing the piezoelectric sensing chips in the aluminum shell along the X axis, the Y axis and the Z axis of the aluminum shell c in a mutually perpendicular manner, leading out leads, and sealing the outside of the packaging shell through epoxy resin, polyurethane and the like to finish the preparation of the MEMS vector hydrophone. The MEMS vector hydrophone structure provided in this embodiment is shown in fig. 1.

Example 3

(1) Preparing a substrate SOI silicon wafer

The prepared SOI silicon chip is a no-clean substrate and can be directly used for experiments. Fig. 4 is a cross-sectional view of an SOI wafer of the piezoelectric sense die, as shown in fig. 4, the SOI wafer comprising: an SOI silicon wafer 1, an SOI buried oxide layer 2 and an SOI silicon substrate layer 3; the thickness of the SOI silicon wafer 1 is 20 μm; the thickness of the SOI buried oxide layer 2 is 1 μm; the thickness of the SOI silicon substrate layer 3 is 200 μm.

(2) Preparation of thermally oxidized silicon dioxide layer

A silicon dioxide layer with the thickness of 3 mu m is prepared on the upper surface of the SOI silicon wafer 1 and the lower surface of the SOI silicon substrate 3 by using a thermal oxidation furnace, the silicon dioxide layer on the upper surface of the SOI silicon wafer 1 is used as an insulating layer 4, and the silicon dioxide layer on the lower surface of the SOI silicon substrate 3 is used as one of the bulk silicon etching mask layers 5, as shown in FIG. 5.

(3) Preparation of bottom electrode 6

And depositing a gold/chromium composite layer with the gold thickness of 0.05 mu m and the chromium thickness of 0.01 mu m on the upper surface of the insulating layer 4 on the front surface of the SOI substrate by utilizing a magnetron sputtering method, and sequentially carrying out the processes of coating photoresist, exposing, developing, corroding the composite layer by corrosive liquid, removing the photoresist by acetone and the like to pattern the composite layer, thereby forming the bottom electrode 6.

(4) Preparation of piezoelectric layer 7

A zinc oxide piezoelectric layer with the thickness of 1 mu m is prepared on the upper surface of the bottom electrode 6 by utilizing a magnetron sputtering method, and processes such as photoresist coating, exposure, development, photoresist removal by etching the zinc oxide piezoelectric layer by etching solution, and the like are sequentially carried out, so that the zinc oxide piezoelectric layer is patterned to form the piezoelectric layer 7.

(5) Preparation of the top electrode 8 by a stripping process

And (3) coating photoresist on the front surface of the silicon substrate, exposing and developing, forming a reverse pattern of the top electrode on the photoresist, depositing a gold/chromium composite layer with the gold thickness of 0.05 mu m and the chromium thickness of 0.01 mu m by using a magnetron sputtering method, and finally removing the photoresist by using acetone to obtain the patterned top electrode 8.

Wherein, a bottom electrode 6, a piezoelectric layer 7 and a top electrode 8 are deposited on the front surface of the silicon substrate to form a piezoelectric unit, and the schematic cross-section of the chip is shown in fig. 6.

(6) Formation of U-shaped slit 5a

And (3) coating photoresist on the front surface of the SOI substrate, exposing and developing, exposing the pattern of the U-shaped slit to be etched on the photoresist, and respectively etching the insulating layer 4 and the SOI silicon wafer 1 by adopting an ICP etching method to form a U-shaped slit 5a with the width of 10 mu m, wherein the etched barrier layer is the SOI buried oxide layer 2, as shown in figure 7.

(7) Patterning of deep silicon etch masks

And depositing a silicon dioxide layer with the thickness of 30 mu m on the surface of the thermal oxidation silicon dioxide layer on the back surface of the SOI substrate by adopting a PECVD method, coating photoresist with the thickness of 200 mu m, exposing patterns of a first etching cavity 10 and a second etching cavity 11 to be etched on the photoresist after double-sided exposure and development of the photoresist, and etching the silicon dioxide layer and the thermal oxide layer under the photoresist by adopting ICP to form a deep silicon etched bulk silicon etching mask layer 5, as shown in figure 8.

(8) Releasing cantilever beam 3a and lower mass 2a

Deep silicon of the SOI silicon substrate layer 3 is etched by a Deep Reactive Ion Etching (DRIE) method, and after etching is completed, the SOI buried oxide layer 2 on the SOI silicon substrate layer 3 is etched by an ICP method to form a first etching cavity 10 and a second etching cavity 11, and the cantilever beam 3a and the lower mass block 2a are released. The first etching chamber 10 is opposite to the piezoelectric unit, and a lower mass 2a is formed between the first etching chamber 10 and the second etching chamber 11, as shown in fig. 9 and 10.

(9) Preparation of upper mass 1a

And analyzing and optimizing the size and the placement position of the upper mass block so as to ensure that the gravity centers of the upper mass block and the lower mass block are positioned on the same horizontal plane. Sputtering a metal platinum film and a titanium film with the thickness of 2 mu m by using another common silicon substrate with double-sided polishing as a substrate, and coating photoresist with the thickness of 40 mu m on the surface of the platinum/titanium composite film; coating photoresist on the other surface of the silicon substrate, exposing and developing, patterning, and carrying out wet etching on bulk silicon; removing photoresist by adopting acetone and ethanol; the platinum/titanium composite film was removed by wet etching to obtain an upper mass 1a.

(10) To which mass 1a is attached

The upper mass block 1a is stuck to the optimized position on the upper surface of the cantilever beam 3a, so that the position of the upper mass block is vertically symmetrical with that of the lower mass block, and the positions of the upper mass block and the lower mass block are opposite, and the integral gravity center of the upper mass block and the integral gravity center of the cantilever beam are ensured to be positioned on the same horizontal plane, as shown in fig. 11.

Subsequently, the silicon wafer is cleaned and dried, and the preparation of the sensor chip is completed, as shown in fig. 11. The working frequency range of the sensing chip is below 10 KHz.

(11) Encapsulation of MEMS vector hydrophone

Fig. 11 is a schematic cross-sectional view of a piezoelectric sensor chip after fabrication is completed. After dicing the sensor chip, a single piezoelectric sensor chip a is formed, as shown in fig. 2. And (3) correspondingly connecting and pasting a plurality of piezoelectric sensing chips a on corresponding PCB circuit boards b by using voltage welding and epoxy resin adhesive, respectively placing the piezoelectric sensing chips in the aluminum shell along the X axis, the Y axis and the Z axis of the aluminum shell c in a mutually perpendicular manner, leading out leads, and sealing the outside of the packaging shell through epoxy resin, polyurethane and the like to finish the preparation of the MEMS vector hydrophone. The MEMS vector hydrophone structure provided in this embodiment is shown in fig. 1.

Example 4

1) Preparing a substrate SOI silicon wafer

The prepared SOI silicon chip is a no-clean substrate and can be directly used for experiments. Fig. 3 is a cross-sectional view of an SOI wafer of the piezoelectric sense die, as shown in fig. 4, the SOI wafer comprising: an SOI silicon wafer 1, an SOI buried oxide layer 2 and an SOI silicon substrate layer 3; the thickness of the SOI silicon wafer 1 is 40 μm; the thickness of the SOI buried oxide layer 2 is 5.5 μm; the thickness of the SOI silicon substrate layer 3 is 400 μm.

(2) Preparation of thermally oxidized silicon dioxide layer

A silicon dioxide layer with the thickness of 8 μm is prepared on the upper surface of the SOI silicon wafer 1 and the lower surface of the SOI silicon substrate 3 by using a thermal oxidation furnace, the silicon dioxide layer on the upper surface of the SOI silicon wafer 1 is used as an insulating layer 4, and the silicon dioxide layer on the lower surface of the SOI silicon substrate 3 is used as one of the bulk silicon etching mask layers 5, as shown in fig. 5.

(3) Preparation of bottom electrode 6

And depositing a platinum/titanium composite layer with the thickness of 0.2 mu m and the thickness of 0.05 mu m on the upper surface of the insulating layer 4 on the front surface of the SOI substrate by utilizing a magnetron sputtering method, and sequentially carrying out the processes of coating photoresist, exposing, developing, corroding the composite layer by corrosive liquid, removing the photoresist by acetone and the like to pattern the composite layer, thereby forming the bottom electrode 6.

(4) Preparation of piezoelectric layer 7

A perovskite film and zinc oxide film composite layer with the thickness of 25 mu m is prepared on the upper surface of the bottom electrode 6 by a sol-gel method, and the processes of photoresist coating, exposure, development, perovskite film corrosion by corrosive liquid, photoresist removal by acetone and the like are sequentially carried out, so that the perovskite film layer is patterned, and the piezoelectric layer 7 is formed.

(5) Preparation of the top electrode 8 by a stripping process

And (3) coating photoresist on the front surface of the silicon substrate, exposing and developing, forming a reverse pattern of a top electrode on the photoresist, depositing a platinum/titanium composite layer with the thickness of 0.2 mu m and the thickness of 0.05 mu m by using a magnetron sputtering method, and finally removing the photoresist by using acetone to obtain the patterned top electrode 8.

Wherein, a bottom electrode 6, a piezoelectric layer 7 and a top electrode 8 are deposited on the front surface of the silicon substrate to form a piezoelectric unit, and the schematic cross-section of the chip is shown in fig. 6.

(6) Formation of U-shaped slit 5a

And (3) coating photoresist on the front surface of the SOI substrate, exposing and developing, exposing the pattern of the U-shaped slit to be etched on the photoresist, and respectively etching the insulating layer 4 and the SOI silicon wafer 1 by adopting an ICP etching method to form a U-shaped slit 5a with the width of 20 mu m, wherein the etched barrier layer is the SOI buried oxide layer 2, as shown in figure 7.

(7) Patterning of deep silicon etch masks

And depositing a silicon dioxide layer with the thickness of 15 mu m on the surface of the thermal oxidation silicon dioxide layer on the back surface of the SOI substrate by adopting a PECVD method, coating photoresist with the thickness of 300 mu m, exposing patterns of a first etching cavity 10 and a second etching cavity 11 to be etched on the photoresist after double-sided exposure and development of the photoresist, and etching the silicon dioxide layer and the thermal oxide layer under the photoresist by adopting ICP to form a deep silicon etched bulk silicon etching mask layer 5, as shown in figure 8.

(8) Releasing cantilever beam 3a and lower mass 2a

Deep silicon of the SOI silicon substrate layer 3 is etched by a Deep Reactive Ion Etching (DRIE) method, and after etching is completed, the SOI buried oxide layer 2 on the SOI silicon substrate layer 3 is etched by an ICP method to form a first etching cavity 10 and a second etching cavity 11, and the cantilever beam 3a and the lower mass block 2a are released. The first etching chamber 10 is opposite to the piezoelectric unit, and a lower mass 2a is formed between the first etching chamber 10 and the second etching chamber 11, as shown in fig. 9 and 10.

(9) Preparation of upper mass 1a

And analyzing and optimizing the size and the placement position of the upper mass block so as to ensure that the gravity centers of the upper mass block and the lower mass block are positioned on the same horizontal plane. Sputtering a metal platinum film and a titanium film with the thickness of 2 mu m by using another common silicon substrate with double-sided polishing as a substrate, and coating photoresist with the thickness of 40 mu m on the surface of the platinum/titanium composite film; coating photoresist on the other surface of the silicon substrate, exposing and developing, patterning, and carrying out dry etching on bulk silicon; removing photoresist by adopting acetone and ethanol; the platinum/titanium composite film was removed by dry etching to obtain an upper mass 1a.

(10) To which mass 1a is attached

The upper mass block 1a is stuck to the optimized position on the upper surface of the cantilever beam 3a, so that the position of the upper mass block is vertically symmetrical with that of the lower mass block, and the positions of the upper mass block and the lower mass block are opposite, and the integral gravity center of the upper mass block and the integral gravity center of the cantilever beam are ensured to be positioned on the same horizontal plane, as shown in fig. 11.

Subsequently, the silicon wafer is cleaned and dried, and the preparation of the sensor chip is completed, as shown in fig. 11. The working frequency range of the sensing chip is below 10 KHz.

(11) Encapsulation of MEMS vector hydrophone

Fig. 11 is a schematic cross-sectional view of a piezoelectric sensor chip after fabrication is completed. After dicing the sensor chip, a single piezoelectric sensor chip a is formed, as shown in fig. 2. And (3) correspondingly connecting and pasting a plurality of piezoelectric sensing chips a on corresponding PCB circuit boards b by using voltage welding and epoxy resin adhesive, respectively placing the piezoelectric sensing chips in the aluminum shell along the X axis, the Y axis and the Z axis of the aluminum shell c in a mutually perpendicular manner, leading out leads, and sealing the outside of the packaging shell through epoxy resin, polyurethane and the like to finish the preparation of the MEMS vector hydrophone. The MEMS vector hydrophone structure provided in this embodiment is shown in fig. 1.

The piezoelectric layer materials used in the embodiments of the present invention, such as zinc oxide film, aluminum nitride film, lead zirconate titanate piezoelectric film, PMN-PT piezoelectric film, perovskite piezoelectric film, or organic piezoelectric film, and composite film layers thereof, may be interchanged.

The MEMS piezoelectric vector hydrophone with the double-mass cantilever structure comprises the steps of firstly, forming a composite vibrating membrane formed by a silicon layer and a thermal oxygen layer on the front surface of an SOI substrate or a silicon substrate, and then depositing a metal lower electrode, a piezoelectric layer and an upper electrode on the composite vibrating membrane in sequence; forming a U-shaped slit on the front surface of the substrate by etching a composite layer around the cantilever beam and the mass block, and laying a foundation for releasing the cantilever beam and the lower mass block; depositing a bulk silicon composite etching mask on the back surface of the substrate to form a bulk silicon etching mask; photoetching and etching a bulk etching mask layer on the back surface of the silicon substrate to form a mask pattern required by bulk etching; etching the bulk silicon to release the composite vibrating membrane and the lower mass block; and an upper mass block opposite to the lower mass block is stuck or bonded on the upper surface of the suspension end of the cantilever beam, so that the preparation of the sensing chip is completed. The device and the preparation method of the invention have the advantages of relatively simple preparation process, good directivity, high sensitivity, stable operation, low noise and no need of a tiny air gap.

After dicing the sensor chip, a single piezoelectric sensor chip is formed. And (3) correspondingly connecting and pasting a plurality of piezoelectric sensing chips on corresponding PCB circuit boards by using voltage welding and epoxy resin glue, respectively placing the piezoelectric sensing chips in the aluminum shell along the X axis, the Y axis and the Z axis of the aluminum shell in a mutually perpendicular manner, leading out leads, sealing the outside of the packaging shell through epoxy resin, polyurethane and the like, and thus completing the preparation of the MEMS vector hydrophone. Compared with the MEMS piezoresistive type MEMS piezoelectric vector hydrophone structure, the MEMS piezoelectric vector hydrophone structure prepared by the method provided by the embodiment of the invention has the advantages that the sensitivity can be obviously improved, the preparation process is relatively simple, meanwhile, a tiny air gap in the MEMS capacitive type vector hydrophone is not needed, the offset voltage is not needed during working, and the MEMS piezoelectric vector hydrophone structure is a passive device, so that the noise is very low. By adding the upper mass block above the cantilever beam to form a double-mass block structure which is vertically symmetrical, the vibration amplitude of the cantilever beam can be obviously improved, so that the piezoelectric material can generate more charges, and the sensitivity of the hydrophone can be obviously improved. Through the double mass block structure which is vertically symmetrical, the 8-shaped shape of the MEMS piezoelectric vector hydrophone is improved, and therefore the directivity of the device is improved.

The piezoelectric sensor chip provided by the embodiment of the invention is composed of an upper mass block, a lower mass block and a composite elastic cantilever beam formed by a piezoelectric layer and a silicon substrate layer. In the MEMS vector hydrophone, when inertial force acts, the piezoelectric cantilever beam deforms to enable the surface of the piezoelectric film to generate charges, and voltage signals are obtained after the charges are amplified by the amplifying circuit, so that the electric measurement of vector information in water can be realized.

Finally, it should be noted that the above embodiments are only for illustrating the technical solution of the present invention and are not limiting. Although the present invention has been described in detail with reference to the embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the present invention, which is intended to be covered by the appended claims.

Claims (10)

1. A MEMS piezoelectric vector hydrophone chip of a dual mass cantilever structure, wherein the chip (a) comprises: the device comprises an upper mass block (1 a), a lower mass block (2 a), a cantilever beam (3 a) and a back-shaped substrate supporting structure (4 a); wherein,,

one end of the cantilever beam (3 a) is connected with the inner wall of one side of the back-shaped substrate supporting structure (4 a) so as to fix the cantilever beam (3 a); the other end of the cantilever beam (3 a) is suspended in the air;

The upper mass block (1 a) and the lower mass block (2 a) are symmetrically distributed on the upper side and the lower side of the suspension end of the cantilever beam (3 a);

the other three side inner walls of the 'back' shaped substrate supporting structure (4 a) and the upper mass block (1 a), the lower mass block (2 a) and the cantilever beam (3 a) form a U-shaped slit (5 a).

2. The MEMS piezoelectric vector hydrophone chip of a double-mass cantilever structure according to claim 1, wherein the upper mass (1 a) and the lower mass (2 a) are etched, glued or bonded to the cantilever (3 a) at the same positions on the upper and lower sides of the suspended end; the upper mass (1 a) and the lower mass (2 a) have the same mass.

3. The MEMS piezoelectric vector hydrophone chip of a dual mass cantilever structure according to claim 1, wherein the cantilever (3 a) comprises, from bottom to top, sequentially stacked: a composite layer and a piezoelectric sensing unit; wherein, the piezoelectricity sensing unit is from bottom to top including stacking gradually: a bottom electrode (6), a piezoelectric layer (7) and a top electrode (8).

4. A MEMS piezoelectric vector hydrophone chip of a dual mass cantilever structure according to claim 3, characterized in that the bottom electrode (6) and the top electrode (8) are aluminum, molybdenum, gold, chromium, platinum, titanium, or a composite film formed of at least two of the metals;

The piezoelectric layer (7) is a zinc oxide piezoelectric film, an aluminum nitride piezoelectric film, a lead zirconate titanate piezoelectric film, a PMN-PT piezoelectric film, a perovskite piezoelectric film, an organic piezoelectric film, a doped film formed by at least one piezoelectric film and a doped element, a composite film formed by at least two piezoelectric films, or a certain piezoelectric film or a composite film with an isolation layer arranged on the surface; the isolation layer is composed of a silicon nitride layer, a silicon dioxide layer, a polysilicon layer, a phosphosilicate glass layer or a composite film formed by at least two of the silicon nitride layer, the silicon dioxide layer, the polysilicon layer and the phosphosilicate glass layer.

5. The MEMS piezoelectric vector hydrophone chip of a dual mass cantilever structure according to claim 1, wherein the "back" shaped base support structure (4 a) comprises, from bottom to top, sequentially stacked: a silicon substrate layer (3) and a composite layer.

6. The MEMS piezoelectric vector hydrophone chip of dual mass cantilever beam structure of claim 3 or 5, wherein the composite layer comprises, from bottom to top, sequentially stacked: a silicon layer (1) and an insulating layer (4).

7. The MEMS piezoelectric vector hydrophone chip of a double-mass cantilever structure according to claim 6, wherein the material of the insulating layer (4) is a silicon dioxide layer, a silicon nitride layer, a polysilicon layer, a phosphosilicate glass layer or a composite layer formed by at least two of them.

8. A preparation method of a MEMS piezoelectric vector hydrophone chip with a double-mass cantilever beam structure comprises the following steps:

step 1, preparing a substrate;

step 2, preparing an insulating layer (4) on the upper surface of the silicon wafer layer, and preparing a bulk silicon etching mask layer (5) on the lower surface of the substrate;

step 3, depositing a bottom electrode film layer on the upper surface of the insulating layer, and patterning to form a bottom electrode (6);

step 4, depositing a piezoelectric layer film layer on the upper surface of the bottom electrode, and patterning to form a piezoelectric layer (7);

step 5, depositing a top electrode film layer on the upper surface of the piezoelectric layer, and patterning to form a top electrode (8);

step 6, preparing a mask for etching the U-shaped slit on the front surface of the substrate, patterning the mask to expose the pattern of the U-shaped slit to be etched, and respectively carrying out wet etching or dry etching on the insulating layer and the silicon wafer layer to form a U-shaped slit (5 a);

step 7, patterning the bulk silicon etching mask layer to obtain patterns required by the etched first etching cavity (10) and the etched second etching cavity (11);

step 8, carrying out wet etching or dry etching on the bottom of the substrate to form a first etching cavity (10) and a second etching cavity (11), and releasing the cantilever beam (3 a) and the lower mass block (2 a); the first etching cavity (10) is opposite to the piezoelectric sensing unit, and a lower mass block (2 a) is formed between the first etching cavity (10) and the second etching cavity (11); the piezoelectric sensing unit is formed by a bottom electrode (6), a piezoelectric layer (7) and a top electrode (8);

Step 9, preparing the upper mass block (1 a) and determining the installation position: bonding or pasting an upper mass block (1 a) on a corresponding position on the upper surface of a cantilever beam (3 a), enabling the position of the upper mass block (1 a) and the position of a lower mass block (2 a) to be vertically symmetrical and opposite to each other, and ensuring that the integral gravity centers of the upper mass block and the lower mass block and the gravity center of the cantilever beam are positioned on the same horizontal plane to obtain an MEMS piezoelectric vector hydrophone chip with a double-mass-block cantilever beam structure;

the lower mass (2 a) is produced by etching, gluing or bonding.

9. The method for manufacturing the MEMS piezoelectric vector hydrophone chip with the double-mass cantilever structure according to claim 8, wherein the SOI substrate or the silicon substrate is adopted as the substrate in the step 1; the SOI substrate comprises a plurality of SOI substrates sequentially stacked from top to bottom: a device silicon layer, an SOI buried oxide layer and a base silicon layer; the silicon substrate comprises the following components sequentially stacked from top to bottom: a device silicon layer and a base silicon layer;

the bulk silicon etching mask layer in the step 2 is a hard mask formed by a silicon dioxide layer, a silicon nitride layer, a polysilicon layer, a phosphosilicate glass layer, metallic aluminum, gold or a composite film formed by at least two materials, or a photoresist layer (9), or a composite mask layer formed by the hard mask and the photoresist layer (9);

When the SOI substrate is used as the substrate, in the step 8, wet etching or dry etching is performed on the base silicon layer and the SOI buried oxide layer of the SOI substrate from outside to inside;

when a silicon substrate is used as the substrate, in the step 8, a wet etching or a dry etching is performed on the base silicon layer of the silicon substrate.

10. The method for manufacturing the MEMS piezoelectric vector hydrophone chip with the double-mass cantilever structure according to claim 8, wherein the step 9 specifically comprises:

modeling the MEMS piezoelectric vector hydrophone chip of the double-mass cantilever beam structure through simulation software, and analyzing and optimizing the size and the placement position of the upper mass block according to the size and the position of the lower mass block so as to ensure that the gravity centers of the whole upper mass block and the whole lower mass block and the gravity center of the cantilever beam are positioned on the same horizontal plane;

preparing an upper mass block: designing a mask according to the optimized size of the upper mass block; a common silicon substrate with double-sided polishing is used as a substrate, a supporting layer is deposited, and thicker photoresist is coated on the surface of the supporting layer; patterning the other surface of the silicon substrate by using a mask plate, and carrying out wet etching or dry etching on bulk silicon; removing the photoresist and the supporting layer to obtain an upper mass block;

Bonding or pasting the upper mass block on the optimized position on the cantilever beam, so that the position of the upper mass block is vertically symmetrical with that of the lower mass block, and the positions are opposite to each other, and the integral gravity centers of the upper mass block and the lower mass block are ensured to be positioned on the same horizontal plane with the gravity center of the cantilever beam;

wherein the supporting layer is aluminum, gold, chromium, platinum, titanium, silicon dioxide, silicon nitride or a composite film formed by at least two of the above.

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