CN116094884A

CN116094884A - HART signal processing method, device, equipment and storage medium

Info

Publication number: CN116094884A
Application number: CN202310103239.0A
Authority: CN
Inventors: 曹雅楠; 李宾; 闫丹
Original assignee: Hangzhou Hollysys Automation Co Ltd
Current assignee: Hangzhou Hollysys Automation Co Ltd
Priority date: 2023-02-01
Filing date: 2023-02-01
Publication date: 2023-05-09

Abstract

The application discloses a method, a device, equipment and a storage medium for processing HART signals, which relate to the field of information communication and comprise the following steps: judging whether a HART signal to be processed is received, if the HART signal to be processed is received, judging the type of the HART signal to be processed so as to generate a signal type judging result; if the HART signal to be processed is the signal to be modulated, analyzing the signal to be modulated by using an FPGA chip, sending the analyzed signal to a digital-to-analog converter for conversion, and processing the sine wave signal obtained after conversion by using a preset first processing rule to obtain a target modulation signal; if the HART signal to be processed is the signal to be demodulated, the signal to be demodulated is processed by using a preset second processing rule, the square wave signal obtained after the processing is sent to an FPGA chip, and the square wave signal is analyzed by using the FPGA chip to obtain the target demodulation signal. Thus, HART communication can be realized through a modem system designed based on an FPGA chip.

Description

HART signal processing method, device, equipment and storage medium

Technical Field

The present invention relates to the field of information communication, and in particular, to a method, an apparatus, a device, and a storage medium for processing HART signals.

Background

The HART (Highway Addressable Remote Transducer) communication is based on an open communication protocol of a high-speed channel of an addressable remote transducer, adopts a half-duplex communication mode, realizes digital signal communication on the existing analog signal transmission line, belongs to a transitional product in the conversion process from an analog system to a digital system, and can ensure the compatibility between signals and the analog system by adopting the HART communication.

In the prior art, the HART communication scheme is generally to adopt HART devices with functions of integrated filtering, signal detection, modulation, demodulation, waveform shaping of HART signals and the like, and peripheral devices are added to form an HART circuit together, so that the HART communication scheme is used in a field instrument and a controller supporting the HART protocol, most of the HART communication is realized by adopting an HART modem integrated chip, the requirements of the HART physical layer specification are met, and the peripheral addition of part of control circuits can be realized. However, the HART modem used in the prior art for implementing HART communication is too costly to be useful for large-scale applications.

Disclosure of Invention

Accordingly, the present invention is directed to a method, an apparatus, a device, and a storage medium for processing HART signals, which can realize HART signal modulation by using a modulation system designed based on an FPGA chip in a modulation and demodulation system designed based on an FPGA chip, and realize HART communication by using a demodulation system designed based on an FPGA chip, and can effectively control cost by using a modulation and demodulation system designed based on an FPGA chip, so as to realize large-scale application of HART communication. The specific scheme is as follows:

In a first aspect, the present application discloses a HART signal processing method, applied to a modem system, including:

judging whether a HART signal to be processed is received or not, and if the HART signal to be processed is received, judging the type of the HART signal to be processed so as to generate a signal type judging result;

if the signal type judgment result represents that the HART signal to be processed is a signal to be modulated, analyzing the signal to be modulated by using an FPGA chip, sending the analyzed signal to a digital-to-analog converter for conversion, and processing a sine wave signal obtained after conversion by using a preset first processing rule to obtain a target modulation signal;

if the signal type judging result represents that the HART signal to be processed is a signal to be demodulated, the signal to be demodulated is processed by using a preset second processing rule, the square wave signal obtained after the processing is sent to the FPGA chip, and the square wave signal is analyzed by using the FPGA chip to obtain a target demodulation signal.

Optionally, before the analyzing the signal to be modulated by using the FPGA chip, sending the signal after the analyzing to the digital-to-analog converter to perform conversion, and processing the sine wave signal obtained after the conversion by using a preset first processing rule to obtain the target modulation signal, the method further includes:

Judging whether a target communication instruction is received, and if the target communication instruction is received, generating a first data unit and a second data unit in the FPGA chip based on the target communication instruction; the first data unit is a data unit storing a signal with a first frequency, and the second data unit is a data unit storing a signal with a second frequency.

Optionally, the analyzing the signal to be modulated by using the FPGA chip, and sending the analyzed signal to a digital-to-analog converter for conversion, includes:

judging the frequency of the signal to be modulated, if the frequency of the signal to be modulated is the first frequency, storing the signal to be modulated into the first data unit, and if the frequency of the signal to be modulated is the second frequency, storing the signal to be modulated into the second data unit;

analyzing the signals to be modulated stored in the first data unit or the second data unit by utilizing the FPGA chip, and transmitting the analyzed signals to a digital-to-analog converter by utilizing a serial peripheral interface;

and converting the analyzed signal based on the digital-to-analog converter to obtain a sine wave signal corresponding to the analyzed signal.

Optionally, the parsing, by using the FPGA chip, the signal to be modulated stored in the first data unit or the second data unit includes:

and performing direct digital frequency synthesis analysis processing on the signals to be modulated stored in the first data unit or the second data unit by using the phase control word, the frequency control word, the phase accumulator and the waveform memory in the FPGA chip to obtain the analyzed signals.

Optionally, the processing the converted sine wave signal by using a preset first processing rule to obtain a target modulation signal includes:

and performing direct current blocking processing on the sine wave signal by using a preset direct current blocking capacitor, and performing voltage-reducing and current-expanding processing on the target direct current blocking signal obtained after direct current blocking to obtain a target modulation signal.

Optionally, the processing the signal to be demodulated by using a preset second processing rule, and sending the square wave signal obtained after the processing to the FPGA chip, includes:

and processing the signal to be demodulated by using the preset direct current blocking capacitor and the zero-crossing comparator to obtain the square wave signal, and sending the square wave signal to the FPGA chip.

Optionally, the analyzing the square wave signal by using the FPGA chip to obtain a target demodulation signal includes:

and detecting the high and low level width of the square wave signal, and performing width analysis on a target detection signal obtained after the high and low level width detection to obtain a target demodulation signal.

In a second aspect, the present application discloses a HART signal processing apparatus, applied to a modem system, including:

the signal judging module is used for judging whether a HART signal to be processed is received or not, and judging the type of the HART signal to be processed if the HART signal to be processed is received so as to generate a signal type judging result;

the signal modulation module is used for analyzing the to-be-modulated signal by using an FPGA chip if the signal type judgment result represents that the to-be-processed HART signal is the to-be-modulated signal, transmitting the analyzed signal to a digital-to-analog converter for conversion, and processing the sine wave signal obtained after conversion by using a preset first processing rule to obtain a target modulation signal;

and the signal demodulation module is used for processing the to-be-demodulated signal by using a preset second processing rule if the signal type judgment result represents that the to-be-processed HART signal is the to-be-demodulated signal, sending the square wave signal obtained after the processing to the FPGA chip, and analyzing the square wave signal by using the FPGA chip to obtain a target demodulation signal.

In a third aspect, the present application discloses an electronic device comprising:

a memory for storing a computer program;

and a processor for executing the computer program to implement the HART signal processing method as described above.

In a fourth aspect, the present application discloses a computer readable storage medium for storing a computer program which, when executed by a processor, implements a HART signal processing method as described above.

In the application, whether a HART signal to be processed is received needs to be judged first, if the HART signal is received, the type of the HART signal to be processed is judged to generate a signal type judging result, if the signal type judging result represents that the HART signal to be processed is a signal to be modulated, the signal to be modulated is analyzed by an FPGA chip, the analyzed signal is sent to a digital-to-analog converter to be converted, a sine wave signal obtained after conversion is processed by a preset first processing rule to obtain a target modulated signal, if the signal type judging result represents that the HART signal to be processed is a signal to be demodulated, the signal to be demodulated is processed by a preset second processing rule, and a square wave signal obtained after processing is sent to the FPGA chip, and the square wave signal is analyzed by the FPGA chip to obtain the target demodulated signal. Therefore, according to the HART signal processing method, when the HART signal to be processed is received, the type of the HART signal to be processed can be judged, and according to the type of the HART signal to be processed, the HART signal to be processed is subjected to corresponding modulation or demodulation processing by using a modulation and demodulation system designed based on an FPGA chip, so that the HART communication is realized by using the modulation and demodulation system designed based on the FPGA chip. Therefore, the HART communication is realized by using the modulation and demodulation system designed based on the FPGA chip, and the cost of the HART communication can be controlled by using the characteristic of lower cost of the FPGA chip, so that the large-scale application of the HART communication can be realized.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flowchart of a HART signal processing method provided in the present application;

fig. 2 is a timing chart of a HART modulation method provided in the present application;

fig. 3 is a timing chart of a HART demodulation method provided in the present application;

fig. 4 is a flowchart of a specific HART signal processing method provided in the present application;

fig. 5 is a schematic diagram of a HART signal provided in the present application;

FIG. 6 is a schematic diagram of a direct digital frequency synthesis provided herein;

fig. 7 is a schematic diagram of a HART modulation FPGA system provided in the present application;

fig. 8 is a flowchart of a specific HART signal processing method provided in the present application;

fig. 9 is a schematic diagram of a HART demodulation FPGA system provided in the present application;

fig. 10 is a schematic structural diagram of a HART signal processing device provided in the present application;

Fig. 11 is a block diagram of an electronic device provided in the present application.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In the prior art, the HART communication implementation scheme is generally to use HART devices with functions of integrated filtering, signal detection, modulation, demodulation, waveform shaping of HART signals and the like, and the HART devices are combined together to form a HART circuit, and most HART communication is realized by using a HART modem integrated chip, but the HART modem adopted in the prior art for realizing HART communication is too high in cost and is not beneficial to large-scale application.

In order to overcome the technical problems, the application provides a method, a device, equipment and a storage medium for processing HART signals, which can realize HART communication by utilizing a modulation and demodulation system based on the design of an FPGA chip and can control the cost of realizing the HART communication by utilizing the characteristic of lower cost of the FPGA chip so as to realize large-scale application of the HART communication.

Referring to fig. 1, an embodiment of the present invention discloses a HART signal processing method, which is applied to a modem system, and includes:

and S11, judging whether a HART signal to be processed is received, and if the HART signal to be processed is received, judging the type of the HART signal to be processed so as to generate a signal type judging result.

In this embodiment, it is determined whether a HART signal to be processed is received, and if the HART signal is received, the type of the HART signal to be processed is determined to generate a signal type determination result. That is, after the modem system built based on the FPGA chip starts to operate, it is required to determine whether the HART signal to be processed is received, if the HART signal to be processed is received, it is required to determine the signal type of the HART signal to determine whether the HART signal is a digital baseband signal to be modulated or a frequency band signal to be demodulated, and after the signal type of the HART signal is determined, a corresponding signal type determination result is generated based on the signal type of the HART signal, so that a corresponding modulation or demodulation operation is performed based on the signal type determination result.

In the HART communication implemented by the HART protocol, the HART protocol adopts FSK frequency shift keying signals based on the Bell202 standard, and audio digital signals with the amplitude of 0.5mA are superimposed on low-frequency 4mA to 20mA analog signals to carry out bidirectional digital communication, wherein the data transmission rate is 1200bps. Because the average value of the FSK signal is 0, the size of the analog signal transmitted to the control system is not affected, and the HART communication can coexist with 4-20 mA signals without mutual interference, thereby ensuring the compatibility with the existing analog system.

It should be further noted that, before processing the HART signal, the method further includes: judging whether a target communication instruction is received, and if the target communication instruction is received, generating a first data unit and a second data unit in the FPGA chip based on the target communication instruction; the first data unit is a data unit storing a signal with a first frequency, and the second data unit is a data unit storing a signal with a second frequency. That is, before the HART signal to be processed is modulated or demodulated, a first data unit and a second data unit for storing the signal need to be established according to the received communication finger, and the storage content of the first data unit is 16-bit code value information of 32 points in one period of the 1200Hz sine wave, and the storage content of the second data unit is 16-bit code value information of 32 points in one period of the 2200Hz sine wave.

And step S12, if the signal type judgment result represents that the HART signal to be processed is a signal to be modulated, analyzing the signal to be modulated by using an FPGA chip, sending the analyzed signal to a digital-to-analog converter for conversion, and processing the sine wave signal obtained after conversion by using a preset first processing rule to obtain a target modulation signal.

In this embodiment, the FPGA chip is used to parse the signal to be modulated, and the parsed signal is sent to the digital-to-analog converter to be converted, and the sine wave signal obtained after conversion is processed by using a preset first processing rule, so as to obtain the target modulation signal. That is, if the signal type determination result of the HART signal to be processed characterizes that the HART signal to be processed is a digital baseband signal to be modulated, as shown in fig. 2, the FPGA chip in the modulation system is used to analyze the signal to be modulated stored in the first data unit or the second data unit to obtain the analyzed signal, and then the analyzed signal is sent to the DAC (digital to analog converter) by using an SPI (Serial Peripheral Interface ) interface, so as to obtain a sine wave signal corresponding to the analyzed signal processed by the DAC digital to analog converter, and after the sine wave signal is obtained, the sine wave signal is subjected to dc-blocking, voltage-reducing and overcurrent operations, so as to obtain a modulated signal corresponding to the HART signal to be processed.

And S13, if the signal type judgment result represents that the HART signal to be processed is a signal to be demodulated, processing the signal to be demodulated by using a preset second processing rule, sending the square wave signal obtained after processing to the FPGA chip, and analyzing the square wave signal by using the FPGA chip to obtain a target demodulation signal.

In this embodiment, the signal to be demodulated is processed by using a preset second processing rule, the square wave signal obtained after the processing is sent to the FPGA chip, and the square wave signal is analyzed by using the FPGA chip, so as to obtain the target demodulation signal. That is, if the signal type judgment result of the HART signal to be processed indicates that the HART signal to be processed is a frequency band signal to be demodulated, as shown in fig. 3, the feedback signal responded by the HART instrument is subjected to dc blocking, the signal obtained after dc blocking is processed by using the zero-crossing comparator, so as to obtain a square wave signal corresponding to the HART signal to be processed, and after the square wave signal is obtained, the square wave signal is sent to the FPGA chip, so that the FPGA chip detects the high level and the low level of the square wave signal and performs width analysis to realize demodulation of the HART signal to be processed.

Therefore, in this embodiment, it is required to determine whether a HART signal to be processed is received, if the HART signal is received, determine the type of the HART signal to be processed to generate a signal type determination result, if the signal type determination result indicates that the HART signal to be processed is a signal to be modulated, parse the signal to be modulated by using an FPGA chip, send the parsed signal to a digital-to-analog converter to be converted, and process a sine wave signal obtained after conversion by using a preset first processing rule to obtain a target modulated signal, and if the signal type determination result indicates that the HART signal to be processed is a signal to be demodulated, process the signal to be demodulated by using a preset second processing rule, send the square wave signal obtained after processing to the FPGA chip, and parse the square wave signal by using the FPGA chip to obtain the target demodulated signal. Therefore, according to the HART signal processing method, when the HART signal to be processed is received, the type of the HART signal to be processed can be judged, and according to the type of the HART signal to be processed, the HART signal to be processed is subjected to corresponding modulation or demodulation processing by using a modulation and demodulation system designed based on an FPGA chip, so that the HART communication is realized by using the modulation and demodulation system designed based on the FPGA chip. Therefore, the HART communication is realized by using the modulation and demodulation system designed based on the FPGA chip, and the cost of the HART communication can be controlled by using the characteristic of lower cost of the FPGA chip, so that the large-scale application of the HART communication can be realized.

Based on the foregoing embodiment, after receiving a HART signal to be processed, the present application needs to determine that the HART signal needs to be modulated or demodulated according to the type of the HART signal, and the embodiment describes how to modulate the HART signal in detail, as shown in fig. 4, and the embodiment of the present invention discloses a HART signal processing method, which includes:

and S21, judging whether a HART signal to be processed is received, and if the HART signal to be processed is received, judging the type of the HART signal to be processed so as to generate a signal type judging result.

And S22, judging the frequency of the signal to be modulated if the signal type judging result represents that the signal to be processed HART is the signal to be modulated, storing the signal to be modulated into a first data unit if the frequency of the signal to be modulated is a first frequency, and storing the signal to be modulated into a second data unit if the frequency of the signal to be modulated is a second frequency.

In this embodiment, the frequency of the signal to be modulated is determined, if the frequency of the signal to be modulated is the first frequency, the signal to be modulated is stored in a first data unit, and if the frequency of the signal to be modulated is the second frequency, the signal to be modulated is stored in a second data unit. That is, when it is determined that the received HART signal to be processed is a digital baseband signal to be modulated, the frequency of the HART signal needs to be determined, and the HART is stored in a corresponding data unit according to the frequency of the HART, so that the HART signal stored in the data unit is modulated accordingly. For example, if the HART signal has a frequency of 1200Hz, the HART signal is stored to a first data unit for subsequent modulation of the signal in the first data unit, if the HART signal has a frequency of 2200Hz, the HART signal is stored to a second data unit for subsequent modulation of the signal in the second data unit, and it is to be noted that the 1200Hz signal represents a logic level "1" and the 2200Hz signal represents a logic level "0" as shown in fig. 5.

And S23, analyzing the signals to be modulated stored in the first data unit or the second data unit by using an FPGA chip, and transmitting the analyzed signals to a digital-to-analog converter by using a serial peripheral interface.

In this embodiment, a specific implementation manner of analyzing the signal to be modulated stored in the first data unit or the second data unit by using the FPGA chip is as follows: and performing direct digital frequency synthesis analysis processing on the signals to be modulated stored in the first data unit or the second data unit by using the phase control word, the frequency control word, the phase accumulator and the waveform memory in the FPGA chip to obtain the analyzed signals. That is, as shown in fig. 6, the DDS (Direct Digital Synthesis, direct digital frequency synthesis) is used in the FPGA chip to analyze the signal to be modulated stored in the first data unit or the second data unit, the phase control word, the frequency control word, the phase accumulator, and the waveform memory are used to analyze the signal to be modulated stored in the first data unit or the second data unit, the binary code stream "1" or "0" transmitted by the upper device is analyzed to obtain an analyzed signal, and then the analyzed signal is sent to the DAC digital-analog converter by using the SPI interface. The phase control word is used for controlling the initial position of the waveform, and the frequency control word is used for controlling the frequency of the generated waveform; the phase accumulator is used for controlling the phase accumulation of the waveforms to form complete waveform display, and controlling the waveform to be continuous; the waveform memory stores discrete signals of a periodic waveform.

And step S24, converting the analyzed signal based on the digital-to-analog converter to obtain a sine wave signal corresponding to the analyzed signal.

In this embodiment, the digital-to-analog converter is used to convert the parsed signal to obtain the sine wave signal corresponding to the parsed signal. That is, as shown in fig. 7, after the HART signal to be processed is parsed to obtain a parsed signal, the parsed signal needs to be sent to the DAC by using the SPI interface, so that the DAC performs digital-to-analog conversion on the parsed signal, and then outputs a sine wave signal with an amplitude of 2.5V and a frequency of 1200Hz or 2200 Hz.

And S25, performing direct current blocking processing on the sine wave signal by using a preset direct current blocking capacitor, and performing buck-spread processing on the target direct current blocking signal obtained after direct current blocking to obtain a target modulation signal.

In this embodiment, a preset dc blocking capacitor is used to perform dc blocking processing on the sine wave signal, and a step-down spreading processing is performed on a target dc blocking signal obtained after dc blocking, so as to obtain a target modulation signal. That is, after the DAC digital-to-analog converter performs digital-to-analog conversion on the analyzed signal to obtain a sine wave signal, a preset dc blocking capacitor is required to perform dc blocking and ac processing on the sine wave signal, and the sine wave signal is subjected to voltage-reducing and current-expanding processing, so as to completely realize the modulation of the HART signal to be processed, so as to obtain the target modulation signal.

It should be noted that, in this embodiment, the steps of step S21 may refer to the foregoing embodiments, and will not be described herein.

It can be seen that in this embodiment, whether a HART signal to be processed is received is first determined, if the HART signal is received, the type of the HART signal to be processed is determined to generate a signal type determination result, if the signal type determination result indicates that the HART signal to be processed is a signal to be modulated, the frequency of the signal to be modulated is determined, if the frequency of the signal to be modulated is a first frequency, the signal to be modulated is stored in a first data unit, and if the frequency of the signal to be modulated is a second frequency, the signal to be modulated is stored in a second data unit; and then analyzing the signal to be modulated stored in the first data unit or the second data unit by using an FPGA chip, sending the analyzed signal to a digital-to-analog converter by using a serial peripheral interface, finally converting the analyzed signal based on the digital-to-analog converter to obtain a sine wave signal corresponding to the analyzed signal, performing direct current blocking processing on the sine wave signal by using a preset direct current blocking capacitor, and performing voltage-reducing and current-expanding processing on the target direct current blocking signal obtained after direct current blocking to obtain a target modulation signal. In this way, the modulation of the HART signal can be realized through a modulation and demodulation system constructed based on the FPGA chip.

Based on the foregoing embodiment, after receiving a HART signal to be processed, the present application needs to determine that the HART signal needs to be modulated or demodulated according to the type of the HART signal, and the present embodiment describes how to demodulate the HART signal in detail, as shown in fig. 8, and the embodiment of the present invention discloses a HART signal processing method, which includes:

step S31, judging whether a HART signal to be processed is received, and if the HART signal is received, judging the type of the HART signal to be processed so as to generate a signal type judging result.

And S32, if the signal type judgment result represents that the HART signal to be processed is a signal to be demodulated, processing the signal to be demodulated by using a preset DC blocking capacitor and a zero-crossing comparator to obtain a square wave signal, and transmitting the square wave signal to the FPGA chip.

In this embodiment, the signal to be demodulated is processed by using a preset dc blocking capacitor and a zero-crossing comparator, so as to obtain a square wave signal, and the square wave signal is sent to the FPGA chip. That is, when it is determined that the received HART signal to be processed is a frequency band signal to be demodulated, after the HART instrument receives the HART signal to be processed, the HART signal to be processed is subjected to dc blocking and ac processing by using a preset dc blocking capacitor, an ac signal obtained by the sub-processing is converted by using a zero-crossing comparator, so as to obtain a square wave signal, and the square wave signal is sent to an FPGA chip for analysis. It should be noted that, the data of HART meter response is a sine wave with the frequency of 80mV to 120mV being 1200Hz or 2200Hz, the data of HART meter response cannot directly enter into the FPGA chip, and the data needs to be converted into logic "high" and "low" level by the zero comparator, and the FPGA chip judges the binary code value of HART response data according to the acquired pulse width of "high" and "low" level.

And step S33, detecting the high and low level width of the square wave signal, and performing width analysis on the target detection signal obtained after the high and low level width detection to obtain a target demodulation signal.

In this embodiment, the square wave signal is detected in high-low level width, and the target detection signal obtained after the detection in high-low level width is subjected to width analysis, so as to obtain a target demodulation signal. That is, after the FPGA chip receives the square wave signal sent by the zero-crossing comparator, as shown in fig. 9, it is necessary to detect the width of the high level and the low level of the square wave signal, and analyze the width of the high level and the low level of the square wave signal, so as to analyze the HART signal from the HART instrument. The high level width is within the range 417us + -20 us and represents "0", and the high level width is within the range 227us + -20 us and represents "1", after the width analysis operation is completed, to obtain the target demodulation signal.

It should be noted that, in this embodiment, the steps of step S31 may refer to the foregoing embodiments, and will not be described herein.

It can be seen that in this embodiment, whether a HART signal to be processed is received is first determined, if the HART signal is received, the type of the HART signal to be processed is determined to generate a signal type determination result, if the signal type determination result indicates that the HART signal to be processed is a signal to be demodulated, the signal to be demodulated is processed by using a preset dc blocking capacitor and a zero-crossing comparator to obtain a square wave signal, the square wave signal is sent to the FPGA chip, finally, the square wave signal is detected in high-low level width, and a target detection signal obtained after the high-low level width detection is analyzed in width to obtain a target demodulation signal. In this way, the demodulation of the HART signal can be realized through a modem system constructed based on the FPGA chip.

Referring to fig. 10, an embodiment of the present invention discloses a HART signal processing device, which is applied to a modem system, and includes:

the signal judging module 11 is configured to judge whether a HART signal to be processed is received, and if the HART signal is received, judge the type of the HART signal to be processed, so as to generate a signal type judging result;

the signal modulation module 12 is configured to parse the to-be-modulated signal by using an FPGA chip if the signal type determination result indicates that the to-be-processed HART signal is the to-be-modulated signal, send the parsed signal to a digital-to-analog converter for conversion, and process the sine wave signal obtained after conversion by using a preset first processing rule to obtain a target modulated signal;

and the signal demodulation module 13 is configured to process the to-be-demodulated signal by using a preset second processing rule if the signal type judgment result indicates that the to-be-processed HART signal is the to-be-demodulated signal, send the processed square wave signal to the FPGA chip, and analyze the square wave signal by using the FPGA chip to obtain the target demodulation signal.

In some embodiments, the HART signal processing apparatus may further include:

the data unit generation module is used for judging whether a target communication instruction is received, and if the target communication instruction is received, generating a first data unit and a second data unit in the FPGA chip based on the target communication instruction; the first data unit is a data unit storing a signal with a first frequency, and the second data unit is a data unit storing a signal with a second frequency.

In some embodiments, the signal modulation module 12 may specifically include:

the signal storage sub-module is used for judging the frequency of the signal to be modulated, storing the signal to be modulated into the first data unit if the frequency of the signal to be modulated is the first frequency, and storing the signal to be modulated into the second data unit if the frequency of the signal to be modulated is the second frequency;

the signal analysis submodule is used for analyzing the signals to be modulated stored in the first data unit or the second data unit by utilizing the FPGA chip;

the signal transmitting sub-module is used for transmitting the analyzed signal to the digital-to-analog converter by utilizing a serial peripheral interface;

And the signal conversion sub-module is used for converting the analyzed signal based on the digital-to-analog converter so as to obtain a sine wave signal corresponding to the analyzed signal.

In some embodiments, the signal parsing sub-module may specifically include:

and the first signal analysis unit is used for performing direct digital frequency synthesis analysis processing on the signals to be modulated stored in the first data unit or the second data unit by utilizing the phase control word, the frequency control word, the phase accumulator and the waveform memory in the FPGA chip so as to obtain the analyzed signals.

In some embodiments, the signal modulation module 12 may specifically include:

and the sine wave signal processing unit is used for conducting direct current blocking processing on the sine wave signal by utilizing a preset direct current blocking capacitor, and conducting voltage-reducing and current-expanding processing on the target direct current blocking signal obtained after direct current blocking so as to obtain a target modulation signal.

In some embodiments, the signal demodulation module 13 may specifically include:

the signal processing unit to be demodulated is used for processing the signal to be demodulated by utilizing the preset DC blocking capacitor and the zero-crossing comparator so as to obtain the square wave signal;

And the square wave signal sending unit is used for sending the square wave signal to the FPGA chip.

and the second signal analysis unit is used for detecting the high-low level width of the square wave signal and performing width analysis on the target detection signal obtained after the high-low level width detection so as to obtain a target demodulation signal.

Further, the embodiment of the present application further discloses an electronic device, and fig. 11 is a block diagram of an electronic device 20 according to an exemplary embodiment, where the content of the figure is not to be considered as any limitation on the scope of use of the present application.

Fig. 11 is a schematic structural diagram of an electronic device 20 according to an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input output interface 25, and a communication bus 26. Wherein the memory 22 is used for storing a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the HART signal processing method disclosed in any of the foregoing embodiments. In addition, the electronic device 20 in the present embodiment may be specifically an electronic computer.

In this embodiment, the power supply 23 is configured to provide an operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and an external device, and the communication protocol to be followed is any communication protocol applicable to the technical solution of the present application, which is not specifically limited herein; the input/output interface 25 is used for acquiring external input data or outputting external output data, and the specific interface type thereof may be selected according to the specific application requirement, which is not limited herein.

The memory 22 may be a carrier for storing resources, such as a read-only memory, a random access memory, a magnetic disk, or an optical disk, and the resources stored thereon may include an operating system 221, a computer program 222, and the like, and the storage may be temporary storage or permanent storage.

The operating system 221 is used for managing and controlling various hardware devices on the electronic device 20 and computer programs 222, which may be Windows Server, netware, unix, linux, etc. The computer program 222 may further include a computer program capable of performing other specific tasks in addition to the computer program capable of performing the HART signal processing method performed by the electronic device 20 as disclosed in any of the foregoing embodiments.

Further, the application also discloses a computer readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the HART signal processing method disclosed previously. For specific steps of the method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and no further description is given here.

In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.

Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing has outlined the detailed description of the preferred embodiment of the present application, and the detailed description of the principles and embodiments of the present application has been provided herein by way of example only to facilitate the understanding of the method and core concepts of the present application; meanwhile, as those skilled in the art will have modifications in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.

Claims

1. A HART signal processing method, applied to a modem system, comprising:

2. The HART signal processing method according to claim 1, wherein before the analyzing the signal to be modulated by using the FPGA chip, sending the analyzed signal to the digital-to-analog converter for conversion, and processing the sine wave signal obtained after conversion by using a preset first processing rule to obtain the target modulated signal, the method further comprises:

3. The HART signal processing method according to claim 2, wherein the parsing the signal to be modulated using the FPGA chip and transmitting the parsed signal to the digital-to-analog converter for conversion, comprises:

4. The HART signal processing method according to claim 3, wherein the parsing the signal to be modulated stored in the first data unit or the second data unit using the FPGA chip comprises:

5. The HART signal processing method according to claim 1, wherein the processing the converted sine wave signal using the preset first processing rule to obtain the target modulation signal comprises:

6. The HART signal processing method according to claim 5, wherein the processing the signal to be demodulated using a preset second processing rule and transmitting the square wave signal obtained after the processing to the FPGA chip, includes:

7. The HART signal processing method according to any one of claims 1 to 6, wherein the parsing the square wave signal with the FPGA chip to obtain a target demodulated signal comprises:

8. A HART signal processing apparatus, for use in a modem system, comprising:

9. An electronic device, comprising:

a memory for storing a computer program;

a processor for executing the computer program to implement the HART signal processing method according to any one of claims 1 to 7.

10. A computer readable storage medium for storing a computer program which when executed by a processor implements the HART signal processing method according to any one of claims 1 to 7.