CN116094882B - Modulation and demodulation method and system based on analog memory calculation - Google Patents
Modulation and demodulation method and system based on analog memory calculation Download PDFInfo
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0024—Carrier regulation at the receiver end
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Abstract
The invention discloses a modulation and demodulation method and a system based on analog memory internal calculation, which firstly convert binary code streams to be modulated into IQ symbol streams, and then calculate an array conductive value for a constructed analog memory according to the IQ symbol streams, so that the output of the analog memory internal calculation array is modulated; in demodulation, an array conductivity value is calculated for an analog memory by a discrete Fourier transform principle, then signal integration and analog-to-digital conversion are carried out on a signal to be demodulated after the signal is subjected to the analog memory to calculate the array, and the IQ symbol is converted into a binary code, so that demodulation is realized. The invention has low power consumption and small time delay.
Description
Technical Field
The present invention relates to communication technologies, and in particular, to a method and a system for modulating and demodulating based on analog in-memory computation.
Background
Modulation and demodulation are important links in communication systems. The modulation process is generally used at the source end of a communication system to convert a digital baseband signal into a digital modulated signal suitable for channel transmission; at the sink side, the modulated signal needs to be restored to the original signal of transmission, that is, the baseband signal is extracted from the carrier wave for sink processing, which is called demodulation. Demodulation is the inverse process of modulation, the demodulation method corresponds to the modulation method, in the traditional mode, modulation and demodulation are realized in a digital domain, the requirements on DAC and ADC are higher, and the power consumption is large.
The main purpose of the memory computation is to solve the problem of memory wall. The most common computer architecture today is von neumann architecture, where the computation unit and the memory unit are completely separated, the computation unit needs to read data from the memory according to instructions, complete the computation in the computation unit, and store the computation result back into the memory. The von neumann architecture, while classical, the frequent transfer of data between the compute unit and the memory unit creates a memory wall problem. In-memory computation is a solution to the problem of the memory wall, and the basic idea of in-memory computation is to combine computation and storage into one, so as to reduce the frequency of accessing the memory by the processor, because the computation is already completed in the memory for the most part.
Disclosure of Invention
The invention aims to: aiming at the problems existing in the prior art, the invention applies in-memory computation to modulation and demodulation, and provides a modulation and demodulation method and system based on analog in-memory computation, which have low power consumption and small time delay.
The technical scheme is as follows: the modulation method based on analog memory calculation comprises the following steps:
(1) Converting binary code streams to be modulated into IQ symbol streams according to the mapping relation between binary codes and IQ symbols;
(2) Constructing an analog in-memory computing array, wherein the analog in-memory computing array comprises m time period subarrays which are connected in a row arrangement, and each time period subarray is an array formed by connecting 2n multiplied by 2 in-memory computing units; n is the number of carrier frequencies, m is the number of time periods;
(3) Extracting 2nm unmodulated IQ symbols from the IQ symbol stream, and setting a conductance value for an in-memory calculation unit of the analog in-memory calculation array according to the IQ modulation principle according to the extracted IQ symbols;
(4) Inputting voltage signals from the row of the analog memory computing array, processing and outputting column output signals of the analog memory computing array, and thus completing modulation of 2nm IQ symbols;
(5) And (3) returning to the step (3) (4) until the modulation of the IQ symbol stream is completed.
Further, the column outputs of each of the time segment sub-arrays are connected to a multiplexer through a differential amplifier.
Further, the setting of the conductance value according to the IQ modulation principle according to the extracted IQ symbols to the in-memory computing unit of the analog in-memory computing array specifically includes:
selecting a 2×2 in-memory computing unit array from the analog in-memory computing array each time according to a preset priority, and selecting 2 IQ symbols from the extracted IQ symbols each time according to a front-to-back sequence to perform conductivity assignment, specifically: the difference of the conductance of the two in-memory computing units in the first row of the small array of in-memory computing units is the conductance value corresponding to the 1 st symbol of the selected 2 symbols, and the difference of the conductance of the two in-memory computing units in the second row is the conductance value corresponding to the 2 nd symbol of the selected 2 symbols.
Further, the preset priority is specifically: time period from front to back, carrier frequency from low to high, I takes precedence over Q priority.
Further, the calculating the row input voltage signal of the array from the analog memory specifically includes:
the cosi ωt voltage is input from the 2i-1 th row of the analog memory, the sini ωt voltage is input from the 2i row, i=1, …, n, ω is the carrier reference frequency, and t is time.
Further, in order to continuously complete modulation of 2nm IQ symbols, the multiplexer is controlled to sequentially gate the m-period subarrays according to the time sequence.
The modulation system based on analog in-memory calculation comprises:
the coding module is used for converting the binary code stream to be modulated into an IQ symbol stream according to the mapping relation between the binary code and the IQ symbol;
the analog memory internal computing array comprises m time period subarrays which are connected in a row arrangement, and each time period subarray is an array formed by connecting 2n multiplied by 2 memory internal computing units; n is the number of carrier frequencies, m is the number of transmit periods;
the conductance assignment module is used for extracting 2nm unmodulated IQ symbols from the IQ symbol stream each time, and setting a conductance value for an in-memory calculation unit of the analog in-memory calculation array according to the extracted IQ symbols according to an IQ modulation principle until modulation is finished;
the voltage source array is used for inputting voltage signals to the rows of the analog memory computing array;
and the processing module is used for processing and outputting the column output signals of the analog memory internal computing array, so as to finish modulation of 2nm IQ symbols.
The demodulation method based on the analog memory internal calculation comprises the following steps:
(1) The method comprises the steps of constructing an analog in-memory computing array, wherein the analog in-memory computing array comprises a demodulation array and a bias resistor array connected above the demodulation array, the demodulation array is an array formed by connecting (2n+2) x 2n in-memory computing units, and the bias resistor array is an array formed by connecting 1 x 2n in-memory computing units; n is the number of carrier frequencies;
(2) Setting a conductance value for the analog memory internal computing array according to a discrete Fourier transform operation principle;
(3) The signal to be demodulated is processed and then is input into a row of an analog memory internal computing array for computing, and the column output of the analog memory internal computing array is processed and then is output to a decoding module;
(4) The decoding module converts the received signal into a binary code stream according to the mapping relation between the binary code and the IQ symbol.
Further, the method for setting the conductance value of the calculation array in the analog memory according to the discrete Fourier transform operation principle comprises the following steps:
G offset ＝G center
wherein G is offset Calculating the conductance value, G, of the cell for each memory cell of the array of bias resistors center To calculate the central conductance value, G, of the cell conductance range in the selected memory *,# The conductance value of the cell is calculated for the memory of row # of the demodulation array, r being a positive constant greater than 1.
Further, the step of inputting the signal to be demodulated after processing to the analog memory internal computing array for row computation, and outputting the column output of the analog memory internal computing array to the decoding module after processing specifically includes:
the method comprises the steps of inputting a signal to be demodulated into a sampling holder for sampling, inputting the sampled signal into an analog memory computing array through a multiplexer and an inverter for computing, integrating the column output of the analog memory computing array through an integrator, performing analog-to-digital conversion through an analog-to-digital converter, and outputting the column output of the analog memory computing array to a decoding module, wherein the input ends of the inverter and the multiplexer are both connected to the output end of the sampling holder, each row of the demodulation array is connected to the output end of the multiplexer, the bias resistor array is connected to the output end of the inverter, and each column of the analog memory computing array is connected to the input end of one analog-to-digital converter through one integrator.
Further, the method for sampling the sampling signal of the sampling holder comprises the following steps:
to be used forIs one period +.>In (2n+2) times of equidistant sampling, the sampling voltage is kept +.>The sampling signals are sequentially input to the multiplexer and the inverter input terminal according to the time sequence.
Further, the multiplexer gates the p-th output port during the p-th sample voltage hold time, p=1, …,2n+2.
The demodulation system based on the analog in-memory calculation comprises:
the analog memory computing array comprises a demodulation array and a bias resistor array connected above the demodulation array, wherein the demodulation array is formed by connecting (2n+2) multiplied by 2n memory computing units, the bias resistor array is formed by connecting 1 multiplied by 2n memory computing units, and n is the number of carrier frequencies;
the first processing module is connected with the analog memory internal computing array and is used for inputting the signals to be demodulated into the lines of the analog memory internal computing array after being processed;
the conductance setting module is used for setting a conductance value for the analog memory internal calculation array according to the discrete Fourier transform principle;
the second processing module is used for processing the column output of the analog memory internal computing array and outputting the processed column output to the decoding module;
the controller is used for controlling the first processing module and the second processing module;
and the decoding module is connected with the second processing module and is used for converting the received signal into a binary code stream according to the mapping relation between the binary code and the IQ symbol.
The beneficial effects are that: compared with the prior art, the invention has the remarkable advantages that: the invention applies in-memory computing in the communication field, the high integration characteristic can improve the portability of the communication equipment, the parallel computing capability can accelerate the information processing, and the low power consumption characteristic can reduce the power consumption of the communication equipment so as to improve the endurance time, thereby leading the designed modulation-demodulation technology to have low power consumption and small time delay.
Drawings
FIG. 1 is a schematic diagram of an array of in-memory computation in a modulation method based on in-memory computation of the present invention;
FIG. 2 is a schematic diagram of a circuit connection of the analog in-memory computing array of FIG. 1 when the analog in-memory computing unit is a memristor;
FIG. 3 is a schematic diagram of conductance of the analog in-memory computing array of FIG. 1;
FIG. 4 is a schematic diagram of an array of in-memory computation in a demodulation method based on in-memory computation according to the present invention;
FIG. 5 is a schematic diagram of a circuit connection of the analog in-memory computing array of FIG. 4 when the analog in-memory computing unit is a memristor;
FIG. 6 is a schematic diagram of conductance of the demodulation array of FIG. 4, G center ＝400μS，r＝2。
Detailed Description
The embodiment provides a modulation method based on analog memory calculation, which comprises the following steps:
(1) And converting the binary code stream to be modulated into an IQ symbol stream according to the mapping relation between the binary code and the IQ symbol.
The mapping relation between binary codes and IQ symbols is related to the modulation scheme selected, and the following description will take 4-QAM and 16-QAM modulation schemes as examples, but other modulation schemes, such as BPSK, 64QAM, etc., are also supported in the present invention. Table 1 shows a mapping relationship between binary codes of 4-QAM and IQ symbols, the IQ modulation signal is Icosi ωt-Qsini ωt, wherein I is the amplitude of the in-phase cosine carrier cosi ωt, Q is the amplitude of the quadrature sine carrier-sini ωt, and the unit is G 0 ,G 0 For the selected reference conductance, the embodiment selects500. Mu.S. Every two binary codes correspond to one I symbol and one Q symbol, the I symbol and the Q symbol can take 1 and-1, and the electric conductance corresponding to the IQ symbol is G 0 or-G 0 . Table 2 is a mapping relation table of binary codes and IQ symbols of 16-QAM, each four-bit binary code corresponds to one I symbol and one Q symbol, and the I and Q can be 3, 1, -1 and-3. The binary code stream is converted into an IQ symbol stream and then arranged in the manner of I QI Q ….
Table 1 4-mapping relation table of binary code and IQ symbol of QAM
| Binary code | IQ symbol | IQ symbol corresponding to the conductance value |
| 11 | 11(I＝1，Q＝1) | G 0 G 0 |
| 10 | 1-1(I＝1，Q＝-1) | G 0 (-G 0 ) |
| 01 | -11(I＝-1，Q＝1) | (-G 0 )G 0 |
| 00 | -1-1(I＝-1，Q＝-1) | (-G 0 )(-G 0 ) |
Table 2 mapping relation table of binary code and IQ symbol of 16-QAM
| Binary code | IQ symbol | IQ symbol corresponding to the conductance value |
| 1000 | 33(I＝3，Q＝3) | (3G 0 )(3G 0 ) |
| 1001 | 31(I＝3，Q＝1) | (3G 0 )G 0 |
| 1011 | 3-1(I＝3，Q＝-1) | (3G 0 )(-G 0 ) |
| 1010 | 3-3(I＝3，Q＝-3) | (3G 0 )(-3G 0 ) |
| 1100 | 13(I＝1，Q＝3) | G 0 (3G 0 ) |
| 1101 | 11(I＝1，Q＝1) | G 0 G 0 |
| 1111 | 1-1(I＝1，Q＝-1) | G 0 (-G 0 ) |
| 1110 | 1-3(I＝1，Q＝-3) | G 0 (-3G 0 ) |
| 0100 | -13(I＝-1，Q＝3) | (-G 0 )(3G 0 ) |
| 0101 | -11(I＝-1，Q＝1) | (-G 0 )G 0 |
| 0111 | -1-1(I＝-1，Q＝-1) | (-G 0 )(-G 0 ) |
| 0110 | -1-3(I＝-1，Q＝-3) | (-G 0 )(-3G 0 ) |
| 0000 | -33(I＝-3，Q＝3) | (-3G 0 )(3G 0 ) |
| 0001 | -31(I＝-3，Q＝1) | (-3G 0 )G 0 |
| 0011 | -3-1(I＝-3，Q＝-1) | (-3G 0 )(-G 0 ) |
| 0010 | -3-3(I＝-3，Q＝-3) | (-3G 0 ))(-3G 0 ) |
For example, assuming that 4-QAM modulation is adopted and the binary code stream to be transmitted is 110001010011100011 …, the IQ symbol stream after conversion is: 11-1-1-11-11-1-1111-1-1-111- …, the corresponding conductance value flows are: g 0 G 0 (-G 0 )(-G 0 )(-G 0 )G 0 (-G 0 )G 0 (-G 0 )(-G 0 )G 0 G 0 G 0 (-G 0 )(-G 0 )(-G 0 )G 0 G 0 …。
(2) An array of analog in-memory computations is constructed.
The built analog in-memory computing array comprises m time period subarrays which are connected in a row arrangement, wherein the column output of each time period subarray is connected to a multiplexer through a differential amplifier, and each time period subarray is an array formed by connecting 2n multiplied by 2 in-memory computing units; n is the number of carrier frequencies and m is the number of time periods. For ease of identification, each in-memory computational element is labeled, where the in-memory computational element of row (2 i-1) and column 1 of the j-th time segment sub-array is labeledThe in-memory computation unit of column 2 is marked +.>The in-memory computing unit of row 2i and column 1 is marked +.>The in-memory computing unit of column 2 is labeledThe reference numeral indicates both the cell number and its conductance value, i is the carrier frequency number, j is the period number, i=1, …, n, j=1, …, m. The in-memory computing unit herein includes, but is not limited to, a resistive random access memory, a phase change memory, a memristor, a flash memory, etc., and if the memristor is selected, the corresponding analog in-memory computing array is shown in fig. 2.
For example, assuming that the number of carrier frequencies is 15 and the number of time periods is 16, the adopted in-memory computing unit is a memristor, the total scale of the memristor array is 30×32, the memristor array is divided into 16 time period subarrays according to the number of time periods on average, and each time period subarray is a 30×2 memristor array.
(3) Extracting 2nm non-modulated IQ symbols from the IQ symbol stream, and setting a conductance value for an in-memory computing unit of the analog in-memory computing array according to the extracted IQ symbols according to an IQ modulation principle.
The specific steps of setting the conductance value are as follows: selecting a 2×2 in-memory computing unit array from the analog in-memory computing array each time according to a preset priority, and selecting 2 IQ symbols from the extracted IQ symbols each time according to a front-to-back sequence to perform conductivity assignment, specifically: the difference of the conductance of the two in-memory computing units in the first row of the small array of in-memory computing units is the conductance value corresponding to the 1 st symbol of the selected 2 symbols, and the difference of the conductance of the two in-memory computing units in the second row is the conductance value corresponding to the 2 nd symbol of the selected 2 symbols. The preset priority is specifically that the time period is from front to back, the carrier frequency is from low to high, the I takes precedence over the Q priority, namely, for the subarrays formed by the in-memory computing units with the subscript ij, the time period sequence number j=1 is firstly set, then the subarrays formed by the in-memory computing units with the carrier sequence number I value from 1 to n are sequentially assigned, the I takes precedence over the Q during assignment, the time period sequence number j=2 is set again, and the subarrays with the time period sequence numbers 2 are assigned until the subarrays with the time period sequence numbers 2 are assigned.
For example, in the above example, assume that the IQ symbol stream is: 11-1-1-11-11-1-1111-1-1-111 …,2×15×16=480 IQ symbols are extracted as 11-1-1-11-11-1-1111-1-1-111 … (480). Selecting a 2×2 array of in-memory computing units from the in-memory computing arrays according to priority, i.e. selectingA small array of symbols is then extracted from the 480 IQ symbols, i.e. 11 (i=1, q=1, corresponding to a conductance value G 0 ,G 0 ) To conduct conductance assignment. The assignment method is such that the following holds: />To achieve this, a suitable center conductance value G may be selected based on the conductance range of the in-memory computing unit center And a reference conductance value G 0 Setting:selected G center And G 0 Should satisfy->Next, another 2X 2 array of in-memory computing units is selected according to priority, i.e.>The next two symbols, namely-1-1 (i= -1, q= -1, corresponding conductance value of-G), are then extracted from the 480 IQ symbols in a small array of components 0 ,-G 0 ) To conduct the conductance assignment, and in particular,then, other small arrays are assigned according to the priority, and the specific sequence is as follows: subscripts 31,41, …, (15) 1,12,22, …, (15) 2,13,23, …, (15) 3, …,1 (16), 2 (16), …(15) (16) until the assignment is complete. The conductance values of the calculated array in the simulated memory after a certain assignment are shown in figure 3.
(4) And (3) inputting voltage signals from the row of the analog memory computing array, processing and outputting column output signals of the analog memory computing array, and thus completing modulation of 2nm IQ symbols.
The input cosi ωt voltage of the array in the 2i-1 th row is calculated from the analog memory, the input-sini ωt voltage of the array in the 2i row is i=1, …, n, and after the input voltage, the QAM (quadrature amplitude modulation) modulation scheme is completed for the same carrier frequency. At t 1 Period of time illustrates: for the first column, the first row input voltage is cos ωt, ω is the carrier reference frequency, here 2000 pi, via a conductanceAccording to ohm's law, the magnitude of the current generated on the first column isThe second line input voltage is-sin ωt, via a conductance of +.>According to ohm's law, the magnitude of the current generated on the first column is +.>Then according to kirchhoff's current law, the two paths of currents are synthesized into total currentFor the second column, the first row input voltage is cos ωt, via a conductance of +.>According to ohm's law, the magnitude of the current generated on the second column is +.>The second line input voltage is-sin ωt, via a conductance of +.>According to ohm's law, the magnitude of the current generated on the second column isThen according to kirchhoff's current law, the two paths of currents are synthesized into total current +.>The current of the first column and the second column is synthesized into one current through the differential amplifier belowUp to this point, QAM modulation of the omega frequency carrier is completed, other frequencies and so on. For different carrier frequencies, an OFDM (orthogonal frequency division multiplexing) modulation mode is completed, namely, a frequency multiplication voltage signal is adopted for input. The output end of the differential amplifier of the final first period obtains a QAM-OFDM modulation signal containing n frequencies, namely The modulated signal carries n I symbols and n Q symbols, for a total of 2n IQ symbols. The principle of other periods is the same. Finally, to achieve continuous modulation of information, the multiplexer is controlled by the controller according to t 1 ～t m The time period (the time period length is 2 pi/omega) sequentially gates m channels, so that continuous and uninterrupted modulation of information can be completed.
The in-memory computing unit realizes storage and computation through ohm law and kirchhoff current law, and an operation result can be directly obtained from the output current of the array. Based on ohm's law and kirchhoff's current law, the array can complete multiply-accumulate operation of vectors and matrixes in one period, and multiplied factors (conductances) are directly stored in the array without a separate storage unit, so that von neumann bottleneck is bypassed.
(5) And (3) returning to the step (3) (4) until the transmission of the IQ symbol stream is completed.
After each analog memory calculates the electric conductance assignment of the array, 2nm IQ symbols can be modulated, so after one transmission, the electric conductance assignment is carried out again according to the next batch of 2nm IQ symbols, and then the modulation is carried out. If the number of unmodulated IQ-symbols extracted from the IQ-symbol stream is less than 2nm, 0 is used to complement the number of IQ-symbols by 2 nm.
The embodiment also provides a modulation system based on analog in-memory calculation, which comprises:
the coding module is used for converting the binary code stream to be modulated into an IQ symbol stream according to the mapping relation between the binary code and the IQ symbol;
the analog memory internal computing array comprises m time period subarrays which are connected in a row arrangement, and each time period subarray is an array formed by connecting 2n multiplied by 2 memory internal computing units; n is the number of carrier frequencies, m is the number of transmit periods;
the conductance assignment module is used for extracting 2nm unmodulated IQ symbols from the IQ symbol stream each time, and setting a conductance value for an in-memory calculation unit of the analog in-memory calculation array according to the extracted IQ symbols according to an IQ modulation principle until modulation is finished;
the voltage source array is used for inputting voltage signals to the rows of the analog memory computing array; the system specifically comprises 2n voltage sources which are correspondingly connected to 2n rows of a calculation array in an analog memory, wherein the 2i-1 th voltage source outputs cosi omega t voltage, the 2 i-th voltage source outputs-sini omega t voltage, i=1, …, n, omega is carrier reference frequency, and t is time;
the processing module is used for processing and outputting column output signals of the analog memory internal computing array so as to finish modulation of 2nm IQ symbols, and specifically comprises m differential amplifiers and a multiplexer, wherein the input end of each differential amplifier is connected with column output of a time period subarray; the multiplexer is connected with the output ends of the m differential amplifiers;
and the controller is connected with the multiplexer and used for controlling the multiplexer to sequentially gate m time periods according to the time sequence.
The apparatus in this embodiment corresponds to the above method one by one, and is not described in detail with reference to the method, and will not be described again.
The embodiment also provides a demodulation method based on analog in-memory calculation, as shown in fig. 4, including:
(1) An array of analog in-memory computations is constructed.
The analog in-memory computing array comprises a demodulation array and a bias resistor array connected above the demodulation array, wherein the demodulation array is an array formed by connecting (2n+2) multiplied by 2n in-memory computing units, the bias resistor array is an array formed by connecting 1 multiplied by 2n in-memory computing units, each column of the analog in-memory computing array is connected to the input end of an analog-to-digital converter through an integrator, each row of the demodulation array is connected to the output end of a multiplexer, the bias resistor array is connected to the output end of an inverter, and the input ends of the inverter and the multiplexer are both connected to the output end of a sampling holder; n is the number of carrier frequencies. The in-memory computing unit herein includes, but is not limited to, a resistive random access memory, a phase change memory, a memristor, a flash memory, etc., and if the memristor is selected, the corresponding analog in-memory computing array is shown in fig. 5.
(2) And setting a conductance value for the analog memory internal computing array according to the discrete Fourier transform operation principle.
Wherein, the method writes the conductance matrix needed by DFT (discrete Fourier transform) operation into the analog internal computing array, and comprises the following steps:
G offset ＝G center
wherein G is offset Calculating the conductance value, G, of the cell for each memory cell of the array of bias resistors center For the selected center conductance value of the in-memory calculation unit conductance range, this embodiment is 400 μs, r=2, g *,# Line-1 of the demodulation arrayThe conductance values of the cells are calculated in the memory of column #. The partial conductance values of the demodulation array are shown in fig. 6.
(3) The signal to be demodulated is processed and then is input into a row of the analog memory internal computing array for computing, and the column output of the analog memory internal computing array is processed and then is output to the decoding module.
The processing of the signal to be demodulated specifically comprises the following steps: and inputting the signal to be demodulated into a sampling holder for sampling, and inputting the sampled signal into an analog in-memory computing array through a multiplexer and an inverter respectively. The controller controls the sampling of the sampling holder, and the method comprises the following steps: to be used forIs one period +.>In (2n+2) times of equidistant sampling, the sampling voltage is kept +.>The sampling signals are sequentially input to the multiplexer and the inverter input terminal according to the time sequence. The controller controls the multiplexer to gate the p-th output port during the p-th sample voltage holding time, p=1, …,2n+2. The p-th output port is connected with the p-th row of the corresponding demodulation array, and the p-th row of the in-memory calculation unit generates current according to ohm's law; the sampling voltage of the sampling keeper can also act on the bias resistor of each column after passing through the phase inverter, and current is generated according to ohm law; the two paths of currents are synthesized according to kirchhoff current law, and the total current flows to integrators below each column for integration. The column output of the analog memory internal computing array is specifically as follows; integrating by integrator and analog-to-digital conversion by analog-to-digital converter, the controller controls the integrator of each column, in a period +.>And (3) carrying out integration internally, outputting an integration result to an ADC input terminal when the period is finished, returning to zero, and starting integration of the next period. End of cycleIn this case, an n-bit analog-to-digital converter (the ADC bit number is selected in accordance with a predetermined code stream-symbol mapping relationship, and in the case of n=1, the analog-to-digital converter is simply a comparator) is used to convert the digital symbol.
(4) The decoding module converts the received signal into a binary code stream according to the mapping relation between the binary code and the IQ symbol.
The embodiment also provides a demodulation system based on analog in-memory computation, which comprises:
the analog memory computing array comprises a demodulation array and a bias resistor array connected above the demodulation array, wherein the demodulation array is formed by connecting (2n+2) multiplied by 2n memory computing units, the bias resistor array is formed by connecting 1 multiplied by 2n memory computing units, and n is the number of carrier frequencies;
the first processing module is connected with the analog memory internal computing array and is used for inputting the signals to be demodulated into the lines of the analog memory internal computing array after being processed; the circuit specifically comprises a sampling holder, an inverter and a multiplexer, wherein the inverter is connected with the bias resistor array; a multiplexer is connected with the demodulation array; the sampling keeper is connected with the phase inverter and the multiplexer;
the conductance setting module is used for setting a conductance value for the analog memory internal computing array according to the Fourier transform principle;
the second processing module is used for processing the column output of the analog memory internal computing array and outputting the processed column output to the decoding module; the system specifically comprises 2n integrators and 2n analog-to-digital converters, wherein each integrator is connected with a column of output of a calculation array in an analog memory; each analog-to-digital converter is connected with an integrator;
a controller for controlling the multiplexer, the sample holder and the integrator of the first processing module and the second processing module;
and the decoding module is connected with all the analog-digital converters of the second processing module and is used for converting the received signals into binary code streams according to the mapping relation between the binary codes and the IQ symbols.
The device in this embodiment corresponds to the demodulation method one by one, and the description of the method is not detailed herein, and will not be repeated.
The above disclosure is only a preferred embodiment of the present invention and should not be construed as limiting the scope of the invention, which is defined by the appended claims.
Claims (10)
1. A modulation method based on analog in-memory computation, comprising:
(1) Converting binary code streams to be modulated into IQ symbol streams according to the mapping relation between binary codes and IQ symbols;
(2) Constructing an analog in-memory computing array, wherein the analog in-memory computing array comprises m time period subarrays which are connected in a row arrangement, and each time period subarray is an array formed by connecting 2n multiplied by 2 in-memory computing units; n is the number of carrier frequencies, m is the number of time periods;
(3) Extracting 2nm unmodulated IQ symbols from the IQ symbol stream, and setting a conductance value for an in-memory calculation unit of the analog in-memory calculation array according to the extracted IQ symbols according to an IQ modulation principle, wherein the method specifically comprises the following steps: selecting a 2×2 in-memory computing unit array from the analog in-memory computing array each time according to a preset priority, and selecting 2 IQ symbols from the extracted IQ symbols each time according to a front-to-back sequence to perform conductivity assignment, specifically: the difference of the conducing of the two memory computing units in the first row of the memory computing unit array is the conducing value corresponding to the 1 st symbol in the selected 2 symbols, and the difference of the conducing of the two memory computing units in the second row is the conducing value corresponding to the 2 nd symbol in the selected 2 symbols; the preset priority is specifically: time period from front to back, carrier frequency from low to high, priority of I over Q;
(4) Inputting voltage signals from the row of the analog memory computing array, processing and outputting column output signals of the analog memory computing array, and thus completing modulation of 2nm IQ symbols;
(5) And (3) returning to the step (3) (4) until the modulation of the IQ symbol stream is completed.
2. The modulation method based on analog in-memory computation of claim 1, wherein: the column outputs of each of the time segment sub-arrays are connected to a multiplexer through a differential amplifier.
3. The modulation method based on analog in-memory computation of claim 1, wherein: the calculating the row input voltage signal of the array from the analog memory specifically comprises:
the input cos (iωt) voltage of the array at the 2i-1 th row, the input sin (iωt) voltage at the 2 i-th row, i=1, …, n, ω is the carrier reference frequency and t is time are calculated from the analog memory.
4. The modulation method based on analog in-memory computation of claim 2, wherein: in order to continuously complete modulation of 2nm IQ symbols, the multiplexer is controlled to sequentially gate the m-period subarrays according to the time sequence.
5. A modulation system based on analog in-memory computation, comprising:
the coding module is used for converting the binary code stream to be modulated into an IQ symbol stream according to the mapping relation between the binary code and the IQ symbol;
the analog memory internal computing array comprises m time period subarrays which are connected in a row arrangement, and each time period subarray is an array formed by connecting 2n multiplied by 2 memory internal computing units; n is the number of carrier frequencies, m is the number of transmit periods;
the conductance assignment module is used for extracting 2nm unmodulated IQ symbols from the IQ symbol stream each time, and setting a conductance value for an in-memory calculation unit of the analog in-memory calculation array according to the extracted IQ symbols according to an IQ modulation principle until modulation is finished; the setting of the conductance value specifically comprises: selecting a 2×2 in-memory computing unit array from the analog in-memory computing array each time according to a preset priority, and selecting 2 IQ symbols from the extracted IQ symbols each time according to a front-to-back sequence to perform conductivity assignment, specifically: the difference of the conducing of the two memory computing units in the first row of the memory computing unit array is the conducing value corresponding to the 1 st symbol in the selected 2 symbols, and the difference of the conducing of the two memory computing units in the second row is the conducing value corresponding to the 2 nd symbol in the selected 2 symbols; the preset priority is specifically: time period from front to back, carrier frequency from low to high, priority of I over Q;
the voltage source array is used for inputting voltage signals to the rows of the analog memory computing array;
and the processing module is used for processing and outputting the column output signals of the analog memory internal computing array, so as to finish modulation of 2nm IQ symbols.
6. A demodulation method based on analog in-memory computation, characterized by comprising:
(1) The method comprises the steps of constructing an analog in-memory computing array, wherein the analog in-memory computing array comprises a demodulation array and a bias resistor array connected above the demodulation array, the demodulation array is an array formed by connecting (2n+2) x 2n in-memory computing units, and the bias resistor array is an array formed by connecting 1 x 2n in-memory computing units; n is the number of carrier frequencies;
(2) Setting a conductance value for the analog memory internal computing array according to a discrete Fourier transform operation principle;
the method comprises the following steps:
G offset ＝G center
wherein G is offset Calculating the conductance value, G, of the cell for each memory cell of the array of bias resistors center To calculate the central conductance value, G, of the cell conductance range in the selected memory *，# Calculating the conductance value of the unit for the memory of the row # of the demodulation array, r being a positive constant greater than 1;
(3) The signal to be demodulated is processed and then is input into a row of an analog memory internal computing array for computing, and the column output of the analog memory internal computing array is processed and then is output to a decoding module;
(4) The decoding module converts the received signal into a binary code stream according to the mapping relation between the binary code and the IQ symbol.
7. The demodulation method based on analog in-memory computation of claim 6, wherein: the processing of the signal to be demodulated is input to the analog memory internal computing array for row computation, and the processing of the column output of the analog memory internal computing array is output to the decoding module specifically comprises:
the method comprises the steps of inputting a signal to be demodulated into a sampling holder for sampling, inputting the sampled signal into an analog memory computing array through a multiplexer and an inverter for computing, integrating the column output of the analog memory computing array through an integrator, performing analog-to-digital conversion through an analog-to-digital converter, and outputting the column output of the analog memory computing array to a decoding module, wherein the input ends of the inverter and the multiplexer are both connected to the output end of the sampling holder, each row of the demodulation array is connected to the output end of the multiplexer, the bias resistor array is connected to the output end of the inverter, and each column of the analog memory computing array is connected to the input end of one analog-to-digital converter through one integrator.
8. The demodulation method based on analog in-memory computation of claim 7, wherein: the method for sampling signals of the sampling holder comprises the following steps:
to be used forIs one period +.>In (2n+2) times of equidistant sampling, the sampling voltage is kept +.>The sampling signals are sequentially input to the multiplexer and the inverter input terminal according to the time sequence, and omega is the carrier reference frequency.
9. The demodulation method based on analog in-memory computation of claim 7, wherein: the multiplexer gates the p-th output port during the p-th sample voltage hold time, p=1, …,2n+2.
10. A demodulation system based on analog in-memory computation, comprising:
the analog memory computing array comprises a demodulation array and a bias resistor array connected above the demodulation array, wherein the demodulation array is formed by connecting (2n+2) multiplied by 2n memory computing units, the bias resistor array is formed by connecting 1 multiplied by 2n memory computing units, and n is the number of carrier frequencies;
the first processing module is connected with the analog memory internal computing array and is used for inputting the signals to be demodulated into the lines of the analog memory internal computing array after being processed;
the conductance setting module is used for setting a conductance value for the analog memory internal calculation array according to the discrete Fourier transform principle; the method comprises the following steps:
G offset ＝G center
wherein G is offset Calculating the conductance value, G, of the cell for each memory cell of the array of bias resistors center To calculate the central conductance value, G, of the cell conductance range in the selected memory *,# Calculating the conductance value of the unit for the memory of the row # of the demodulation array, r being a positive constant greater than 1;
the second processing module is used for processing the column output of the analog memory internal computing array and outputting the processed column output to the decoding module;
the controller is used for controlling the first processing module and the second processing module;
and the decoding module is connected with the second processing module and is used for converting the received signal into a binary code stream according to the mapping relation between the binary code and the IQ symbol.
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