CN116094492A - Digital filtering system for multi-domain analysis of vector network analyzer - Google Patents

Abstract

The invention provides a digital filtering system for multi-domain analysis of a vector network analyzer, which comprises the following specific processes of signal processing: the analog intermediate frequency signals enter an analog-to-digital conversion control and holding unit through a signal conditioning circuit, and the multichannel analog intermediate frequency signals are converted into multichannel digital intermediate frequency signals; the multichannel digital intermediate frequency signal enters a multichannel data synchronization unit; the method comprises the steps that a continuous filtering unit is arranged in a non-modulation measurement domain, a synchronous modulation filtering unit is arranged in a synchronous modulation domain, and an ADC data storage unit is arranged in a data storage mode, a spectrum mode or other special modes; the filter coefficient generation and control unit generates different FIR filter coefficients according to the input data mode, and sends the filter coefficients to the multichannel parallel FIR filter unit. The technical scheme of the invention solves the problem that a filtering system in the prior art cannot meet the digital filtering requirements of a vector network analyzer in different measuring modes.

Description

Digital filtering system for multi-domain analysis of vector network analyzer

Technical Field

The invention relates to the technical field of digital filtering of a vector network analyzer for multi-domain analysis, in particular to a digital filtering system for the multi-domain analysis of the vector network analyzer.

Background

Filtering is a technology in the most basic and important signal processing field, and is a means for correctly acquiring information of a signal to be detected of a system. With the rapid development of FPGA and DSP chips, digital filtering technology based on programmable hardware is widely applied in the fields of communication, antenna, radar, satellite navigation, instruments, biomedicine and the like. In test instruments such as vector network analyzers, the digital filter usually adopts FIR filter type to process the intermediate frequency signals of the system, the intermediate frequency bandwidths of the filters in different measurement instruments are different, but are usually fixed, and some systems adopt special algorithms to modulate the filter coefficients, but the filter order is more, and the filter coefficients need to be rewritten every time the intermediate frequency bandwidth is changed, so that the data processing time is increased.

In the prior art, two implementation modes of a network instrument digital filtering system for providing complex multi-domain analysis exist, and one implementation mode is that better out-of-band suppression is realized by reducing intermediate frequency bandwidth; a complex algorithm achieves a larger passband and smaller stopband rejection. The first mode reduces the test speed due to the small intermediate frequency bandwidth; the second complex algorithm is not universal, the calculation result cannot be obtained or aliasing is generated in the stop band of the filter, and the cascade filter is high in far-end out-of-band rejection.

Therefore, a network instrument digital filtering system capable of meeting digital filtering requirements of a vector network analyzer in different measuring modes and achieving good testing indexes is needed.

Disclosure of Invention

The invention mainly aims to provide a digital filtering system for multi-domain analysis of a vector network analyzer, which aims to solve the problem that the filtering system in the prior art cannot meet the digital filtering requirements of the vector network analyzer in different measurement modes.

In order to achieve the above purpose, the present invention provides a digital filtering system for multi-domain analysis of a vector network analyzer, wherein the specific flow of the digital filtering system processing signals is as follows:

the analog intermediate frequency signals enter an analog-to-digital conversion control and holding unit through a signal conditioning circuit, and the multichannel analog intermediate frequency signals are converted into multichannel digital intermediate frequency signals;

the multichannel digital intermediate frequency signals enter a multichannel data synchronization unit, and the unit realizes synchronous reading and writing of data among different channels in a clock synchronization, common time base and storage buffer mode so as to ensure that the phase relation among the multichannel digital intermediate frequency signals is kept unchanged;

the method comprises the steps that a continuous filtering unit is arranged in a non-modulation measurement domain, a synchronous modulation filtering unit is arranged in a synchronous modulation domain, and an ADC data storage unit is arranged in a data storage mode, a spectrum mode or other special modes;

after being buffered and shaped, the ADC data of the continuous filtering unit is subjected to digital down conversion with a digital intermediate frequency signal generated by an NCO of the FPGA to obtain I-path and Q-path data, the I-path and Q-path data enter a multichannel parallel FIR filtering unit for filtering, and finally the data are written into a multichannel filtering data storage unit for waiting for further processing;

when the gate control pulse is effective, the synchronous modulation filtering unit starts to process ADC data, mixes with NCO after passing through a delay unit capable of setting delay to obtain I-path and Q-path data, enters a multichannel parallel FIR filtering unit to carry out filtering, and writes a filtering result into a multichannel filtering data storage unit to wait for further processing;

in the data storage mode, the original ADC data is written into the multi-channel data integrating and storing unit through the delay module according to the triggering command of the triggering control unit, namely the triggering condition and the storage number;

the filter coefficient generation and control unit generates different FIR filter coefficients according to an input data mode, namely a continuous filter mode or a synchronous modulation filter mode, and sends the filter coefficients to the multichannel parallel FIR filter unit.

Further, the filter coefficient generation and control unit includes: a primary filter and a secondary filter cascaded therewith.

Further, in the continuous or synchronous modulation filtering mode, the specific flow of the filtering coefficient generation and control unit to generate different FIR filtering coefficients according to the input data mode is as follows:

s1, reading the current intermediate frequency bandwidth of a vector network analyzer;

s2, looking up a table to obtain the FIR filtering order or dynamically producing the filtering order according to a self-adaptive intermediate frequency filter design algorithm;

s3, judging whether the filtering order is smaller than 1024;

s4, if so, obtaining a filtering coefficient address according to the intermediate frequency bandwidth index table lookup, and then executing step S7;

s5, if not, obtaining a primary filter coefficient and a secondary filter order by looking up a table;

s6, taking the order of the second-level filter as the circulation times, and circularly reading the first-level filter coefficient;

s7, sequentially reading the filter coefficients, and sending the filter coefficients into a multichannel parallel FIR filtering unit.

Further, in the synchronous modulation mode, a self-adaptive intermediate frequency filter design algorithm is adopted to generate a filter order, and the specific steps of obtaining the filter coefficient are as follows:

s2.1, calculating an initial filtering order n according to a formula (1) and an intermediate frequency bandwidth IFBW set by a user, wherein C is a constant;

s2.2, calculating an initial filter order m according to the formula (2) and the modulation period Tw;

s2.3, determining a main lobe approximate width formula according to a filter window type selected by a user, when the filter window type is a rectangular window, substituting M and n into a filtering order M, taking a value of the main lobe width which is closer to IFBW as an M value, and performing the next calculation;

s2.4, adjusting the M value according to the formula (3) so that the calculated M value is nearest to the zero point;

further, when a window type other than the rectangular window is selected, the filtering system performs filtering in two stages, and at this time, M values are decomposed into T1 and T2, so that m=t1×t2, T1 and T2 are prime numbers, and T1 is greater than 128 and smaller than 1024, where T1 is a primary filtering order, and T2 is a secondary filtering order.

Further, in the data storage mode, the digital filter system splices the multichannel digital intermediate frequency signals according to the signal input sequence, and reads the multichannel digital intermediate frequency signals into the upper computer through the high-speed PCIe interface, the ADC data storage unit controls the data storage by the trigger control unit, and the trigger control unit generates a control time sequence according to the detection mode;

if the detection mode is an external synchronous mode, detecting an external input signal by using a sampling clock, and starting to store data when the input signal is valid;

if the detection mode is a level mode, starting to store data when the level of the ADC data storage unit meets the condition;

if the detection mode is a delay mode, the user starts and delays for a designated time to start storing data.

The invention has the following beneficial effects:

1. the digital filtering system provided by the invention has the advantages that the filtering requirements of the vector network analyzer in the multi-domain mode are considered, the digital filtering system comprises a standard filtering mode with fixed intermediate frequency bandwidth, a dynamic filter generating algorithm with self-adaptive intermediate frequency bandwidth and a self-defined filtering mode for generating filter coefficients according to a specified window function, and the flexible filtering mode can meet the digital filtering requirements of the vector network analyzer in different measuring modes, so that the digital filtering system meets the requirements of good test indexes;

2. the digital filtering system suitable for the network instrument multi-domain analysis provides a filtering system which can be used for continuous wave testing, pulse testing, intermodulation distortion testing and FFT testing, and provides basic signal analysis processing support for the network instrument frequency domain analysis, time domain analysis, pulse modulation domain analysis and digital domain analysis;

3. under the synchronous modulation filtering mode, the method for acquiring the filter coefficients by adopting the adaptive intermediate frequency filter design algorithm is simpler, the filtering time of each point is shorter, the occupied resources are less, and the time for processing data by the digital filtering system is shortened;

4. the digital filtering system provided by the invention comprises the ADC data storage unit, so that a user can process original sampling data, and the user can expand application conveniently;

5. the multi-channel data synchronization unit ensures that the data obtained by the user is relatively stable.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art. In the drawings:

FIG. 1 shows a signal processing flow diagram of a digital filtering system for multi-domain analysis of a vector network analyzer of the present invention;

fig. 2 shows a flow chart of a filtering mode in the filtering coefficient transmission control unit of fig. 1.

Detailed Description

The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The specific flow of the digital filtering system processing signals for the multi-domain analysis of the vector network analyzer is as follows, as shown in fig. 1:

the analog intermediate frequency signals enter an analog-to-digital conversion control and holding unit through a signal conditioning circuit, and the multichannel analog intermediate frequency signals are converted into multichannel digital intermediate frequency signals;

the multichannel digital intermediate frequency signals enter a multichannel data synchronization unit, and the unit realizes synchronous reading and writing of data among different channels in a clock synchronization, common time base and storage buffer mode so as to ensure that the phase relation among the multichannel digital intermediate frequency signals is kept unchanged;

the method comprises the steps that a continuous filtering unit is arranged in a non-modulation measurement domain, a synchronous modulation filtering unit is arranged in a synchronous modulation domain, and an ADC data storage unit is arranged in a data storage mode, a spectrum mode or other special modes;

after being buffered and shaped, the ADC data of the continuous filtering unit is subjected to digital down conversion with a digital intermediate frequency signal generated by an NCO of the FPGA to obtain I-path and Q-path data, the I-path and Q-path data enter a multichannel parallel FIR filtering unit for filtering, and finally the data are written into a multichannel filtering data storage unit for waiting for further processing;

when the gate control pulse is effective, the synchronous modulation filtering unit starts to process ADC data, mixes with NCO after passing through a delay unit capable of setting delay to obtain I-path and Q-path data, enters a multichannel parallel FIR filtering unit to carry out filtering, and writes a filtering result into a multichannel filtering data storage unit to wait for further processing;

the multichannel filtering data storage unit adopts a first-in first-out queue, and the queue does not need to sample a large-capacity memory, because the data volume after filtering is smaller, if a high-speed data interface is adopted, the time of filtering processing can meet the data reading time;

when in a data storage mode, original ADC data is written into a multi-channel data integration and storage unit through a delay module according to a trigger command of a trigger control unit, namely trigger conditions and the number of storage, the storage unit uses a high-capacity high-speed memory to realize a dual-port read-write mode so as to ensure that the ADC data can be correctly read out while being written into the storage unit, and the capacity of the high-capacity memory needs to be at least larger than the capacity of the ADC sampling rate which is equal to the number of channels;

the filter coefficient generation and control unit generates different FIR filter coefficients according to an input data mode, namely a continuous filter mode or a synchronous modulation filter mode, and sends the filter coefficients to the multichannel parallel FIR filter unit.

The multichannel parallel FIR filtering unit is used for processing filtering flows under different measurement modes, and the invention adopts the FIR filtering mode which can provide a filtering passband of a linear phase and has simple implementation mode and easy FPGA programming implementation; through the FIR mode, the filters with different bandwidths, different shapes and different characteristics can be realized by changing the filter coefficient, and the requirements of multi-domain testing of the network instrument can be met.

Specifically, the filter coefficient generation and control unit includes: a primary filter and a secondary filter cascaded therewith.

Specifically, as shown in fig. 2, in the continuous or synchronous modulation filtering mode, the specific flow of the filtering coefficient generation and control unit generating different FIR filtering coefficients according to the input data mode is as follows:

s1, reading the current intermediate frequency bandwidth of a vector network analyzer;

s2, looking up a table to obtain the FIR filtering order or dynamically producing the filtering order according to a self-adaptive intermediate frequency filter design algorithm;

s3, judging whether the filtering order is smaller than 1024;

s4, if so, obtaining a filtering coefficient address according to the intermediate frequency bandwidth index table lookup, and then executing step S7;

s5, if not, obtaining a primary filter coefficient and a secondary filter order by looking up a table;

s6, taking the order of the second-level filter as the circulation times, and circularly reading the first-level filter coefficient;

s7, sequentially reading the filter coefficients, and sending the filter coefficients into a multichannel parallel FIR filtering unit.

In the continuous filtering mode, the system sequentially obtains the filtering coefficients from a pre-stored filtering coefficient table according to the intermediate frequency bandwidth positioning coefficient address and sends the filtering coefficients to a multichannel parallel FIR filtering unit. The determination of the filter coefficient is realized by a window function FIR design method of Matlab, the filter coefficient is less when the bandwidth is large, and the filter coefficient is determined according to the 3dB intermediate frequency bandwidth, the intermediate frequency and the out-of-band rejection frequency. The filter coefficients with different bandwidths are stored according to the order of the bandwidths, the initial addresses of the filter coefficients with different bandwidths are obtained during reading, and the coefficients are sequentially read from the initial addresses. The filter coefficient is usually large when the bandwidth is small, the filter stage is divided into two stages, the order of the first stage filter is N, fs/n×m=intermediate frequency needs to be ensured, and m is an integer satisfying the condition. The second-stage filter is cascaded with the first-stage filter to achieve a small intermediate frequency bandwidth. The multichannel filtering data storage unit adopts a first-in first-out queue mode, and when the storage unit has data, the storage unit informs a subsequent processing unit to read the data for further processing.

Specifically, in the synchronous modulation mode, a self-adaptive intermediate frequency filter design algorithm is adopted to generate a filter order, and the specific steps of obtaining the filter coefficient are as follows:

s2.1, calculating an initial filtering order n according to a formula (1) and an intermediate frequency bandwidth IFBW set by a user, wherein C is a constant;

s2.2, calculating an initial filter order m according to the formula (2) and the modulation period Tw;

s2.3, determining a main lobe approximate width formula according to a filter window type selected by a user, when the filter window type is a rectangular window, substituting M and n into a filtering order M, taking a value of the main lobe width which is closer to IFBW as an M value, and performing the next calculation;

s2.4, adjusting the M value according to the formula (3) so that the calculated M value is nearest to the zero point;

the M value obtained by the calculation in the steps is filtered, so that the effect of realizing higher spurious suppression of the modulation signal by using the minimum filtering order can be realized, and the filtering requirements under different modulations can be realized by using less filtering time.

Specifically, when a window type other than the rectangular window is selected, the filtering system performs filtering in two stages, and at this time, M values are decomposed into T1 and T2, so that m=t1×t2, T1 and T2 are prime numbers, and T1 is greater than 128 and smaller than 1024, where T1 is a primary filtering order, and T2 is a secondary filtering order.

When the system is in synchronous modulation mode, the self-adaptive intermediate frequency filter design algorithm is adopted to dynamically generate the filter coefficient and the filter order, and the algorithm is a method for selectively filtering the tested signal according to the window function characteristic shown in the table 1 to obtain the tested signal.

The main parameters of the filter window can be seen in table 1, which lists the maximum sidelobe amplitudes, the main lobe approximation widths, the maximum approximation errors and the transition band widths of the equivalent Kaiser windows of the different window functions.

TABLE 1 Main lobe approximation Width Meter for different Window types

In order to fully utilize the limited storage space of the FPGA, the digital filtering system of the vector network analyzer only stores half of the filtering coefficient N according to the characteristic of symmetry of the coefficients of the FIR filter, and returns to 1 from N after N is taken from the 1 st point during filtering; in order to achieve higher filtering precision and reduce system processing pressure, the FIR filtering of the digital filtering system of the vector network analyzer is also divided into two parts, the first part completes the first half filtering, the second part completes the second half filtering, then the two parts are accumulated, and the accumulated sum is sent to the DSP for normalization and other processing, so that smaller filtering bandwidth is achieved with smaller resource occupation.

Specifically, in a data storage mode, the digital filtering system splices the multichannel digital intermediate frequency signals according to the signal input sequence, reads the multichannel digital intermediate frequency signals into an upper computer through a high-speed PCIe interface, controls data storage by the ADC data storage unit by the trigger control unit, and generates a control time sequence by the trigger control unit according to the detection mode;

if the detection mode is an external synchronous mode, detecting an external input signal by using a sampling clock, and starting to store data when the input signal is valid;

if the detection mode is a level mode, starting to store data when the level of the ADC data storage unit meets the condition;

if the detection mode is a delay mode, the user starts and delays for a designated time to start storing data.

It should be understood that the above description is not intended to limit the invention to the particular embodiments disclosed, but to limit the invention to the particular embodiments disclosed, and that the invention is not limited to the particular embodiments disclosed, but is intended to cover modifications, adaptations, additions and alternatives falling within the spirit and scope of the invention.

Claims (6)

1. The digital filtering system for multi-domain analysis of the vector network analyzer is characterized in that the specific flow of the signal processing of the digital filtering system is as follows:

the analog intermediate frequency signals enter an analog-to-digital conversion control and holding unit through a signal conditioning circuit, and the multichannel analog intermediate frequency signals are converted into multichannel digital intermediate frequency signals;

the multichannel digital intermediate frequency signals enter a multichannel data synchronization unit, and the unit realizes synchronous reading and writing of data among different channels in a clock synchronization, common time base and storage buffer mode so as to ensure that the phase relation among the multichannel digital intermediate frequency signals is kept unchanged;

the method comprises the steps that a continuous filtering unit is arranged in a non-modulation measurement domain, a synchronous modulation filtering unit is arranged in a synchronous modulation domain, and an ADC data storage unit is arranged in a data storage mode, a spectrum mode or other special modes;

after being buffered and shaped, the ADC data of the continuous filtering unit is subjected to digital down conversion with a digital intermediate frequency signal generated by an NCO of the FPGA to obtain I-path and Q-path data, the I-path and Q-path data enter a multichannel parallel FIR filtering unit for filtering, and finally the data are written into a multichannel filtering data storage unit for waiting for further processing;

when the gate control pulse is effective, the synchronous modulation filtering unit starts to process ADC data, mixes with NCO after passing through a delay unit capable of setting delay to obtain I-path and Q-path data, enters a multichannel parallel FIR filtering unit to carry out filtering, and writes a filtering result into a multichannel filtering data storage unit to wait for further processing;

in the data storage mode, the original ADC data is written into the multi-channel data integrating and storing unit through the delay module according to the triggering command of the triggering control unit, namely the triggering condition and the storage number;

the filter coefficient generation and control unit generates different FIR filter coefficients according to an input data mode, namely a continuous filter mode or a synchronous modulation filter mode, and sends the filter coefficients to the multichannel parallel FIR filter unit.

2. A digital filtering system for multi-domain analysis of a vector network analyzer according to claim 1, wherein the filter coefficient generation and control unit comprises: a primary filter and a secondary filter cascaded therewith.

3. The digital filtering system for multi-domain analysis of vector network analyzer according to claim 2, wherein the specific flow of the filter coefficient generation and control unit generating different FIR filter coefficients according to the input data mode in the continuous or synchronous modulation filter mode is as follows:

s1, reading the current intermediate frequency bandwidth of a vector network analyzer;

s2, looking up a table to obtain the FIR filtering order or dynamically producing the filtering order according to a self-adaptive intermediate frequency filter design algorithm;

s3, judging whether the filtering order is smaller than 1024;

s4, if so, obtaining a filtering coefficient address according to the intermediate frequency bandwidth index table lookup, and then executing step S7;

s5, if not, obtaining a primary filter coefficient and a secondary filter order by looking up a table;

s6, taking the order of the second-level filter as the circulation times, and circularly reading the first-level filter coefficient;

s7, sequentially reading the filter coefficients, and sending the filter coefficients into a multichannel parallel FIR filtering unit.

4. A digital filtering system for multi-domain analysis of a vector network analyzer according to claim 3, wherein in the synchronous modulation mode, the filtering order is generated by adopting an adaptive intermediate frequency filter design algorithm, and further the specific steps of obtaining the filter coefficient are as follows:

s2.1, calculating an initial filtering order n according to a formula (1) and an intermediate frequency bandwidth IFBW set by a user, wherein C is a constant;

s2.2, calculating an initial filter order m according to the formula (2) and the modulation period Tw;

s2.3, determining a main lobe approximate width formula according to a filter window type selected by a user, when the filter window type is a rectangular window, substituting M and n into a filtering order M, taking a value of the main lobe width which is closer to IFBW as an M value, and performing the next calculation;

and S2.4, adjusting the M value according to the formula (3) so that the calculated M value is nearest to the zero point.

5. The digital filtering system for multi-domain analysis of vector network analyzer according to claim 4, wherein when a window type other than a rectangular window is selected, the filtering system performs filtering in two stages, where M values are decomposed into T1 and T2 such that m=t1×t2, T1 and T2 are prime numbers, and T1 is greater than 128 and less than 1024, where T1 is a first-stage filtering order and T2 is a second-stage filtering order.

6. The digital filtering system for multi-domain analysis of the vector network analyzer according to claim 1, wherein in the data storage mode, the digital filtering system splices the multi-path digital intermediate frequency signals according to the signal input sequence, and reads the signals into the upper computer through the high-speed PCIe interface, the ADC data storage unit controls the data storage by the trigger control unit, and the trigger control unit generates the control time sequence according to the detection mode;

if the detection mode is an external synchronous mode, detecting an external input signal by using a sampling clock, and starting to store data when the input signal is valid;

if the detection mode is a level mode, starting to store data when the level of the ADC data storage unit meets the condition;

if the detection mode is a delay mode, the user starts and delays for a designated time to start storing data.

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