CN116094295A - Inverter topology and inverter - Google Patents

Inverter topology and inverter Download PDF

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Publication number
CN116094295A
CN116094295A CN202211660463.1A CN202211660463A CN116094295A CN 116094295 A CN116094295 A CN 116094295A CN 202211660463 A CN202211660463 A CN 202211660463A CN 116094295 A CN116094295 A CN 116094295A
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switching tube
bridge arm
point
electrode
switching
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CN116094295B (en
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容佳
余火长
夏田
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Solax Power Network Technology Zhejiang Co Ltd
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Solax Power Network Technology Zhejiang Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H02M1/123—Suppression of common mode voltage or current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H02M1/126—Arrangements for reducing harmonics from ac input or output using passive filters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02S—GENERATION OF ELECTRIC POWER BY CONVERSION OF INFRARED RADIATION, VISIBLE LIGHT OR ULTRAVIOLET LIGHT, e.g. USING PHOTOVOLTAIC [PV] MODULES
    • H02S40/00—Components or accessories in combination with PV modules, not provided for in groups H02S10/00 - H02S30/00
    • H02S40/30—Electrical components
    • H02S40/32—Electrical components comprising DC/AC inverter means associated with the PV module itself, e.g. AC modules
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J2207/20—Charging or discharging characterised by the power electronics converter
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention discloses an inversion topology and an inverter, comprising: the input anode, input cathode, bridge arm module; the bridge arm module comprises a bridge arm I, a bridge arm II and a follow current unit; each of the first bridge arm and the second bridge arm comprises at least two switching tubes connected in series; one end of the bridge arm I is connected with the input anode, and the other end of the bridge arm I is connected with the input cathode; the bridge arm II is connected with the bridge arm I in parallel; the follow current unit is connected with the bridge arm I and the bridge arm II; a voltage dividing module; one end of the voltage dividing module is connected with the input positive electrode, and the other end of the voltage dividing module is connected with the input negative electrode; equalizing the bridge arm; one end of the balance bridge arm is connected with the potential midpoint of the voltage division module, and the other end of the balance bridge arm is connected with the midpoint of the bridge arm I; the equalizing bridge arm at least comprises two switching tubes which are connected in reverse series. The invention can weaken the influence caused by inconsistent turn-off characteristics of the switching tube and reduce the intensity of the common-mode voltage source.

Description

Inverter topology and inverter
Technical Field
The invention belongs to the technical field of inverters, and particularly relates to an inversion topology and an inverter.
Background
The non-isolated photovoltaic energy storage inverter framework does not contain an isolation transformer and has the advantages of high conversion efficiency, and low volume, weight and cost. However, because the photovoltaic panel has a parasitic capacitance to the ground, the switching action of the inverter switching device is easy to generate a high-frequency alternating voltage, the voltage acts on the parasitic capacitance, and the elimination of the transformer enables the photovoltaic component and the power grid to be electrically connected to form a loop, so that the generation of a high-frequency common-mode current is finally caused, as shown in fig. 1. The generation of high frequency common mode current can lead to conduction and radiation interference, increased network access current harmonics and loss, and even endanger equipment and personnel safety.
The inversion topology adopted by the non-isolated photovoltaic energy storage inverter in the market at present can generally inhibit the generation of common mode current theoretically. However, in practical application, there are factors such as inconsistent turn-off characteristics of the switching tube, parasitic parameters of the switching tube, and the like, which easily cause that the topology cannot operate in an ideal state, so that common-mode current is easily generated, and in order to reduce the common-mode current, a high-impedance filter is usually required to be connected into a power loop, which leads to an increase in product volume, a decrease in system conversion efficiency, and an increase in product cost.
Disclosure of Invention
The invention aims to provide an inversion topology and an inverter so as to solve the technical problems.
In order to solve the technical problems, the specific technical scheme of the inversion topology and the inverter is as follows:
an inverter topology, comprising:
the input positive electrode is used for being connected with a positive bus of the direct current power supply;
the input negative electrode is used for being connected with a negative bus of the direct current power supply;
bridge arm module; the bridge arm module comprises a bridge arm I, a bridge arm II and a follow current unit; each of the first bridge arm and the second bridge arm comprises at least two switching tubes connected in series; one end of the bridge arm I is connected with the input anode, and the other end of the bridge arm I is connected with the input cathode; the bridge arm II is connected with the bridge arm I in parallel; the follow current unit is connected with the bridge arm I and the bridge arm II;
a voltage dividing module; one end of the voltage dividing module is connected with the input positive electrode, and the other end of the voltage dividing module is connected with the input negative electrode; the method comprises the steps of,
equalizing the bridge arm; one end of the balance bridge arm is connected with the potential midpoint of the voltage division module, and the other end of the balance bridge arm is connected with the midpoint of the bridge arm I; the equalizing bridge arm at least comprises two switching tubes which are connected in reverse series.
Further, the bridge arm I comprises a switching tube Q1 and a switching tube Q2, and the switching tube Q1 and the switching tube Q2 are sequentially connected in series; the connection point of the switching tube Q1 and the switching tube Q2 is set as a point A; the bridge arm II comprises a switching tube Q3 and a switching tube Q4, and the switching tube Q3 and the switching tube Q4 are sequentially connected in series; the connection point of the switching tube Q3 and the switching tube Q4 is set as a point B; the follow current unit comprises a switching tube Q5 and a switching tube Q6, and the switching tube Q5 and the switching tube Q6 are reversely connected in series; the equalizing bridge arm comprises a switching tube Q7 and a switching tube Q8, and the switching tube Q7 and the switching tube Q8 are reversely connected in series; and two ends of the follow current unit are respectively connected with the point A of the bridge arm I and the point B of the bridge arm II.
Further, the switching tube Q1, the switching tube Q2, the switching tube Q3, the switching tube Q4, the switching tube Q5, the switching tube Q6, the switching tube Q7 and the switching tube Q8 are N-channel MOSFETs, a drain electrode of the switching tube Q1 is connected to an input positive electrode, a source electrode of the switching tube Q1 is connected to a drain electrode of the switching tube Q2, and a source electrode of the switching tube Q2 is connected to an input negative electrode; the drain electrode of the switching tube Q3 is connected with the input positive electrode, the source electrode of the switching tube Q3 is connected with the drain electrode of the switching tube Q4, and the source electrode of the switching tube Q4 is connected with the input negative electrode; the source electrode of the switching tube Q5 is connected with the point A, the drain electrode of the switching tube Q5 is connected with the drain electrode of the switching tube Q6, the source electrode of the switching tube Q6 is connected with the point B, the drain electrode of the switching tube Q7 is connected with the potential midpoint of the voltage dividing module, the source electrode of the switching tube Q7 is connected with the source electrode of the switching tube Q8, and the drain electrode of the switching tube Q8 is connected with the point A of the bridge arm I.
Further, the freewheel unit is replaced by a diode D1, a diode D2, a switching tube Q5 and a switching tube Q6; the switching tube Q1, the switching tube Q6 and the switching tube Q2 are sequentially connected in series, and the connection part of the switching tube Q1 and the switching tube Q6 is a point A; the switching tube Q3, the switching tube Q5 and the switching tube Q4 are sequentially connected in series, and the joint of the switching tube Q3 and the switching tube Q5 is set as a point B; the anode of the diode D1 is connected with the junction of the switching tube Q6 and the switching tube Q2, and the cathode of the diode D1 is connected with the point B; the anode of the diode D2 is connected with the junction of the switching tube Q5 and the switching tube Q4, and the cathode of the diode D2 is connected with the point A.
Further, the switching tube Q1, the switching tube Q2, the switching tube Q3, the switching tube Q4, the switching tube Q5, the switching tube Q6, the switching tube Q7 and the switching tube Q8 are N-channel MOSFETs, a drain electrode of the switching tube Q1 is connected to an input positive electrode, a source electrode of the switching tube Q1 is connected to a drain electrode of the switching tube Q6, a source electrode of the switching tube Q6 is connected to a drain electrode of the switching tube Q2, and a source electrode of the switching tube Q2 is connected to an input negative electrode; the drain electrode of the switching tube Q3 is connected with the input positive electrode, the source electrode of the switching tube Q3 is connected with the drain electrode of the switching tube Q5, the source electrode of the switching tube Q5 is connected with the drain electrode of the switching tube Q4, the source electrode of the switching tube Q4 is connected with the input negative electrode, the drain electrode of the switching tube Q7 is connected with the potential midpoint of the voltage division module, the source electrode of the switching tube Q7 is connected with the source electrode of the switching tube Q8, and the drain electrode of the switching tube Q8 is connected with the point A of the bridge arm I.
Further, the voltage dividing module comprises an impedance part Zu and an impedance part Zd, one end of the impedance part Zu is connected with the input positive electrode, the other end of the impedance part Zu is connected with one end of the impedance part Zd, and the other end of the impedance part Zd is connected with the input negative electrode; the connection point of the impedance element Zu and the impedance element Zd is a potential midpoint.
Further, the inversion topology further comprises a filter circuit, one end of the filter circuit is connected with the middle point of the bridge arm I, and the other end of the filter circuit is connected with the middle point of the bridge arm II.
Further, the filter circuit includes an inductor La, a capacitor Co, and an inductor Lb, where the inductor La is connected in series with the capacitor Co and the inductor Lb.
The invention also discloses an inverter comprising the inverter topology.
The invention also discloses an energy storage system, which comprises:
a battery and the inverter; the inverter is connected with the storage battery.
The inversion topology and the inverter have the following advantages: the invention can weaken the influence caused by inconsistent switching-off characteristics of the switching tube, reduce the intensity of a common-mode voltage source from the source, avoid the common-mode current caused by factors such as inconsistent switching-off characteristics of the switching tube, parasitic parameters of the switching tube and the like in the prior art, and can inhibit the common-mode current to a reasonable level without being provided with an expensive filter. The method can be applied to a non-isolated photovoltaic energy storage inverter.
Drawings
FIG. 1 is a schematic diagram of the generation of a high frequency common mode current for a non-isolated photovoltaic energy storage inverter;
fig. 2 is a schematic diagram of a topology of a conventional non-isolated photovoltaic energy storage inverter;
FIG. 3 is a schematic diagram of the equivalent circuit of FIG. 2;
FIG. 4 is a simplified schematic diagram of the high frequency model of FIG. 3;
FIG. 5 is a schematic diagram of a modulation scheme of the circuit of FIG. 3;
FIG. 6 is a schematic diagram of the equivalent circuit of FIG. 2 after Q1, Q2, Q3, Q4 are turned off;
fig. 7 is a schematic diagram of an inverter topology circuit structure according to the present invention;
FIG. 8 is a schematic diagram of an inverter topology modulation scheme according to the present invention;
fig. 9 is a schematic diagram of an inverter topology circuit variant structure according to the present invention.
Detailed Description
For a better understanding of the objects, structure and function of the invention, an inverter topology and an inverter of the invention will be described in further detail with reference to the accompanying drawings.
First, the drawbacks of the common topology are explained as follows:
taking the common topology in fig. 2 as an example, the parasitic capacitance Cp of the photovoltaic panel to ground and the impedance Rp of the neutral point N to ground are introduced, so that an equivalent circuit is obtained as shown in fig. 3.
Setting the voltage of A, B points to a direct current bus voltage reference point G as Ua (S) and Ub (S) respectively; the high frequency model of fig. 3 can be simplified to fig. 4 by assuming Zp (S) as the equivalent impedance after the parasitic capacitance Cp is connected in series with the ground impedance Rp, and considering that the high frequency impedance of the parasitic capacitor Co at the system switching frequency is negligible. Wherein Ia (S) and Ib (S) are currents flowing through the inductor La and the inductor Lb, respectively. Za (S) and Zb (S) are impedances corresponding to the inductor La and the inductor Lb, respectively. The analytical circuit may obtain:
U a (S)＝I a (S)·Z a (S)+[I a (S)+I b (S)]·Z p (S)
U b (S)＝I b (S)·Z b (S)+[I a (S)+I b (S)]·Z p (S)
let L a ＝L b
Then there is Z a (S)＝Z b (S)
Let Z a (S)＝Z b (S)＝Z(S)
Then there are:
U a (S)+U b (S)＝[I a (S)+I b (S)]·[Z(S)+2·Z p (S)]
Figure BDA0004013623370000051
set I a (S)+I b (S)＝I com (S)
Then there are:
Figure BDA0004013623370000052
I com (S) is a Laplace transform expression of the common mode current. In steady state S=j.omega
Where j is an imaginary unit and ω is an angular frequency.
Figure BDA0004013623370000053
I com (j.omega.) is a frequency domain expression of the common mode current.
It can be seen that when the sum of the voltages of the point a and the point B to the reference point G in the time domain is a constant value, the sum of the voltages of the point a and the point B to the reference point G in the frequency domain is zero, and the following steps are included:
U a (j·ω)+U b (j·ω)＝0
I com (j·ω)＝0
at this time, the common mode current ac is zero, and the common mode current dc is zero because the parasitic capacitor Cp has the dc isolation function in fig. 3.
The circuit modulation scheme depicted in fig. 2 is as in fig. 5.
When the amplitude of the modulation wave output by the controller is higher than the amplitude of the carrier wave, the switching tube Q1 and the switching tube Q4 are driven to be at high level, and the switching tube Q6 is driven to be at low level; when the amplitude of the modulation wave output by the controller is lower than the amplitude of the carrier wave, the switching tube Q1 and the switching tube Q4 are driven to be at low level, and the switching tube Q6 is driven to be at high level; in the whole Uo (t) positive half cycle, the switching transistors Q2 and Q3 are driven low, and the switching transistor Q5 is driven high.
Uo (t) negative half cycle, namely when the amplitude of the modulation wave output by the controller is higher than the amplitude of the carrier wave, the switching tube Q2 and the switching tube Q3 are driven to be at high level, and the switching tube Q5 is driven to be at low level; when the amplitude of the modulation wave output by the controller is lower than the amplitude of the carrier wave, the switching tube Q2 and the switching tube Q3 are driven to be at low level, and the switching tube Q5 is driven to be at high level; in the whole Uo (t) positive half cycle, the switching transistors Q1 and Q4 are driven low, and the switching transistor Q6 is driven high.
As shown in fig. 2, in an ideal state, when the switching tube Q1 and the switching tube Q4 are turned on, the point a is Ubus, the point B voltage is 0, and the sum of the two is Ubus;
when Q2 and Q3 are conducted, the point A is 0, the point B voltage is Ubus, and the sum of the two is Ubus;
ideally, the switching speed and the characteristics of the switching tube Q1, the switching tube Q2, the switching tube Q3 and the switching tube Q4 are the same, and when the switching tube Q1, the switching tube Q2, the switching tube Q3 and the switching tube Q4 are turned off, the voltage at point a and the voltage at point B are equal to one half of the voltage of the Ubus, and the sum of the voltage at point a and the voltage at point B is a constant value.
Therefore, in an ideal state, the sum of the voltages of the point A and the point B is constant voltage Ubus at any time, and the system does not generate leakage current.
However, in an actual circuit, there is a certain difference between the characteristics of the driving circuit and the switching tube, and the sum of the voltage at point a and the voltage at point B is liable to be a non-constant value. Let Z13 be the parallel impedance after switching Q1 and Q3 off, and let Z24 be the parallel impedance after switching Q2 and Q4 off. When the switching tube Q1, the switching tube Q2, the switching tube Q3, and the switching tube Q4 are turned off, the equivalent circuit of fig. 2 is shown in fig. 6, and it can be seen that the point a is short-circuited with the point B, the current of the inductor La and the inductor Lb follow the energy circuit in fig. 6, and the magnitudes of the currents flowing through the inductor La and the inductor Lb are equal. At this time, the potential of the point A is equal to the potential of the point B, and the potential is influenced by the synchronism of the turn-off of the switching tube Q1, the switching tube Q2, the switching tube Q3 and the switching tube Q4 and by the equivalent impedance after the turn-off of the switching tube Q1, the switching tube Q2, the switching tube Q3 and the switching tube Q4.
After the switching transistors Q1, Q2, Q3, and Q4 are completely turned off, if Z13 and Z24 are resistive, there are:
Figure BDA0004013623370000071
if the switching-off characteristics of the switching tubes are not consistent, there are:
Z 13 ≠Z 24
Figure BDA0004013623370000072
U a (t)+U b (t)≠U bus
it can be seen that the system is prone to leakage currents when there is a difference in the switching characteristics of the switching tubes. FIG. 5 shows that Z13 < Z24, where the sum of the voltages at points A and B cannot meet the condition that the voltage at any moment is constant, the system is prone to generate leakage current.
In order to solve the above problems, the inverter power topology designed by the present invention is as shown in fig. 7. The circuit comprises an input positive electrode, an input negative electrode, a bridge arm I, a bridge arm II, a follow current unit, an equalizing bridge arm, a filter circuit and a voltage division module;
the input positive electrode is connected with a positive bus of the direct current power supply, and the input negative electrode is connected with a negative bus of the direct current power supply. The bridge arm I comprises a switching tube Q1 and a switching tube Q2, and the switching tube Q1 and the switching tube Q2 are sequentially connected in series; in one embodiment, the switching tube Q1 and the switching tube Q2 are N-channel MOSFETs, the drain electrode of the switching tube Q1 is connected to the input positive electrode, the source electrode of the switching tube Q1 is connected to the drain electrode of the switching tube Q2, the source electrode of the switching tube Q2 is connected to the input negative electrode, and the connection point of the switching tube Q1 and the switching tube Q2 is set as point a.
The bridge arm II comprises a switching tube Q3 and a switching tube Q4, and the switching tube Q3 and the switching tube Q4 are sequentially connected in series; in one embodiment, the switching tube Q3 and the switching tube Q4 are N-channel MOSFETs, the drain electrode of the switching tube Q3 is connected to the input positive electrode, the source electrode of the switching tube Q3 is connected to the drain electrode of the switching tube Q4, the source electrode of the switching tube Q4 is connected to the input negative electrode, and the connection point of the switching tube Q3 and the switching tube Q4 is set as the point B.
As one embodiment of the freewheel unit, the freewheel unit includes a switching tube Q5 and a switching tube Q6, and the switching tube Q5 and the switching tube Q6 are connected in reverse series. In one embodiment, the switching transistor Q5 and the switching transistor Q6 are N-channel MOSFETs, the source of the switching transistor Q5 is connected to the point a, the drain of the switching transistor Q5 is connected to the drain of the switching transistor Q6, and the source of the switching transistor Q6 is connected to the point B.
One end of the filter circuit is connected with the point A of the balance bridge arm I, and the other end of the filter circuit is connected with the point B of the bridge arm II. As one embodiment of the filter circuit, the filter circuit includes an inductor La, a capacitor Co, and an inductor Lb, the inductor La is connected in series with the capacitor Co and the inductor Lb, one end of the series circuit is connected to the point a of the bridge arm one, and the other end is connected to the point B of the bridge arm two.
The voltage dividing module comprises an impedance piece Zu and an impedance piece Zd, one end of the impedance piece Zu is connected with the input positive electrode, the other end of the impedance piece Zu is connected with one end of the impedance piece Zd, and the other end of the impedance piece Zd is connected with the input negative electrode; the connection point of the impedance Zu and the impedance Zd is the potential midpoint. The impedance Zu is equal to the impedance Zd in parameter. The impedance element includes at least a resistor, and the resistor may be a resistor alone or a resistor, a capacitor, or other components, so as to satisfy the requirement that the parameters of the impedance element Zu and the impedance element Zd are equal. .
The equalizing bridge arm comprises a switching tube Q7 and a switching tube Q8, and the switching tube Q7 and the switching tube Q8 are reversely connected in series; and two ends of the balance bridge arm are respectively connected with the potential midpoint of the voltage division module and the point A of the bridge arm I. In one embodiment, the switching tube Q7 and the switching tube Q8 are N-channel MOSFETs, the drain electrode of the switching tube Q7 is connected to the potential midpoint of the voltage dividing module, the source electrode of the switching tube Q7 is connected to the source electrode of the switching tube Q8, and the drain electrode of the switching tube Q8 is connected to the point a of the bridge arm one.
The bridge arm I, the bridge arm II, the freewheel unit and the balance bridge arm can also comprise a resistor, and the resistor is connected with a switch tube in the bridge arm in series.
The system modulation is as in fig. 8.
When the amplitude of the modulation wave output by the controller is higher than the amplitude of the carrier wave, the switching tube Q1 and the switching tube Q4 are driven to be at high level, the switching tube Q6 is driven to be at low level, and the switching tube Q7 and the switching tube Q8 are driven to be at low level; when the amplitude of the modulation wave output by the controller is lower than the amplitude of the carrier wave, the switching tube Q1 and the switching tube Q4 are driven to be at low level, the switching tube Q6 is driven to be at high level, and the switching tube Q7 and the switching tube Q8 are driven to be at high level; in the whole Uo (t) positive half cycle, the switching transistors Q2 and Q3 are driven low, and the switching transistor Q5 is driven high.
Uo (t) negative half cycle, namely when the amplitude of the modulation wave output by the controller is higher than the amplitude of the carrier wave, the switching tube Q2 and the switching tube Q3 are driven to be high level, the switching tube Q5 is driven to be low level, and the switching tube Q7 and the switching tube Q8 are driven to be low level; when the amplitude of the modulation wave output by the controller is lower than the amplitude of the carrier wave, the switching tube Q2 and the switching tube Q3 are driven to be at low level, the switching tube Q5 is driven to be at high level, and the switching tube Q7 and the switching tube Q8 are driven to be at high level; in the whole Uo (t) positive half cycle, the switching transistors Q1 and Q4 are driven low, and the switching transistor Q6 is driven high.
The impedance piece Zu is set to be equal to the impedance piece Zd, and has:
Z u ＝Z d ＞＞Z 13
Z u ＝Z d ＞＞Z 24
then, after the switching tube Q1, the switching tube Q2, the switching tube Q3 and the switching tube Q4 are turned off, the potential of the point C can be approximately obtained as follows:
Figure BDA0004013623370000091
as can be seen, in the positive half cycle Uo (t), after the switching transistors Q1 and Q4 are turned off, the switching transistors Q7 and Q8 are turned on, and the points a and B are clamped to the point C potential, and at this time, there are:
U a (t)＝U b (t)＝U bus
the negative half-cycle of Uo (t) is similar to the positive half-cycle of Uo (t). When the switching tube Q1 and the switching tube Q4 are conducted, the point A is Ubus, the point B voltage is 0, and the sum of the two is Ubus; when the switching tube Q2 and the switching tube Q3 are conducted, the point A is 0, the point B voltage is Ubus, and the sum of the two is Ubus; therefore, the sum of the voltages at the point A and the point B is a constant voltage Ubus at any time, and the system does not generate leakage current.
A modification of the topology of fig. 7 is as in fig. 9, and the modulation scheme of fig. 9 is the same as that of fig. 7. The topology and debug mode of fig. 9 are also within the scope of the present technology.
As another embodiment of the freewheel unit, the freewheel unit is replaced by a freewheel unit including a diode D1, a diode D2, a switching tube Q5 and a switching tube Q6; the switching tube Q1, the switching tube Q6 and the switching tube Q2 are sequentially connected in series, and the connection part of the switching tube Q1 and the switching tube Q6 is a point A; specifically, the switching tube Q1, the switching tube Q2 and the switching tube Q6 are N-channel MOSFETs, the drain electrode of the switching tube Q1 is connected to the input anode, the source electrode of the switching tube Q1 is connected to the drain electrode of the switching tube Q6, the source electrode of the switching tube Q6 is connected to the drain electrode of the switching tube Q2, and the source electrode of the switching tube Q2 is connected to the input cathode.
The switching tube Q3, the switching tube Q5 and the switching tube Q4 are sequentially connected in series, and the joint of the switching tube Q3 and the switching tube Q5 is set as a point B; the anode of the diode D1 is connected with the junction of the switching tube Q6 and the switching tube Q2, and the cathode of the diode D1 is connected with the point B; the anode of the diode D2 is connected with the junction of the switching tube Q5 and the switching tube Q4, and the cathode of the diode D2 is connected with the point A; specifically, the switching tube Q3, the switching tube Q4, and the switching tube Q5 are N-channel MOSFETs, a drain electrode of the switching tube Q3 is connected to an input positive electrode, a source electrode of the switching tube Q3 is connected to a drain electrode of the switching tube Q5, a source electrode of the switching tube Q5 is connected to a drain electrode of the switching tube Q4, and a source electrode of the switching tube Q4 is connected to an input negative electrode.
The equalizing bridge arm comprises a switching tube Q7 and a switching tube Q8, and the switching tube Q7 and the switching tube Q8 are reversely connected in series; and two ends of the balance bridge arm are respectively connected with the potential midpoint of the voltage division module and the point A of the bridge arm I. In one embodiment, the switching tube Q7 and the switching tube Q8 are N-channel MOSFETs, the drain electrode of the switching tube Q7 is connected to the potential midpoint of the voltage dividing module, the source electrode of the switching tube Q7 is connected to the source electrode of the switching tube Q8, and the drain electrode of the switching tube Q8 is connected to the point a of the bridge arm one.
One end of the filter circuit is connected with the point A, and the other end of the filter circuit is connected with the point B. The filter circuit includes an inductor La, a capacitor Co, and an inductor Lb, and the inductor La is connected in series with the capacitor Co and the inductor Lb.
The voltage dividing module comprises an impedance piece Zu and an impedance piece Zd, one end of the impedance piece Zu is connected with the input positive electrode, the other end of the impedance piece Zu is connected with one end of the impedance piece Zd, and the other end of the impedance piece Zd is connected with the input negative electrode; the connection point of the impedance Zu and the impedance Zd is the potential midpoint. The impedance Zu is equal to the impedance Zd in parameter.
The MOSFET described above may also be replaced by an IGBT of the same or similar function.
It will be understood that the invention has been described in terms of several embodiments, and that various changes and equivalents may be made to these features and embodiments by those skilled in the art without departing from the spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims (10)

1. An inverter topology, comprising:
the input positive electrode is used for being connected with a positive bus of the direct current power supply;
the input negative electrode is used for being connected with a negative bus of the direct current power supply;
bridge arm module; the bridge arm module comprises a bridge arm I, a bridge arm II and a follow current unit; each of the first bridge arm and the second bridge arm comprises at least two switching tubes connected in series; one end of the bridge arm I is connected with the input anode, and the other end of the bridge arm I is connected with the input cathode; the bridge arm II is connected with the bridge arm I in parallel; the follow current unit is connected with the bridge arm I and the bridge arm II;
a voltage dividing module; one end of the voltage dividing module is connected with the input positive electrode, and the other end of the voltage dividing module is connected with the input negative electrode; the method comprises the steps of,
equalizing the bridge arm; one end of the balance bridge arm is connected with the potential midpoint of the voltage division module, and the other end of the balance bridge arm is connected with the midpoint of the bridge arm I; the equalizing bridge arm at least comprises two switching tubes which are connected in reverse series.
2. The inverter topology of claim 1, wherein said leg one comprises a switching tube Q1 and a switching tube Q2, said switching tube Q1 and switching tube Q2 being serially connected in sequence; the connection point of the switching tube Q1 and the switching tube Q2 is set as a point A; the bridge arm II comprises a switching tube Q3 and a switching tube Q4, and the switching tube Q3 and the switching tube Q4 are sequentially connected in series; the connection point of the switching tube Q3 and the switching tube Q4 is set as a point B; the follow current unit comprises a switching tube Q5 and a switching tube Q6, and the switching tube Q5 and the switching tube Q6 are reversely connected in series; the equalizing bridge arm comprises a switching tube Q7 and a switching tube Q8, and the switching tube Q7 and the switching tube Q8 are reversely connected in series; and two ends of the follow current unit are respectively connected with the point A of the bridge arm I and the point B of the bridge arm II.
3. The inverter topology of claim 2, wherein the switching tube Q1, the switching tube Q2, the switching tube Q3, the switching tube Q4, the switching tube Q5, the switching tube Q6, the switching tube Q7, and the switching tube Q8 are N-channel MOSFETs, a drain electrode of the switching tube Q1 is connected to an input positive electrode, a source electrode of the switching tube Q1 is connected to a drain electrode of the switching tube Q2, and a source electrode of the switching tube Q2 is connected to an input negative electrode; the drain electrode of the switching tube Q3 is connected with the input positive electrode, the source electrode of the switching tube Q3 is connected with the drain electrode of the switching tube Q4, and the source electrode of the switching tube Q4 is connected with the input negative electrode; the source electrode of the switching tube Q5 is connected with the point A, the drain electrode of the switching tube Q5 is connected with the drain electrode of the switching tube Q6, the source electrode of the switching tube Q6 is connected with the point B, the drain electrode of the switching tube Q7 is connected with the potential midpoint of the voltage dividing module, the source electrode of the switching tube Q7 is connected with the source electrode of the switching tube Q8, and the drain electrode of the switching tube Q8 is connected with the point A of the bridge arm I.
4. The inverter topology of claim 2, wherein the freewheel unit is replaced by a circuit comprising diode D1, diode D2, switching tube Q5 and switching tube Q6; the switching tube Q1, the switching tube Q6 and the switching tube Q2 are sequentially connected in series, and the connection part of the switching tube Q1 and the switching tube Q6 is a point A; the switching tube Q3, the switching tube Q5 and the switching tube Q4 are sequentially connected in series, and the joint of the switching tube Q3 and the switching tube Q5 is set as a point B; the anode of the diode D1 is connected with the junction of the switching tube Q6 and the switching tube Q2, and the cathode of the diode D1 is connected with the point B; the anode of the diode D2 is connected with the junction of the switching tube Q5 and the switching tube Q4, and the cathode of the diode D2 is connected with the point A.
5. The inverter topology of claim 4, wherein said switching tube Q1, switching tube Q2, switching tube Q3, switching tube Q4, switching tube Q5, switching tube Q6, switching tube Q7, and switching tube Q8 are N-channel MOSFETs, the drain of said switching tube Q1 is connected to the input positive pole, the source of said switching tube Q1 is connected to the drain of switching tube Q6, the source of said switching tube Q6 is connected to the drain of switching tube Q2, and the source of said switching tube Q2 is connected to the input negative pole; the drain electrode of the switching tube Q3 is connected with the input positive electrode, the source electrode of the switching tube Q3 is connected with the drain electrode of the switching tube Q5, the source electrode of the switching tube Q5 is connected with the drain electrode of the switching tube Q4, the source electrode of the switching tube Q4 is connected with the input negative electrode, the drain electrode of the switching tube Q7 is connected with the potential midpoint of the voltage division module, the source electrode of the switching tube Q7 is connected with the source electrode of the switching tube Q8, and the drain electrode of the switching tube Q8 is connected with the point A of the bridge arm I.
6. The inverter topology according to claim 1, wherein the voltage dividing module comprises an impedance Zu and an impedance Zd, one end of the impedance Zu is connected to the input positive electrode, the other end is connected to one end of the impedance Zd, and the other end of the impedance Zd is connected to the input negative electrode; the connection point of the impedance element Zu and the impedance element Zd is a potential midpoint.
7. The inverter topology of claim 1, further comprising a filter circuit having one end connected to a midpoint of leg one and another end connected to a midpoint of leg two.
8. The inverter topology of claim 7, wherein said filter circuit comprises an inductor La, a capacitor Co, and an inductor Lb, said inductor La being in series with capacitor Co and inductor Lb.
9. An inverter comprising the inverter topology of any one of claims 1-8.
10. An energy storage system, comprising:
a battery and the inverter according to claim 9; the inverter is connected with the storage battery.
CN202211660463.1A 2022-12-23 2022-12-23 Inverter topology and inverter Active CN116094295B (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202004681U (en) * 2011-03-31 2011-10-05 上海美科新能源股份有限公司 Topological structure of photovoltaic grid-connected inverter
CN102361408A (en) * 2011-10-20 2012-02-22 东南大学 Non-isolated photovoltaic grid-connected inverter and switching control time sequence thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202004681U (en) * 2011-03-31 2011-10-05 上海美科新能源股份有限公司 Topological structure of photovoltaic grid-connected inverter
CN102361408A (en) * 2011-10-20 2012-02-22 东南大学 Non-isolated photovoltaic grid-connected inverter and switching control time sequence thereof

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