CN116093145A - Grid manufacturing method - Google Patents
Grid manufacturing method Download PDFInfo
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- CN116093145A CN116093145A CN202310090289.XA CN202310090289A CN116093145A CN 116093145 A CN116093145 A CN 116093145A CN 202310090289 A CN202310090289 A CN 202310090289A CN 116093145 A CN116093145 A CN 116093145A
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- etching
- gate
- layer
- polysilicon layer
- isotropic etching
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 97
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 21
- 229920005591 polysilicon Polymers 0.000 claims description 41
- 239000000460 chlorine Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 14
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 9
- 229910052731 fluorine Inorganic materials 0.000 claims description 9
- 239000011737 fluorine Substances 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 7
- 229910052801 chlorine Inorganic materials 0.000 claims description 7
- 239000007789 gas Substances 0.000 description 22
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000003667 anti-reflective effect Effects 0.000 description 2
- 210000000746 body region Anatomy 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000001000 micrograph Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 125000001153 fluoro group Chemical group F* 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012806 monitoring device Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
Abstract
The invention provides a method for manufacturing a grid, which comprises the steps of performing first isotropic etching to remove native oxide on the side wall of the grid after the grid is formed by etching a polycrystalline silicon layer, and performing second isotropic etching to remove stripe morphology on the side wall of the grid. According to the invention, two-step isotropic etching is added after the grid electrode is etched, and the stripe phenomenon on the side wall of the grid electrode is avoided by controlling the etching parameters of the two-step isotropic etching, so that the shape of the side wall of the grid electrode is improved, and the stability of the device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a grid electrode.
Background
RFLDMOS (Radio Frequency Lateral Double-diffused MOSFET) has the advantages of high working frequency, high voltage resistance, high output power, high gain, high linearity and the like, and is widely applied to mobile transmitting base stations, broadcast television transmitting base stations, broadband frequency modulation transmitters, airborne transponders, radar systems and the like.
The gate morphology has an important influence on the threshold voltage, and in the manufacturing process of the RFLDMOS device, polysilicon gate is formed by etching polysilicon, and if the etched gate morphology is unstable, the threshold voltage of the device is influenced, so that the performance of the device is influenced. However, in the gate electrode (GPL ET) of the RFLDMOS product, due to the coarsening of polysilicon particles, during the process of etching the gate polysilicon (Poly), the sidewall stripe (stress) of the gate electrode is serious, as shown in fig. 1, and a layer of native oxide is easily formed on the sidewall, so that the subsequent over-etching (Poly OE step) of the gate electrode cannot improve the stress morphology, which causes trouble to the etched sidewall and bottom morphology. Therefore, a method for fabricating a gate is needed to improve the gate sidewall morphology.
Disclosure of Invention
The invention aims to provide a manufacturing method of a grid electrode, which improves the shape of the side wall of the grid electrode and improves the stability of a device by adding two isotropic etching parts in the grid electrode etching process.
In order to achieve the above object, the present invention provides a method for manufacturing a gate, comprising:
providing a substrate, and sequentially forming a gate oxide layer and a polysilicon layer on the substrate;
etching the polysilicon layer to form a grid electrode;
performing first isotropic etching to remove the native oxide on the side wall of the grid electrode;
and performing a second isotropic etching to remove the stripe morphology of the side wall of the grid electrode.
Optionally, the process of forming the gate electrode by etching the polysilicon layer includes:
forming a patterned bottom anti-reflection layer and a photoresist layer on the polysilicon layer;
and etching the polysilicon layer by taking the patterned bottom anti-reflection layer and the photoresist layer as masks.
Optionally, the etching the polysilicon layer includes: pre-etching, main etching, landing etching and over-etching.
Optionally, the etching gas used in the first isotropic etching includes a fluorine-based gas.
Optionally, the fluorine-based gas comprises CF 4 、CH 2 F 2 、CHF 3 One or a combination of at least two of the foregoing.
Optionally, the bias power in the first isotropic etching is 50-100W.
Optionally, the etching gas used in the second isotropic etching includes a chlorine-based gas.
Optionally, the chlorine-based gas comprises Cl 2 、CH 2 Cl 2 、CH 3 One or a combination of at least two of Cl.
Optionally, the bias power in the second isotropic etching is 50-100W.
Optionally, the thickness of the gate oxide layer is
The thickness of the polysilicon layer is
The bottom anti-reflection layer has a thickness of +.>
/>
Drawings
FIG. 1 is an electron microscope image of the sidewall morphology of a polysilicon gate;
FIG. 2 is a flowchart of a method for fabricating a gate according to an embodiment of the present invention;
fig. 3A to fig. 3D are schematic structural diagrams of steps corresponding to a method for manufacturing a gate according to an embodiment of the invention;
fig. 4 is an electron microscope image of the sidewall morphology of the polysilicon gate manufactured by the gate manufacturing method provided by the invention.
Wherein, the reference numerals are as follows:
100-a substrate; 101-a gate oxide layer; 102-a polysilicon layer; 103—a bottom antireflective layer; 104-a photoresist layer; 105-native oxide.
Detailed Description
In order to make the contents of the present invention more clear and understandable, the contents of the present invention will be further described with reference to the accompanying drawings. Of course, the invention is not limited to this particular embodiment, and common alternatives known to those skilled in the art are also encompassed within the scope of the invention.
In the following description, the present invention will be described in detail with reference to the drawings, which are not to be construed as limiting the invention, for the purpose of illustration and not as an actual scale.
For ease of description, some embodiments of the invention may use spatially relative terms such as "above" …, "" below "…," "top," "below," and the like to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures of the embodiments. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or components described as "below" or "beneath" other elements or components would then be oriented "above" or "over" the other elements or components. The terms "first," "second," and the like, herein below, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
Fig. 2 is a flow chart of a method for manufacturing a gate according to the present embodiment, as shown in fig. 2, the method for manufacturing a gate according to the present embodiment includes the following steps:
step S01: providing a substrate, and sequentially forming a gate oxide layer and a polysilicon layer on the substrate;
step S02: etching the polysilicon layer to form a grid electrode;
step S03: performing first isotropic etching to remove the native oxide on the side wall of the grid electrode; the method comprises the steps of,
step S04: and performing a second isotropic etching to remove the stripe morphology of the side wall of the grid electrode.
Fig. 3A to fig. 3D are schematic structural diagrams of steps corresponding to a method for manufacturing a gate according to an embodiment of the invention. Referring to fig. 2, and referring to fig. 3A to 3D, a method for manufacturing a gate according to the present invention is described in detail.
First, referring to fig. 3A, step S01 is performed to provide a substrate 100, and a gate oxide layer 101 and a polysilicon layer 102 are sequentially formed on the substrate 100.
Specifically, a substrate 100 is provided, where the substrate 100 may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi) or silicon carbide (SiC), and may also be Silicon On Insulator (SOI), germanium On Insulator (GOI); or may be other materials such as III-V compounds such as gallium arsenide. The substrate 100 in this embodiment is only exemplified by a silicon substrate, and the present invention is not limited thereto.
Further, in this embodiment, taking an RFLDMOS (Radio Frequency Lateral Double-diffused MOSFET) as an example, an epitaxial layer is formed in the substrate 100, a channel region and a drift region are formed in the epitaxial layer, an active region and a body region are formed in the channel region, a drain region is formed at one side of the drift region, and a gate oxide layer (GOX) 101 is formed on the epitaxial layer. The epitaxial layer, the channel region, the active region, the body region, the drift region and the drain region are formed by adopting a conventional method in an RFLDMOS manufacturing process, and are not described in detail herein and are not marked in the drawings.
Next, referring to fig. 3A and 3B, step S02 is performed to etch the polysilicon layer 102 to form a gate.
Specifically, the process of forming the gate electrode by etching the polysilicon layer 102 includes:
forming a patterned bottom anti-reflection layer 103 and a photoresist layer 104 on the polysilicon layer 102;
the polysilicon layer 102 is etched using the patterned bottom anti-reflective layer 103 and photoresist layer 104 as a mask.
Wherein etching the polysilicon layer 102 includes: pre-etching, main etching, landing etching and over-etching. Pre-etching (Oxide Breakthrough) a natural oxide layer (not shown) covering the surface of the polysilicon layer to be etched is removed by plasma of an etching gas, for example, a fluorine-based gas is selected; main etching (Main etching) under low pressure with high density plasma to react with polysilicon layer without damaging gate oxide layer, such as Cl 2 Etching with HBr gas; landing etching (Soft-landing etching), wherein the high selectivity ratio of the gate oxide layer ensures that the gate oxide layer is not damaged, so that the polysilicon etching reaches an etching end point (the etching end point is automatically detected by an end point monitoring device); over etching (Over)Etch), removing Etch residues and remaining polysilicon, which requires a sufficient selectivity to the underlying material, typically using HBr and O 2 And the combination is carried out, the selection ratio of the oxide is increased, and the damage to the gate oxide layer is avoided.
In this embodiment, the gate oxide layer 101, the polysilicon layer 102, the bottom anti-reflection layer (Bottom Anti Reflective coating, BARC) 103 and the photoresist layer (PR) 104 are stacked in order to form a gate stack film. Wherein the thickness of the gate oxide layer is
For example +.>
The gate oxide layer has a gradient under the formed gate, and the thickness of the gate oxide layer near the drain region is larger than that near the source region, and the thickness of the polysilicon layer is
For example +.>
The bottom anti-reflection layer has a thickness of +.>
For example, as
Further, after the polysilicon etching, the bottom anti-reflection layer of the target region is etched away by a low etching ratio reactive gas, which is a gas having an etching rate ratio of 1 to 2 for the photoresist layer 104 and the bottom anti-reflection layer 103, the low etching ratio reactive gas including nitrogen. The bottom anti-reflection layer 104 is removed by etching with the reaction gas with low etching ratio, so that the probability of forming stripes of patterns formed by etching can be reduced, and the reliability of the device is improved.
Next, referring to fig. 3C and 3D, step S03 is performed, and a first isotropic etching is performed to remove the native oxide of the gate sidewall.
In the above polysilicon etching process, the stripe (formation) phenomenon of the sidewall of the polysilicon gate formed by main etching is serious, and a layer of Native oxide 105 is formed on the sidewall of the gate, which results in that the subsequent over-etching of polysilicon cannot improve the stripe morphology of the sidewall, thereby causing trouble to the sidewall and the bottom morphology of the gate.
The first isotropic etching uses low bias power and fluorine-based etching gas to etch and remove part of the gate oxide layer (GOX) and the native oxide 105 on the side wall of the polysilicon gate, wherein the etching selectivity is improved and the lateral etching is enhanced by adjusting the etching gas and the bias voltage. In this embodiment, the bias power is, for example, 50W to 100W, and the fluorine-based gas includes CF 4 、CH 2 F 2 、CHF 3 One or a combination of at least two of the fluorine-based gases, e.g. CF 4 。
After etching is performed by the etching gas containing fluorine, the characteristic dimension (critical dimension, CD) of the etched gate pattern can be adjusted, so that the etching morphology is better, and the reliability of the device is improved. Alternatively, in the present embodiment, the etching time for etching by the etching gas including fluorine group is, for example, 10 seconds to 40 seconds.
Next, referring to fig. 3D, step S04 is performed, and a second isotropic etching is performed to remove the stripe shape of the gate sidewall.
After the first isotropic etching, the gate sidewall is protected by the native oxide 105, the second isotropic etching is used to improve the gate sidewall morphology and remove the stripe (structure) morphology, and the morphology of the obtained gate sidewall is shown in fig. 4, so that the morphology of the gate sidewall is obviously improved.
The etching gas adopted in the second isotropic etching is chlorine-based gas, and the chlorine-based gas comprises Cl 2 、CH 2 Cl 2 、CH 3 One or a combination of at least two of Cl, e.g. the chlorine-based gas is Cl 2 The bias power used for etching is, for example, 120W to 200W.
Further, the gate manufacturing method provided in this embodiment further includes: and metal silicide is formed on the source region, the drain region and the grid electrode, a Faraday shielding cover is formed above the part of the grid electrode close to the drain region and the part of the drift region close to the grid electrode, and the Faraday shielding cover is stepped, so that the resistance of the Faraday shielding cover to the ground is reduced, and the broadband performance and the reliability of the device under high frequency are effectively improved.
It should be appreciated that many other layers may be present in the gate fabrication method provided in this embodiment, such as spacer elements and/or other suitable components, and are omitted from the illustration for simplicity
In summary, in the method for manufacturing a gate, after a gate is formed by etching a polysilicon layer, a first isotropic etching is performed to remove a native oxide on a sidewall of the gate, and a second isotropic etching is performed to remove a stripe shape on the sidewall of the gate. According to the invention, two-step isotropic etching is added after the grid electrode is etched, and the stripe phenomenon of the side wall of the grid electrode is eliminated by controlling the etching parameters of the two-step isotropic etching, so that the shape of the side wall of the grid electrode is improved, and the stability of a device is improved.
While the invention has been described in terms of preferred embodiments, it is not intended to be limiting. Any person skilled in the art can make many possible variations and modifications to the technical solution of the present invention or modifications to equivalent embodiments using the methods and technical contents disclosed above, without departing from the scope of the technical solution of the present invention. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
Claims (10)
1. A method for fabricating a gate, comprising:
providing a substrate, and sequentially forming a gate oxide layer and a polysilicon layer on the substrate;
etching the polysilicon layer to form a grid electrode;
performing first isotropic etching to remove the native oxide on the side wall of the grid electrode;
and performing a second isotropic etching to remove the stripe morphology of the side wall of the grid electrode.
2. The method of fabricating a gate electrode of claim 1, wherein the etching of the polysilicon layer to form the gate electrode comprises:
forming a patterned bottom anti-reflection layer and a photoresist layer on the polysilicon layer;
and etching the polysilicon layer by taking the patterned bottom anti-reflection layer and the photoresist layer as masks.
3. The method of fabricating a gate electrode according to claim 2, wherein etching the polysilicon layer comprises: pre-etching, main etching, landing etching and over-etching.
4. A method of fabricating a gate electrode according to claim 3, wherein the etching gas used for the first isotropic etching comprises a fluorine-based gas.
5. The method of manufacturing a gate electrode according to claim 4, wherein the fluorine-based gas includes CF 4 、CH 2 F 2 、CHF 3 One or a combination of at least two of the foregoing.
6. The method of manufacturing a gate electrode according to claim 4, wherein the bias power in the first isotropic etching is 50W to 100W.
7. The method of claim 6, wherein the etching gas used for the second isotropic etching comprises chlorine-based gas.
8. The method of manufacturing a gate electrode according to claim 7, wherein the chlorine-based gas includes Cl 2 、CH 2 Cl 2 、CH 3 One or a combination of at least two of Cl.
9. The method of claim 7, wherein the bias power in the second isotropic etching is 120W to 200W.
10. The method of manufacturing a gate electrode according to claim 2, wherein the gate oxide layer has a thickness of
The thickness of the polysilicon layer is +.>
The bottom anti-reflection layer has a thickness of
/>
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310090289.XA CN116093145A (en) | 2023-01-31 | 2023-01-31 | Grid manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310090289.XA CN116093145A (en) | 2023-01-31 | 2023-01-31 | Grid manufacturing method |
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| CN116093145A true CN116093145A (en) | 2023-05-09 |
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| CN202310090289.XA Pending CN116093145A (en) | 2023-01-31 | 2023-01-31 | Grid manufacturing method |
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- 2023-01-31 CN CN202310090289.XA patent/CN116093145A/en active Pending
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