CN116093065A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN116093065A CN116093065A CN202310091802.7A CN202310091802A CN116093065A CN 116093065 A CN116093065 A CN 116093065A CN 202310091802 A CN202310091802 A CN 202310091802A CN 116093065 A CN116093065 A CN 116093065A
- Authority
- CN
- China
- Prior art keywords
- substrate
- layer
- rewiring layer
- semiconductor structure
- rewiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 72
- 238000000034 method Methods 0.000 claims abstract description 31
- 238000002161 passivation Methods 0.000 claims description 41
- 229910000679 solder Inorganic materials 0.000 claims description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 238000007747 plating Methods 0.000 claims description 2
- 238000004806 packaging method and process Methods 0.000 abstract description 18
- 230000008054 signal transmission Effects 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 239000000463 material Substances 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 239000002131 composite material Substances 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 238000000465 moulding Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000011368 organic material Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- HHUIAYDQMNHELC-UHFFFAOYSA-N [O-2].[O-2].[O-2].[Al+3].[Al+3].O=[Si]=O Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3].O=[Si]=O HHUIAYDQMNHELC-UHFFFAOYSA-N 0.000 description 2
- FRIKWZARTBPWBN-UHFFFAOYSA-N [Si].O=[Si]=O Chemical compound [Si].O=[Si]=O FRIKWZARTBPWBN-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- -1 silicon dioxide-phosphorus silicon Chemical compound 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- RNFJDJUURJAICM-UHFFFAOYSA-N 2,2,4,4,6,6-hexaphenoxy-1,3,5-triaza-2$l^{5},4$l^{5},6$l^{5}-triphosphacyclohexa-1,3,5-triene Chemical compound N=1P(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP=1(OC=1C=CC=CC=1)OC1=CC=CC=C1 RNFJDJUURJAICM-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 241000724291 Tobacco streak virus Species 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000003063 flame retardant Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises the following components: and the substrate is coated on the rewiring layer on the substrate, and the rewiring layer is embedded with a conductive column and an electric connecting wire or a wiring for electrically connecting the rewiring layer with the substrate. By utilizing the scheme of the invention, high-density wire arrangement can be realized, the number of working procedures is reduced, the packaging thickness is reduced, and the electric signal transmission performance is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.
Background
The 2.5D package is an advanced heterogeneous chip package, can realize high-density circuit connection of a plurality of chips, is further integrated into one package, and has strong advantages in meeting the requirements of products on high bandwidth, low power consumption and high integration level. The 2.5D refers to a manufacturing process in which chips are not packaged first, but are arranged in parallel on the same substrate, and then connected to an interposer through a wire bonding or flip chip or through silicon via process, so that a plurality of functional chips are connected in a vertical direction. The packaging technology can reduce the packaging size area, reduce the interconnection distance between the longitudinal directions of the chips and improve the electrical performance index of the chips.
Conventional 2.5D packages are manufactured by applying an Interposer (Interposer), in particular, a plurality of chips placed side-by-side on top of the Interposer, connected by micro-bumps of the chips to wiring in the Interposer. The interposer is a silicon substrate made of silicon and organic materials, is connected with the upper layer and the lower layer through silicon through holes (Through Silicon Via, TSVs), is welded to a traditional 2D packaging substrate through tin balls, is a pipeline for transmitting electric signals of the multi-chip module in advanced packaging, can realize interconnection between chips, can also realize interconnection with the packaging substrate, and serves as a bridge between a plurality of bare chips and a circuit board. Through silicon vias are a key implementation of 2.5D packaging solutions, i.e., copper filled wafers, providing vertical interconnects through the silicon wafer die, with the shortest path to electrically connect one side of the die to the other.
The application medium layer realizes packaging, not only can the packaging size be increased, but also the transmission of the electric signals can be influenced to a certain extent, for example, the electric signals can be fuzzy and slow.
Disclosure of Invention
The embodiment of the invention provides a semiconductor structure and a manufacturing method thereof, which can realize high-density wire arrangement, reduce the number of working procedures, reduce the packaging thickness and improve the electric signal transmission performance.
Therefore, the embodiment of the invention provides the following technical scheme:
in one aspect, the present invention implements a semiconductor structure comprising: and the substrate is coated on the rewiring layer on the substrate, and the rewiring layer is embedded with a conductive column and an electric connecting wire or a wiring for electrically connecting the rewiring layer with the substrate.
Optionally, a solder resist layer is further laid between the substrate and the rewiring layer.
Optionally, a passivation layer is further applied between the substrate and the rewiring layer.
Optionally, the semiconductor structure further includes: and a chip disposed on the rewiring layer.
Optionally, the chip comprises a die and/or a passive element.
Optionally, the semiconductor structure further includes: and a filling medium filled between the chip and the rewiring layer.
Optionally, the semiconductor structure further includes: and a molding medium for coating the rewiring layer, the filling medium and the chip.
Optionally, the semiconductor structure further includes: and an electrical contact disposed under the substrate.
In another aspect, an embodiment of the present invention further provides a method for manufacturing a semiconductor structure, where the method includes:
providing a substrate;
forming a rewiring layer on the upper surface of the substrate, wherein a conductive post and an electrical connecting wire or wiring are embedded in the rewiring layer;
and electrically connecting the rewiring layer with the substrate by utilizing the conductive posts and the connecting wires or the wirings.
Optionally, the method further comprises: before forming the rewiring layer on the upper surface of the substrate, a solder resist layer is formed on the upper surface of the substrate, and the rewiring layer is formed on the solder resist layer.
Optionally, the method further comprises: before forming a rewiring layer on the upper surface of the substrate, forming a passivation layer on the upper surface of the substrate, and forming the rewiring layer on the passivation layer.
Optionally, the passivation layer is any one of the following: silicon dioxide-phosphorus silicon composite film, silicon dioxide-silicon nitride composite film, silicon dioxide-aluminum oxide composite film, polyimide film.
Optionally, the forming a rewiring layer on the passivation layer includes:
exposing and developing the passivation layer to form a photoresist pattern on the passivation layer;
and carrying out copper plating treatment on the passivation layer by taking the photoresist pattern as a mask to form a rewiring layer.
Optionally, the method further comprises: and forming solder bumps on the rewiring layer.
Optionally, the method further comprises: and arranging a chip on the rewiring layer, and filling a filling medium between the chip and the rewiring layer.
Optionally, the method further comprises: and coating the rewiring layer, the filling medium and the chip by using a molding medium.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
the semiconductor structure and the manufacturing method thereof provided by the embodiment of the invention replace an intermediate layer by utilizing the rewiring layer process on the substrate, can realize high-density wire arrangement, reduce the number of procedures, reduce the packaging thickness and improve the electric signal transmission performance. By utilizing the semiconductor structure provided by the embodiment of the invention, ultra-thin 2.5D packaging can be realized, and the requirements of products on high bandwidth, low power consumption and high integration level are met.
Further, the rewiring layer can be formed on the solder mask layer on the substrate, or the rewiring layer can be formed on the passivation layer on the substrate, so that the structural design is more flexible, and the application requirements of different products are facilitated.
Drawings
FIG. 1 is a schematic diagram of a prior art process for 2.5D packaging using an interposer;
fig. 2 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention;
FIG. 3 is a flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present invention;
fig. 4 to 11 are schematic views illustrating a specific implementation process of a semiconductor structure manufacturing method according to an embodiment of the present invention;
fig. 12 is another flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present invention.
Detailed Description
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
The process of existing 2.5D packaging of application intermediaries is briefly described below.
As shown in fig. 1, the process of applying 2.5D encapsulation of an interposer mainly includes the following three steps:
(1) Providing a substrate 11;
(2) Placing an interposer 12 on a substrate 11, and forming a through silicon via 121 on the interposer 12;
(3) A die (die) 13 and passive components (e.g., resistive, capacitive, inductive, etc.) 14 are placed on interposer 12 and connected to substrate 11 by leads 15 and through-silicon vias 121.
Interposer 12 is a silicon substrate made of silicon and organic materials and is a conduit for electrical signals transmitted by the multi-chip module. Although the interposer 12 is thin, the addition of the interposer obviously results in a larger package size and has some effect on electrical signal transmission.
Therefore, the embodiment of the invention provides a semiconductor structure and a manufacturing method thereof, wherein the rewiring layer process on the substrate is used for replacing an interposer, and the signal transmission of the multi-chip module can be realized without additionally adding a silicon substrate.
Fig. 2 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.
The semiconductor structure includes: a substrate 21, a rewiring layer 22 disposed on the substrate, wherein the rewiring layer 22 is embedded with conductive posts 26 and electrical connection lines or traces (not shown) for electrically connecting the rewiring layer 22 to the substrate 21. Of course, various through holes, buried holes or blind holes may be provided in the rewiring layer 22 to achieve connection of the wires, depending on design requirements.
The conductive pillars 26 provide a conductive function, and the material of the conductive pillars 26 may be metal or metal alloy, which is not limited in this embodiment of the present invention.
Referring to fig. 2, a chip, which may be a chip of various sizes and functions, is further provided on the rewiring layer 22. The chip may include a die (die) 23 and/or passive components (e.g., resistive, capacitive, inductive, etc.) 24 and is electrically connected to the rewiring layer 22 by leads 25. In addition, the specification and the function of the chip can be determined according to actual needs, and the embodiment of the invention is not limited.
In one non-limiting structure, a Solder Mask (SR) is further laid between the substrate 21 and the rewiring layer 22, and the rewiring layer 22 is laid on the Solder Mask.
In another non-limiting structure, a passivation layer is further applied between the substrate 21 and the rewiring layer 22, the rewiring layer 22 being applied on the passivation layer. Of course, the passivation layer may have one or more layers, which is not limited to the embodiment of the present invention.
It should be noted that the solder mask layer and the passivation layer may be formed by some existing manufacturing processes, which is not limited to the embodiment of the present invention.
In practical applications, the thickness of the rewiring layer 22 may be 5 to 15um.
The substrate 21 may be a coreless substrate or a cored substrate. In addition, the material of the substrate 21 is not limited in the embodiment of the present invention, and may include, for example, organic and/or inorganic substances, and may be a rigid material or a flexible material.
In one non-limiting embodiment, the semiconductor structure may further comprise: and a filling medium filled between the chip and the rewiring layer. The filling medium can be made of non-conductive adhesive and the like, and the embodiment of the invention is not limited.
In another non-limiting embodiment of the semiconductor structure, the semiconductor structure may further comprise: and a molding medium for coating the rewiring layer, the filling medium and the chip. The molding medium can be made of epoxy resin, flame retardant, adhesive and other materials, and the embodiment of the invention is not limited.
In another non-limiting embodiment of the semiconductor structure, as shown in fig. 2, the semiconductor structure may further comprise: and an electrical contact 27 disposed under the substrate for making electrical connection of the semiconductor structure to the outside. The electrical contact 27 may be a solder ball, bump, wire stud, wire, etc., and the embodiment of the present invention is not limited thereto.
The semiconductor structure provided by the embodiment of the invention replaces an interposer by a rewiring layer process on the substrate, can realize high-density wire arrangement, reduces the number of procedures, reduces the packaging thickness and improves the electric signal transmission performance. By utilizing the semiconductor structure provided by the embodiment of the invention, ultra-thin 2.5D packaging can be realized, and the requirements of products on high bandwidth, low power consumption and high integration level are met.
Correspondingly, the embodiment of the invention also provides a semiconductor structure manufacturing method, and as shown in fig. 3, a flowchart of the semiconductor structure manufacturing method provided by the embodiment of the invention comprises the following steps:
the substrate may be a coreless substrate or a cored substrate. In addition, the material of the substrate is not limited in the embodiment of the invention, and some conventional materials can be adopted.
of course, various through holes, buried holes or blind holes may be further provided in the rewiring layer to realize connection of the circuits according to design requirements, which is not limited in the embodiment of the present invention.
And 303, electrically connecting the rewiring layer with the substrate by utilizing the conductive posts and the connecting wires or the wirings.
In one non-limiting embodiment, the re-wiring layer may be formed by first forming a solder resist layer on the upper surface of the substrate and then re-forming the re-wiring layer on the solder resist layer.
In another non-limiting embodiment, the re-wiring layer may be formed by first forming a passivation layer on the upper surface of the substrate and then re-forming the re-wiring layer on the passivation layer.
The process flow of forming the re-wiring layer will be described in detail with reference to fig. 4 to 11, taking the example of forming the re-wiring layer on the passivation layer.
First, referring to fig. 4, a passivation layer 20 is formed by coating a specific material on a substrate 21, and as shown in fig. 5, the passivation layer 20 may be made of an inorganic material or an organic material, and a passivation protection layer made of an inorganic material includes: silicon dioxide-phosphorus silicon composite film, silicon dioxide-silicon nitride composite film, silicon dioxide-aluminum oxide composite film, etc., passivation protection layer made of organic material such as polyimide film, etc.
The passivation layer 20 may be formed by a deposition process (such as a low pressure chemical vapor deposition process or a plasma enhanced chemical vapor deposition process) or a growth process, and functions to passivate the substrate surface to prevent the substrate surface from being contaminated by the environment and damage to the substrate surface due to external force, so as to ensure the stability and reliability of the operation of the semiconductor device.
In general, a passivation layer in direct contact with a substrate is called a primary passivation layer, and a secondary passivation layer may be further applied before chip packaging, which is called a re-passivation layer, in order to improve passivation effect.
The passivation layer 20 may be a primary passivation layer or a secondary passivation layer, which is not limited to the embodiment of the present invention.
Referring to fig. 6, the passivation layer 20 is exposed and developed such that the passivation layer forms a photoresist pattern 30.
Referring to fig. 7, the passivation layer is copper-plated using the photoresist pattern 30 as a mask to form a re-wiring layer 31. The re-wiring layer 31 may be formed by electroplating or electroless plating, which is well known to those skilled in the art, and will not be described herein.
Referring to fig. 8, the rewiring layer 31 is copper plated to form a metal bump 32.
Referring to fig. 9, a photoresist 33 is coated on the metal bump 32, and the photoresist 33 may be made of the same material as the passivation layer 20 or a different material, which is not limited to the embodiment of the present invention.
Referring to fig. 10, metal bumps 32 are electroplated to form solder bumps 34. The solder bump 34 may be a copper stud bump, or may be formed by printing solder paste or directly implanting a prefabricated solder ball, and then performing a wet reflow process to form the final solder bump 34, which is not limited in this embodiment of the present invention.
Finally, the photoresist is removed, resulting in the structure shown in fig. 11.
As shown in fig. 12, another flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present invention includes the following steps:
and 124, arranging a chip on the rewiring layer, and filling a filling medium between the chip and the rewiring layer.
The chip may include a die (die) and/or a passive element (such as a resistor, a capacitor, an inductor, etc.), and in addition, the specification and the function of the chip may be determined according to actual needs, which is not limited in this embodiment of the present invention. In another non-limiting embodiment, the method may further comprise the steps of: and coating the rewiring layer, the filling medium and the chip by using a molding medium.
The semiconductor structure and the manufacturing method thereof provided by the embodiment of the invention replace an intermediate layer by utilizing the rewiring layer process on the substrate, can realize high-density wire arrangement, reduce the number of procedures, reduce the packaging thickness and improve the electric signal transmission performance. By utilizing the semiconductor structure provided by the embodiment of the invention, ultra-thin 2.5D packaging can be realized, and the requirements of products on high bandwidth, low power consumption and high integration level are met.
Further, the rewiring layer can be formed on the solder mask layer on the substrate, or the rewiring layer can be formed on the passivation layer on the substrate, so that the structural design is more flexible, and the application requirements of different products are facilitated.
It should be understood that the term "and/or" is merely an association relationship describing the associated object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In this context, the character "/" indicates that the front and rear associated objects are an "or" relationship.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (10)
1. A semiconductor structure, the semiconductor structure comprising: and the substrate is coated on the rewiring layer on the substrate, and the rewiring layer is embedded with a conductive column and an electric connecting wire or a wiring for electrically connecting the rewiring layer with the substrate.
2. The semiconductor structure of claim 1, wherein a solder mask layer is further applied between the substrate and the rewiring layer.
3. The semiconductor structure of claim 1, wherein a passivation layer is further applied between the substrate and the rewiring layer.
4. The semiconductor structure of any one of claims 1 to 3, further comprising:
and a chip disposed on the rewiring layer.
5. The semiconductor structure of claim 4, wherein the chip comprises a die and/or a passive element.
6. A method of fabricating a semiconductor structure, the method comprising:
providing a substrate;
forming a rewiring layer on the upper surface of the substrate, wherein a conductive post and an electrical connecting wire or wiring are embedded in the rewiring layer;
and electrically connecting the rewiring layer with the substrate by utilizing the conductive posts and the connecting wires or the wirings.
7. The method of fabricating a semiconductor structure of claim 6, further comprising:
before forming the rewiring layer on the upper surface of the substrate, a solder resist layer is formed on the upper surface of the substrate, and the rewiring layer is formed on the solder resist layer.
8. The method of fabricating a semiconductor structure of claim 6, further comprising:
before forming a rewiring layer on the upper surface of the substrate, forming a passivation layer on the upper surface of the substrate, and forming the rewiring layer on the passivation layer.
9. The method of fabricating a semiconductor structure according to claim 8, wherein forming a rewiring layer on the passivation layer comprises:
exposing and developing the passivation layer to form a photoresist pattern on the passivation layer;
and carrying out copper plating treatment on the passivation layer by taking the photoresist pattern as a mask to form a rewiring layer.
10. The method of fabricating a semiconductor structure of claim 9, further comprising:
and forming solder bumps on the rewiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310091802.7A CN116093065A (en) | 2023-02-09 | 2023-02-09 | Semiconductor structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310091802.7A CN116093065A (en) | 2023-02-09 | 2023-02-09 | Semiconductor structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116093065A true CN116093065A (en) | 2023-05-09 |
Family
ID=86206171
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310091802.7A Pending CN116093065A (en) | 2023-02-09 | 2023-02-09 | Semiconductor structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116093065A (en) |
-
2023
- 2023-02-09 CN CN202310091802.7A patent/CN116093065A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11664323B2 (en) | Semiconductor package and method | |
| US11990454B2 (en) | Package structure and method of forming the same | |
| US9082636B2 (en) | Packaging methods and structures for semiconductor devices | |
| US10037963B2 (en) | Package structure and method of forming the same | |
| US9748216B2 (en) | Apparatus and method for a component package | |
| US12009335B2 (en) | Structure and method of forming a joint assembly | |
| TWI523126B (en) | Semiconductor device and method of forming cavity in pcb containing encapsulant or dummy die having cte similar to cte of large array wlcsp | |
| KR20210093712A (en) | Semiconductor device and method of manufacture | |
| US12002737B2 (en) | Electronic package and method of fabricating the same | |
| TW201828370A (en) | Method of forming package-on-package structure | |
| CN106206511A (en) | Device, encapsulating structure and forming method thereof | |
| WO2021018014A1 (en) | Tsv-based multi-chip package structure and method for manufacturing same | |
| KR102386542B1 (en) | Semiconductor device and method of manufacture | |
| US9548283B2 (en) | Package redistribution layer structure and method of forming same | |
| WO2020238914A1 (en) | High-density embedded line transfer fan-out packaging structure and fabrication method therefor | |
| US20240194611A1 (en) | Semiconductor package and method | |
| CN116093065A (en) | Semiconductor structure and manufacturing method thereof | |
| TWI635546B (en) | Semiconductor structure and manufacturing method thereof | |
| TWI820317B (en) | Package component and manufacturing method thereof | |
| TWI788230B (en) | Electronic package and manufacturing method thereof | |
| CN111554676B (en) | Interposer packaging structure with enhanced local bandwidth and manufacturing method thereof | |
| TW202414701A (en) | Packaging substrate and fabrication method thereof | |
| CN113257777A (en) | Substrate structure and substrate process | |
| TW202412239A (en) | Electronic package and manufacturing method thereof | |
| TW202401684A (en) | Electronic package and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |