CN116092919A - Wafer control wafer reuse method - Google Patents
Wafer control wafer reuse method Download PDFInfo
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- CN116092919A CN116092919A CN202310096805.XA CN202310096805A CN116092919A CN 116092919 A CN116092919 A CN 116092919A CN 202310096805 A CN202310096805 A CN 202310096805A CN 116092919 A CN116092919 A CN 116092919A
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- 238000000034 method Methods 0.000 title claims abstract description 132
- 230000007547 defect Effects 0.000 claims abstract description 130
- 230000001681 protective effect Effects 0.000 claims abstract description 38
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 18
- 238000001039 wet etching Methods 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 14
- 238000005259 measurement Methods 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 239000004642 Polyimide Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 6
- 239000002245 particle Substances 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 5
- 239000003153 chemical reaction reagent Substances 0.000 claims description 2
- 238000012544 monitoring process Methods 0.000 abstract description 9
- 238000004064 recycling Methods 0.000 abstract description 7
- 235000012431 wafers Nutrition 0.000 description 210
- 239000010408 film Substances 0.000 description 76
- 238000004519 manufacturing process Methods 0.000 description 14
- 238000000151 deposition Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 7
- 238000009826 distribution Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical Vapour Deposition (AREA)
Abstract
The invention provides a reuse method of a wafer control wafer, which protects the wafer control wafer by growing a protective film layer on the wafer control wafer in advance, so that structural damage to the wafer control wafer caused by using plasma in the process of a film layer of a plasma chemical vapor deposition process is avoided in the follow-up monitoring of a CVD process, the situation that the defect value of the wafer control wafer is too high is avoided, the recycling frequency of the wafer control wafer is greatly improved, and the use cost of the wafer control wafer is reduced to a certain extent.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a wafer control wafer reuse method.
Background
The wafer control chip is a wafer for monitoring the production process, and in the manufacturing process of chips, the wafer control chip is generally used for simulating the product process firstly because the parameter monitoring difficulty of partial products is high and the monitoring means can cause adverse effects on the products, and the product wafer is used for production after various indexes meet the design requirements, so that the defective rate can be reduced. After the wafer control wafer runs out of the process to be inspected, if the process does not meet the design requirement, operators can also conduct parameter adjustment in a targeted manner so as to meet the design requirement.
The use of wafer control wafers may occur in many steps of the semiconductor process. For example: chemical vapor deposition (Chemical Vapor Deposition, CVD) processes are used to deposit thin films on wafers in many processes that require high quality defects in the deposited films, requiring daily quality monitoring of the CVD process, which results in very high wafer control wafer usage. Therefore, the wafer control wafer is required to be reusable, so as to reduce the use cost of the wafer control wafer.
In the conventional method for monitoring the quality of a CVD process using a wafer control wafer, it is necessary to use a high-density plasma process to simulate the growth of an insulating film on the wafer control wafer, remove the insulating film by using a wet etching process after the detection is completed, and then simulate the growth of the insulating film on the etched wafer control wafer for continuous use. When the insulating film is simulated to grow, the plasma can continuously bombard the wafer control wafer, so that the structural damage of the wafer control wafer can be caused, and the defect value of the wafer control wafer is too high in the repeated use process, so that the wafer control wafer cannot be used as the wafer control wafer, and otherwise, the accuracy of monitoring the quality of the CVD process can be reduced.
Therefore, how to reduce the defect value of the wafer control wafer and increase the recycling frequency of the wafer control wafer is a current problem to be solved.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for reusing a wafer control wafer, which is used for solving the problems of the prior art that the wafer control wafer is reusable for a small number of times and the use cost of the wafer control wafer is high.
To achieve the above and other related objects, the present invention provides a method for reusing a wafer control wafer, comprising the steps of:
providing a wafer control wafer, and growing a protective film layer on the wafer control wafer;
performing defect measurement on the wafer control wafer to obtain first defect information of the wafer control wafer;
forming a process film layer on the wafer control wafer, wherein the process film layer covers the protective film layer;
performing defect measurement on the wafer control wafer to obtain second defect information of the wafer control wafer;
comparing the first defect information with the second defect information to obtain defect information difference;
comparing the defect information difference with a defect standard to judge the quality of the machine;
and removing the process film layer by a wet etching process to obtain the wafer control wafer to be reused.
Optionally, the method for forming the protective film layer is a plasma enhanced chemical vapor deposition method.
Optionally, the protective film layer includes any one or a combination of silicon dioxide, silicon nitride, tantalum oxide, or polyimide.
Optionally, the thickness of the protective film layer is
Optionally, the first defect information includes a first defect image and a corresponding first defect value, and the defect includes any one or a combination of a surface defect, an epitaxial stacking defect, a scratch defect, a particle residue defect, and a slide wire defect existing on the wafer control wafer; the second defect information comprises a second defect image and a corresponding second defect value, and the defects comprise any one or combination of surface defects, epitaxial stacking defects, scratch defects, particle residue defects and slide wire defects existing on the wafer control wafer.
Optionally, the method for forming the process film layer is a high-density plasma chemical vapor deposition method.
Optionally, the process film layer includes any one or combination of silicon dioxide, silicon nitride, tantalum oxide, or polyimide.
Optionally, the thickness of the process film layer is
Optionally, the chemical reagent adopted in the wet etching process is hydrofluoric acid solution, and HF in the hydrofluoric acid solution is as follows: h 2 The ratio of O is 1:500～1：100。
optionally, after the wet etching process is performed to remove the process film layer, the method further comprises a step of removing the protection film layer.
As described above, the wafer control wafer reuse method of the invention has the following beneficial effects: the wafer control wafer is protected by growing the protective film layer on the wafer control wafer in advance, so that structural damage to the wafer control wafer due to the use of plasma in the process of the film layer of the plasma chemical vapor deposition process is avoided when the subsequent CVD process is monitored, the situation that the defect value of the wafer control wafer is too high is avoided, the recycling frequency of the wafer control wafer is greatly improved, and the use cost of the wafer control wafer is reduced to a certain extent.
Drawings
FIG. 1 is a flow chart of a method for recycling a wafer control wafer according to the present invention.
Fig. 2 to fig. 4 are schematic views illustrating the steps of the wafer control wafer recycling method according to the present invention.
Description of element reference numerals
101. Wafer control wafer
102. Protective film layer
103. Craft film layer
S1 to S7 steps
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.
It should be understood that the use of the terms "first," "second," and the like, as used herein, are merely intended to facilitate distinguishing between the above elements and not to limit the scope of the invention unless otherwise specified.
Please refer to fig. 1 to 4. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Referring to fig. 1, a flowchart of a method for reusing a wafer control wafer according to an embodiment of the present application is shown, where the method includes the following steps:
s1: providing a wafer control wafer, and growing a protective film layer on the wafer control wafer;
s2: performing defect measurement on the wafer control wafer to obtain first defect information of the wafer control wafer;
s3: forming a process film layer on the wafer control wafer, wherein the process film layer covers the protective film layer;
s4: performing defect measurement on the wafer control wafer to obtain second defect information of the wafer control wafer;
s5: comparing the first defect information with the second defect information to obtain defect information difference;
s6: comparing the defect information difference with a defect standard to judge the quality of the machine;
s7: and removing the process film layer by a wet etching process to obtain the wafer control wafer to be reused.
The following describes a method for reusing the wafer control wafer with reference to the accompanying drawings, specifically as follows:
in step S1, referring to fig. 1 and 2, a wafer control wafer is provided, and a protective film layer is grown on the wafer control wafer.
The wafer control wafer refers to: in the production process of semiconductor devices, after the parameter adjustment of each process step is completed, in order to monitor whether the parameter of each process step meets the requirement of production quality, a "bare wafer" for monitoring the process step is performed. Specifically, in this embodiment, the wafer control wafer 101 is used to monitor whether each parameter of the High Density Plasma Chemical Vapor Deposition (HDPCVD) process is properly selected, and the selected process parameters are used to deposit the thin process film 103 on the surface of the wafer control wafer 101, and then the defect values of the wafer control wafer 101 before and after the deposition of the thin process film 103 are compared and analyzed to determine whether the parameters of the High Density Plasma Chemical Vapor Deposition (HDPCVD) process meet the production requirements.
In the embodiment of the present invention, the protective film 102 is formed on the front surface of the wafer control wafer 101, and optionally, the protective film 102 is formed by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, where the thickness of the protective film 102 is
For example, it may be +.>
Or->
The thickness of the protective film 102 is not particularly limited herein. The thickness of the protective film 102 may be controlled by controlling parameters such as deposition time, deposition temperature, and ambient pressure in a plasma enhanced chemical vapor deposition process, which is well known to those skilled in the art and is not repeated hereSaid.
Optionally, the protective film layer 102 includes any one or combination of silicon dioxide, silicon nitride, tantalum oxide, or polyimide. In this embodiment, the protective film 102 is preferably silicon dioxide, on one hand, the silicon dioxide layer with a certain thickness is used to protect the wafer control wafer, so as to prevent the high density plasma from generating structural damage in the subsequent high density plasma deposition process, and on the other hand, the cost for forming the silicon dioxide layer is low, so that the manufacturing cost can be saved to a certain extent.
In step S2, defect measurement is performed on the wafer control wafer 101 to obtain first defect information of the wafer control wafer 101.
Specifically, in this embodiment, after the protective film 102 is deposited on the wafer control wafer 101, the defects of the wafer control wafer 101 are covered by the protective film 102 while partial defects remain, the wafer control wafer 101 is photographed to obtain first defect information thereof, the first defect information includes a first defect image and a corresponding first defect value, that is, initial brightness distribution information of the wafer control wafer 101 is obtained, and then the first defect image and the corresponding first defect value in the wafer control wafer 101 are obtained according to the brightness distribution information, where the defects include any one or a combination of surface defects, epitaxial stacking defects, scratch defects, particle residue defects, and slide line defects existing on the wafer control wafer 101, and the position of each defect type on the wafer control wafer 101.
In step S3, referring to fig. 1 and 3, a process film 103 is formed on the wafer control wafer 101, and the process film 103 covers the protection film 102.
In the embodiment of the present invention, a process film layer 103 is formed on the front surface of the wafer control wafer 101, where the process film layer 103 covers the protection film layer 102. Alternatively, the process film 103 is formed by high-density plasma chemical vapor deposition, whose principle is briefly described as follows: the reaction gas is dissociated into plasma by the radio frequency energy, and a deflection electric field is applied to the plasma, so that the plasma bombards the surface of the wafer control wafer 101 under the action of the electric field, thereby forming a process on the surface of the wafer control wafer 101Film layer 103. Optionally, the thickness of the process film 103 is
For example, it may be +.>
There is no limitation in this regard. The thickness of the process layer 103 may be controlled by controlling parameters such as deposition time, deposition temperature, and rf power in the hdp cvd process, which are well known to those skilled in the art and will not be described herein.
Alternatively, the process film layer 103 may include any one or a combination of silicon dioxide, silicon nitride, tantalum oxide, and polyimide, which may be selected according to practical needs, and is not limited herein.
Next, step S4 is performed to perform defect measurement on the wafer control wafer 101, so as to obtain second defect information of the wafer control wafer 101.
Specifically, in this embodiment, after the process film 103 is grown on the wafer control wafer 101, defect measurement is performed on the wafer control wafer 101 again to obtain second defect information of the wafer control wafer 101, that is, obtain second brightness distribution information of the wafer control wafer 101, and obtain a second defect image and a corresponding second defect value in the wafer control wafer 101 according to the brightness distribution information, where the second defect value includes any one or a combination of surface defects, epitaxial stacking defects, scratch defects, residual defects of particles, and sliding line defects existing on the wafer control wafer 101, and a position of each defect type on the wafer control wafer 101.
And then, executing steps S5 and S6, comparing the first defect information with the second defect information to obtain defect information difference, comparing the defect information difference with a defect standard, and judging whether the quality of the machine meets the requirement.
Specifically, in the present embodiment, the principle of obtaining the defect information difference by comparison is as follows: defects in the first defect information and defects in the second defect information are removed and are not counted in comparison calculation, defects of the same type in the first defect information are subtracted by utilizing the defects in the second defect information to obtain defect information differences, wherein the defect information differences are newly added defects, and the newly added defects can be ensured to be only sourced from the process film layer 103 grown by using the high-density plasma chemical vapor deposition method, so that whether parameter settings in the high-density plasma chemical vapor deposition process step meet quality requirements is judged by the newly added defects.
Judging whether the parameter setting of the machine meets the production requirement or not through the comparison of the newly added defects and the defect standard preset by the system, if the newly added defects are smaller than or equal to the defect standard preset by the system, the defect number of the process film layer 103 grown by the high-density plasma chemical vapor deposition method is small, namely, the parameter setting in the high-density plasma chemical vapor deposition process step meets the production quality requirement, and new wafer deposition can be performed by using the process; if the newly added defects are greater than the defect standard preset by the system, it indicates that the number of defects in the process film 103 grown by the high-density plasma chemical vapor deposition method is large, i.e., the parameter setting in the high-density plasma chemical vapor deposition process step does not meet the production quality requirement, the process parameters of the process need to be reset and the test of the wafer control wafer 101 needs to be performed again until the newly added defects are less than or equal to the defect standard preset by the system, i.e., the parameter setting in the high-density plasma chemical vapor deposition process step meets the production quality requirement, so that the process can not perform new wafer deposition.
In step S7, referring to fig. 1 and 4, a wet etching process is performed to remove the process film 103 to obtain a wafer control wafer to be reused.
Specifically, in the embodiment of the present invention, after the wet etching process is performed to remove the process film layer 103, the step of removing the protection film layer 102 is further included. Since the protective film 102 is deposited before the wafer control wafer 101 is used to form a protective effect on the wafer control wafer 101, and then the process film 103 is formed, so that the plasma does not pass through the protective film 102 to damage the body of the wafer control wafer 101, in order to ensure that the wafer control wafer 101 can be reused, the process film 102 and the protective film 103 need to be removed after the test is completed, thus obtaining a brand new wafer control wafer 101, the brand new wafer control wafer 101 can be reused for monitoring the chemical vapor deposition process, and theoretically, the wafer control wafer 101 can be used infinitely.
Optionally, the process of removing the process film 103 and the protective film 102 may be a wet etching process, the etching solution of the wet etching process is a hydrofluoric acid solution, the temperature range of the hydrofluoric acid solution is 100-250 ℃, and HF in the hydrofluoric acid solution is: h 2 The ratio of O is 1: 500-1: 100, according to the thickness of the protective film 102 formed in step S1 and the thickness of the process film 103 formed in step S3, different wet etching times and different HF and H needs to be selected 2 O ratio, thereby ensuring that the protective film layer 102 and the process film layer 103 on the wafer control wafer 101 are completely removed, and finally obtaining a new wafer control wafer 101 which can be recycled.
In this step, the advantage of selecting the wet etching process to remove the protective film 102 and the process film 103 is that: since the etching rate of the wet etching is isotropic, the wet etching time can be freely controlled according to the thickness and etching rate of the protective film layer 102 and the process film layer 103, so that the protective film layer 102 and the process film layer 103 can be completely and uniformly removed, and in addition, when the protective film layer 102 and the process film layer 103 are removed by utilizing the wet etching process, the wet etching time is strictly controlled to ensure that the wafer control wafer 101 is not damaged, so that the number of times of repeated use of the wafer control wafer 101 is increased; and the manufacturing cost of the wet etching process is relatively low, so that the production cost can be controlled to a certain extent.
In summary, according to the method for recycling the wafer control wafer, the wafer control wafer is protected by growing the protective film layer on the wafer control wafer in advance, so that structural damage to the wafer control wafer due to the use of plasma in the process of the film layer of the plasma chemical vapor deposition process is avoided, the situation that the defect value of the wafer control wafer is too high is avoided, the recycling times of the wafer control wafer are greatly improved, and the use cost of the wafer control wafer is reduced to a certain extent. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. The wafer control wafer reuse method is characterized by comprising the following steps:
providing a wafer control wafer, and growing a protective film layer on the wafer control wafer;
performing defect measurement on the wafer control wafer to obtain first defect information of the wafer control wafer;
forming a process film layer on the wafer control wafer, wherein the process film layer covers the protective film layer;
performing defect measurement on the wafer control wafer to obtain second defect information of the wafer control wafer;
comparing the first defect information with the second defect information to obtain defect information difference;
comparing the defect information difference with a defect standard to judge the quality of the machine;
and removing the process film layer by a wet etching process to obtain the wafer control wafer to be reused.
2. The reuse method according to claim 1, characterized in that: the forming method of the protective film layer is a plasma enhanced chemical vapor deposition method.
3. The reuse method according to claim 1, characterized in that: the protective film layer comprises any one or combination of silicon dioxide, silicon nitride, tantalum oxide or polyimide.
4. The reuse method according to claim 1, characterized in that: the thickness of the protective film layer is
5. The reuse method according to claim 1, characterized in that: the first defect information comprises a first defect image and a corresponding first defect value, and the defects comprise any one or combination of surface defects, epitaxial stacking defects, scratch defects, particle residue defects and slide wire defects existing on the wafer control wafer; the second defect information comprises a second defect image and a corresponding second defect value, and the defects comprise any one or combination of surface defects, epitaxial stacking defects, scratch defects, particle residue defects and slide wire defects existing on the wafer control wafer.
6. The reuse method according to claim 1, characterized in that: the forming method of the process film layer is a high-density plasma chemical vapor deposition method.
7. The reuse method according to claim 1, characterized in that: the process film layer comprises any one or combination of silicon dioxide, silicon nitride, tantalum oxide or polyimide.
8. The reuse method according to claim 1, characterized in that: the thickness of the process film layer is
9. The reuse method according to claim 1, characterized in that: the chemical reagent adopted in the wet etching process is hydrofluoric acid solution, and HF in the hydrofluoric acid solution is as follows: h 2 The ratio of O is 1: 500-1:100。
10. the reuse method according to claim 1, characterized in that: and after the wet etching process is carried out to remove the process film layer, the method further comprises the step of removing the protective film layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202310096805.XA CN116092919A (en) | 2023-02-07 | 2023-02-07 | Wafer control wafer reuse method |
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| CN202310096805.XA CN116092919A (en) | 2023-02-07 | 2023-02-07 | Wafer control wafer reuse method |
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