CN116091293B - Microminiature intelligent missile-borne computer architecture - Google Patents

Abstract

The invention relates to a microminiature intelligent missile-borne computer architecture, belongs to the technical field of precise guidance of missiles, and relates to intelligent, high-performance, small-volume and low-power consumption comprehensive information processing. The invention discloses a missile-borne microminiature intelligent computer architecture, which has the characteristics of small volume, light weight, low power consumption, high performance and intellectualization. The architecture adopts heterogeneous multi-chip design, and three types of computing chips, namely DSP, FPGA and NPU, can support complex information processing requirements on the shell under lower power consumption. For missile-borne environmental constraints, the plurality of interface chips and the plurality of processing chips are integrated through an integrated packaging technology to reduce the volume and the weight.

Description

Microminiature intelligent missile-borne computer architecture

Technical Field

The invention relates to a microminiature intelligent missile-borne computer architecture, belongs to the technical field of precise guidance of missiles, and relates to intelligent, high-performance, small-volume and low-power consumption comprehensive information processing.

Background

The guidance precision and speed of the missile are highly dependent on the processing capacity of the missile-borne computer, the missile-borne computer with high calculation power can support the requirements of quickly identifying and tracking targets, and the power system is controlled to complete guidance based on target information.

Currently, most of existing missile-borne computers adopt an architecture of embedded DSP main control and FPGA co-processing, the former is a processing core, the latter provides a peripheral communication interface for the computer and can perform simple preprocessing, and the architecture can furthest exert floating point computing capability and high-speed serial computing capability of the DSP. However, in order to improve the target detection and recognition capability, the seeker is developed towards multi-mode, multi-dimensional and multi-resolution directions, and the data amount output by the seeker per unit time is rapidly increased.

The processing architecture of the DSP+FPGA can only depend on increasing the number of DSPs to linearly improve the computing capacity, so that the volume and the weight of the missile-borne computer system are greatly increased.

In addition to missile-borne computers, missile systems have fewer, more and more than ten subsystems. The missile-borne computer is used as a system master control, needs to communicate with other subsystems of the guided missile, and on the premise of guaranteeing the reliability of interfaces, the number of peripheral interface chips of the missile-borne computer is increased by more subsystems, so that the volume and the weight of the system are obviously increased.

The missile system has the requirements of intelligent perception and intelligent decision in a complex environment, so that the real-time processing function of an intelligent algorithm based on a deep neural network becomes one of conditions which a missile-borne computer must have. The existing technology for running the deep learning algorithm by adopting the DSP chip can require more DSP quantity, and further has higher requirements on the power consumption, the volume and the weight of the system.

Furthermore, the missile-borne environment is a strongly constrained environment, with severe constraints on volume, weight and power consumption. Therefore, under the strict boundary constraint of volume, weight and power consumption, the characteristics of the prior art, such as high performance and intelligence of the missile-borne computer, are broken through, and the method is a serious challenge.

Disclosure of Invention

In order to solve the problems in the prior art, a micro intelligent missile-borne computer architecture is provided, which is a multi-chip heterogeneous missile-borne computer architecture using a system-in-package technology, and aims to adapt to the missile-borne information processing requirement and environment and remarkably reduce the volume, weight and power consumption of the system.

The technical scheme of the invention is as follows:

a microminiature intelligent missile-borne computer architecture comprises a central processing unit and an image processing unit;

the central processing unit comprises a DSP chip, an FPGA chip and an external interface chip;

the DSP chip is of a multi-core architecture and is used for bearing a computer system main control task, wherein the main control task comprises a system main control, flight control and monitoring system internal chip, the DSP chip uses a core to run main control software, and the main control software is communicated with other subsystems through an FPGA chip and an RS485 chip of the central processing unit; the DSP chip uses a core to run a flight control program, and the output of 19 paths of level signals is controlled by sending an instruction to the FPGA chip, so that the control of a power system is realized; the DSP chip uses a core to run a monitoring program, and the monitoring program monitors the working state of the computer processing chip through a system internal communication link;

the FPGA chip is connected with the external interface chip through the GPIO, the FPGA chip is connected with the central processing unit DSP chip through the EMIF interface, the FPGA chip is connected with the image processing unit DSP2 through the EMIF interface, a dual-port RAM supporting information exchange between the DSP chip and the DSP2 is arranged in the FPGA chip, level control logic is provided in the FPGA chip, the external interface chip is controlled according to instructions of the DSP chip, and further the external level is controlled, an HDLC protocol transceiver is provided in the central processing unit FPGA chip, and the DSP chip and an external subsystem are supported to communicate through an RS485 level interface;

the external interface chip comprises 20 level isolation chips, 5 switching value output chips and 14 RS485 chips, wherein each switching value output chip can support at most 6 paths of switching value signal output, and the level isolation chips and the RS485 chips jointly provide a low-speed communication interface;

because the central processing unit involves more interface chips, occupies larger area and is easy to integrate, the 8-way synchronous RS485 interface chip and the 27-way output switching value interface chip are packaged into an integrated interface SIP, so that the system volume is reduced;

the image processing unit comprises an image processing SIP (DSP 1+FPGA 1), a high-capacity FPGA chip (FPGA 2), a target identification DSP chip (DSP 2) and an NPU chip (NPU) and a storage chip;

the image processing unit board light-carrying module receives an image input by an external part system in a physical form of an optical signal, and the optical module converts the optical signal into a differential electrical signal and provides the differential electrical signal to the FPGA2. The FPGA2 receives 4 paths of image signals (2 paths of visible light images and 2 paths of infrared images) from the optical module through the SRIO interface, and four groups of DDR3 SRAM (double data rate 3 SRAM) with the size of 2GB are arranged outside the FPGA2 and used for caching original images;

the FPGA2 is connected with the NPU through a PCIE interface, provides visible light image signals for the NPU, performs distortion correction and image denoising on the 2 paths of infrared original images, and provides corrected and enhanced images for the FPGA1 through an SRIO interface;

the FPGA1 receives 2 paths of infrared images through an SRIO interface, carries out mean value filtering and median filtering on the images, then carries out binarization processing and row line segment extraction, and stores the processing results into a dual-port RAM for reading by the DSP1 through an EMIF interface;

four groups of DDR3 SRAMs are arranged outside the FPGA1, the capacity is 2GB, and the DDR3 SRAMs are used for caching batch image data;

an HDLC protocol transceiver is arranged in the FPGA1 to support the instruction communication between the DSP1 and an external part system; an HDLC protocol transceiver is arranged in the FPGA1 to support the DSP1 to respectively complete internal communication with the DSP and the FPGA 2;

the DSP1 reads a row line segment processing result of the FPGA1 through an EMIF interface and calculates a target position;

the DSP1 sends the target position information to the DSP and an external part system through an HDLC protocol transceiver provided by the FPGA1;

the DSP2 acquires the result of extracting the FPGA1 line segment through the SRIO interface, and the DSP2 performs target type identification and authenticity identification according to preset parameters by utilizing a multi-core framework of the DSP2;

the NPU acquires two paths of visible light images through a PCIE interface, and the intelligent recognition and situation awareness processing are completed by utilizing a dual-core neural network acceleration core at the bottom layer;

because the number of the chips of the image processing unit is large, the main devices are five high-performance heterogeneous processors (2 DSPs, 2 FPGAs and 1 NPU), each processor is externally provided with a large-capacity memory and a high-speed interface circuit, and a power supply chip, a clock chip, a reset chip and the like, and the total of 100 integrated circuits and thousands of resistor-capacitor parts are arranged, the number of the components is large, and the layout on a single board is difficult, so that a piece of high-performance FPGA, a piece of high-performance DSP and an external memory are packaged into the image information processing SIP.

A missile-borne microminiature intelligent computer architecture comprises a DSP chip, an FPGA chip, memory chips such as plug-in Flash, DDR SDRAM, SDR SDRAM and EMMC, interface chips such as switching value and RS485, and an NPU deep learning reasoning chip.

And adopting an NPU deep learning reasoning chip to undertake reasoning calculation of a deep neural network of the system.

The external interface chip is integrated by adopting an integrated packaging technology.

And part of the DSP, part of the FPGA chip and the plug-in memory chip are integrated by adopting an integrated packaging technology.

Advantageous effects

(1) The invention discloses a missile-borne microminiature intelligent computer architecture, which has the characteristics of small volume, light weight, low power consumption, high performance and intellectualization. The architecture adopts heterogeneous multi-chip design, and three types of computing chips, namely DSP, FPGA and NPU, can support complex information processing requirements on the shell under lower power consumption. For missile-borne environmental constraints, the plurality of interface chips and the plurality of processing chips are integrated through an integrated packaging technology to reduce the volume and the weight.

(2) The invention carries out cooperative processing on processors with various architectures, fully plays the advantages of various processing architectures, improves the performance-power consumption ratio of the system, and meets the huge information real-time processing requirement of the on-board system with lower power consumption (about 25W). The strong interface and the data stream processing capability of the FPGA are utilized to realize interface communication and image preprocessing; the high-speed serial processing task is finished by the characteristics of high main frequency and low power consumption of ARM; the parallel processing capability and the powerful floating point processing capability of the DSP are utilized to realize navigation, flight control and partial image processing tasks; and the low-power consumption real-time intelligent processing is realized by utilizing the strong matrix operation capability of the NPU.

(3) According to the invention, a plurality of isolation chips, RS485 chips and output switching value driving chips are integrated through a system level packaging technology, 39 interface chips are packaged in a volume of 25.0mm multiplied by 5.0mm, the area occupation of the chips on a PCB is reduced, and the system volume is further reduced by about 15%.

(4) According to the invention, a high-performance DSP, a high-capacity FPGA, a plurality of memories and interface chips are integrated through a system level packaging technology, 14 chips are packaged in a volume of 49.0mm multiplied by 5.7mm, the area occupation of the chips on a PCB is reduced, and the system volume is further reduced by about 8% on the basis of 2).

Drawings

FIG. 1 is a schematic diagram of a processing architecture of the present invention;

FIG. 2 is a hardware component of a CPU according to an embodiment of the present invention;

FIG. 3 is a hardware component of an image processing unit according to an embodiment of the present invention;

FIG. 4 is an integrated interface SIP internal composition;

fig. 5 is an internal composition of the image information processing SIP.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. The specific embodiments described herein are to be considered in an illustrative sense only and are not intended to limit the invention.

The functional composition of the central processing unit is shown in fig. 1, the functional composition of the image processing unit is shown in fig. 2, and the actual layout of the two processing units is shown in fig. 3 in view of the structural limitation. The detailed composition diagram of the CPU circuit is shown in FIG. 4, and the detailed composition diagram of the image processing circuit is shown in FIG. 5.

In general, as the central processing unit has more interface chips, 20 isolation chips, 14 RS485 interface chips and 5 output switching value driving chips are integrated and packaged into an integrated interface SIP, and the packaged volume is 25.0mm multiplied by 5.0mm.

Because the processing chips of the image processing unit are more, the area of a single board card is tense, a piece of high-performance FPGA, a piece of high-performance DSP and an external memory are packaged into the image information processing SIP, and the packaged volume is 49.0mm multiplied by 5.7mm.

Because the interface chip of the central processing unit is integrated to bring more PCB area to be free, in practical implementation, the DSP2 with the architecture layer being attributed to the image processing unit is placed on the PCB board of the central processing unit, so that the difficulty in layout and wiring of the PCB circuit in implementation is reduced.

According to the system architecture composition of fig. 1 and the hardware block diagram of the central processing unit shown in fig. 2, the detailed implementation information of the hardware of the central processing unit is:

the central processing unit and the image processing unit are communicated at high speed by adopting an XMC series XMC-0530-07T connector;

XC7A200T is adopted in the FPGA;

the FPGA is externally hung with Flash and the storage capacity is 512Mb;

the FPGA is externally connected with: 8 paths of synchronous isolation RS485 and 27 paths of switching value output (realized by an integrated interface SIP) and 5 paths of isolation switching value input;

DSP adopts FT-Q6713;

FT-Q6713 DSP plug-in a group of 16-bit FLASH with capacity of 128MB;

FT-Q6713 DSP plug-in 4 groups of 32-bit SDRAM, capacity 128MB;

DSP2 adopts FT-M6678;

the FT-M6678 DSP is externally hung with a group of 64-bit DDR3 with the capacity of 2GB;

FT-M6678 DSP plug-in SPI Flash with capacity of 512Mb;

the FT-M6678 DSP interfaces with an image processing unit: 1-way 4X SRIO.

The hardware block diagram of the image processing unit is shown in fig. 3, and the detailed implementation information is as follows:

the image processing unit and the central processing unit are communicated at high speed by adopting an XMC series XMC-0530-03Z connector;

the FPGA2 in the image processing unit adopts XC7VX690T;

the FPGA2 is externally hung with 4 pieces of DDR3 to form 2 groups of DDR3 with 32 bits and capacity of 2GB;

the FPGA2 is externally hung with SPI Flash and the capacity is 512Mb;

the FPGA2 is externally hung with 1 optical fiber interface module, and receives four paths of image input information through 3 groups of 1X SRIOs;

the FPGA2 is communicated with the central processing unit through 1 group of 4X SRIOs and a plurality of GPIOs;

the image information processing SIP plug-in 4 pieces of DDR3, 2 groups of DDR3 with 32 bits and capacity of 2GB are formed;

the SIP plug-in 1 Flash of image information processing has 512Mb of storage capacity;

NPU adopts Haisha HI3559A, and AI calculates 4Tops;

4 pieces of DDR4 SDRAM are hung outside the NPU, and each piece of DDR4 SDRAM is 8Gb;

NPU joins 1 piece EMMC, capacity 8GB.

The detailed implementation information of the integrated interface SIP is as follows:

1) Integrating 10 GL1401 isolated chips;

2) Integrating 10 GL1402 isolation chips;

3) 14 SIT3491 RS485 chips are integrated;

4) The 5-piece SN5407 output switching value chip is integrated.

As shown in fig. 4, detailed implementation information inside the SIP chip employed by the above-described image processing unit is as follows:

the FPGA1 adopts XC7K325T;

DSP1 adopts FT-M6678;

the DSP1 is externally hung with 4 DDR3 sheets, and the capacity is 1GB;

the FPGA1 and the DSP1 are externally hung with a plurality of interface chips, namely a USB2.0 interface 1 path, a gigabit network interface 1 path, an RS422 interface 2 path, an RS232 interface 1 path, a 1553B interface 1 path, an I2C interface 1 path, an SPI interface 1 path and an LVDS interface 182 path.

The information processing function and chip coupling relation of the architecture of the invention is briefly described as follows:

the central processing unit DSP performs navigation calculation, flight control and system main control.

(1) The DSP uses a core to run navigation calculation software, and communicates with an inertial navigation subsystem and a satellite navigation subsystem through a central processing unit FPGA and an RS485 chip to acquire navigation information and calculate positions;

(2) The DSP uses a core to run a flight control program, and controls the output of the switching value of the 19 paths of power systems by sending instructions to the FPGA, and makes a decision by combining target position information and navigation information provided by the image processing unit so as to realize the control of the power systems;

(3) The DSP uses a core to run main control software, the main control software communicates with other subsystems through an FPGA and an RS485 chip of the central processing unit to externally control 8 paths of switching value signals, and the main control software also transmits task instructions, calculation parameters and the like to other processing chips related to the invention through an internal communication link of the computer;

(4) The DSP uses a core to run a monitoring program, and the monitoring program monitors the working states of other processing chips of the computer through an internal communication link of the system.

The central processing unit FPGA realizes HDLC communication of an external interface, processing of input switching value and output switching value, timing and interrupt processing.

The FPGA chip realizes the functions of the five HDLC protocol transceivers in parallel by utilizing programmable logic resources and supports the communication of external systems;

the FPGA chip realizes the functions of two HDLC protocol transceivers in parallel by utilizing programmable logic resources, and supports communication with the FPGA1;

the FPGA chip realizes one HDLC protocol transceiver function in parallel by using programmable logic resources, and supports communication with the FPGA 2;

the FPGA chip is internally provided with a dual-port RAM for supporting the data exchange between the DSP and the image processing unit DSP2;

the FPGA chip monitors the pulse width of the input switching value by utilizing the delay stability of the FPGA chip and forms a judging result to be provided for the DSP;

the FPGA chip generates output switching value according to a DSP instruction by utilizing the time delay stability of the FPGA chip, and specifically comprises an infrared image exposure signal, a visible light image exposure signal, a communication emission enabling signal, a communication synchronization time synchronizing signal, a satellite time synchronizing pulse forwarding signal, an axial separation ignition signal, an attitude and orbit control ignition signal, a test termination signal and 19 paths of power control signals;

the FPGA chip generates timing signals and interrupt signals according to the DSP instructions and sends the timing signals and the interrupt signals to the DSP chip through a special IO port of the DSP.

The image processing unit FPGA2 receives an original image and performs preprocessing.

The FPGA2 chip receives four paths of input image signals from the optical module through the SRIO interface;

the FPGA2 chip utilizes a large amount of internal programmable logic resources to realize distortion correction of four paths of high-resolution images;

the FPGA2 chip utilizes a large amount of internal programmable logic resources to realize denoising of four paths of high-resolution images;

the FPGA2 chip provides two paths of visible light images for the NPU through the PCIE high-speed interface;

the FPGA2 chip provides two paths of infrared images for the FPGA1 of the image processing SIP through the SRIO high-speed interface;

the FPGA2 chip forwards exposure signals of the two paths of images to the FPGA1 of the image processing SIP through the GPIO interface.

The image processing unit FPGA1 extracts target features and completes target detection tasks in a matching way.

An HDLC transceiver is arranged in the FPGA1 and can complete communication with a central processing unit FPGA through a GPIO interface;

an HDLC transceiver is arranged in the FPGA1 and can support the DSP1 and the seeker system to complete instruction communication;

the FPGA1 chip monitors exposure signals of the FPGA2 in real time and receives infrared image data from the FPGA2 through the SRIO high-speed interface;

the FPGA1 chip performs mean value filtering and median value filtering on two paths of infrared images in parallel by utilizing a large amount of internal programmable logic resources;

the FPGA1 chip carries out binarization processing on the filtering result by utilizing a large amount of internal programmable logic resources;

the FPGA1 chip extracts a row line segment of the binarization processing result by utilizing a large amount of internal programmable logic resources;

the FPGA1 chip is internally provided with a double-port RAM for storing the result after the line segment extraction, so that the DSP1 can read the result through an EMIF interface.

The image processing unit DSP1 runs target detection and tracking software, detects and tracks a target according to the calculation result of the FPGA1, and returns the detection and tracking result to the central processing unit DSP.

The DSP1 acquires the extracted line segment through an EMIF interface, and performs target position detection by using two processing cores;

the DSP1 utilizes two processing cores to track the target position in real time;

the DSP1 utilizes a core to transmit detection and tracking information to a central processing unit DSP in real time through an HDLC transceiver arranged in the FPGA1;

the DSP1 is communicated with an external seeker system through an EMIF interface and an HDLC transceiver arranged in the FPGA1.

And the image processing unit DSP2 runs target recognition software, and the 8-core acceleration vector operation is utilized to finish the judgment and the identification of the true or false of the target type.

The DSP2 is connected with the central processing unit FPGA through an EMIF interface, and the data exchange with the central processing unit DSP is completed by means of the double-port RAM arranged in the CPU;

the DSP2 is connected with the FPGA2 through an SRIO high-speed interface to acquire four paths of original images and preprocessed images;

the DSP2 is connected with the FPGA1 through an SRIO high-speed interface to acquire target position information.

The NPU chip of the image processing unit runs a target detection and tracking algorithm based on deep learning, and intelligently processes two paths of visible light images.

The NPU chip acquires visible light image data from the FPGA2 through a PCIE interface;

the NPU chip utilizes an ARM processing core and a dual-core neural network acceleration engine to run an intelligent algorithm, and performs target detection tracking and situation analysis on two paths of visible light images in real time;

the NPU chip sends target information to the FPGA2 chip through the SPI interface, the target information is forwarded to the FPGA chip through the GPIO and HDLC protocol, and the central processing unit DSP can finally read the information processing result of the NPU from the FPGA chip.

All the DSP, FPGA and NPU chips are used for carrying out internal high-speed and low-speed communication tasks which are adaptive to information processing requirements.

With reference to fig. 3, the above-mentioned high-low speed communication task is specifically implemented as follows:

the DSP in the central processing unit is communicated with the FPGA through an EMIF bus, and functions of timing, interruption and the like are realized through GPIO;

the DSP2 in the central processing unit communicates with the FPGA through an EMIF bus, and functions of timing, interruption and the like are realized through GPIO;

the DSP and the DSP2 communicate through a serial port;

the FPGA and the FPGA2 communicate through GPIO and HDLC protocols;

the FPGA2 and the DSP2 communicate through an SRIO bus;

the FPGA1 and the DSP2 are communicated through an SRIO bus;

the DSP1 in the image processing SIP communicates with the FPGA1 through an EMIF bus, and functions of timing, interruption and the like are realized through GPIO;

the DSP1 in the image processing SIP communicates with the FPGA2 through an EMIF bus, and can also communicate through a PCIE bus;

the FPGA1 in the image processing SIP is respectively communicated with the FPGA and the DSP2 through an SRIO bus;

the FPGA1 in the image processing SIP communicates with the FPGA and the DSP through serial ports;

the FPGA1 in the image processing SIP communicates with the FPGA2 through an SRIO bus;

the NPU communicates with the FPGA2 through a PCIE bus, and can also communicate with the FPGA2 through a serial port and an SPI bus;

the above embodiments are merely for illustrating the design concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement the same, the scope of the present invention is not limited to the above embodiments. Therefore, all equivalent changes or modifications according to the principles and design ideas of the present invention are within the scope of the present invention.

Claims (5)

1. The utility model provides a microminiature intelligence missile-borne computer framework which characterized in that: the missile-borne computer framework comprises a central processing unit and an image processing unit;

the central processing unit comprises a DSP chip, an FPGA chip and an external interface chip;

the DSP chip is a multi-core architecture and is used for bearing a computer system main control task, wherein the main control task comprises a system main control, flight control and monitoring system internal chip;

the DSP chip uses a core to run main control software, and the main control software communicates with other subsystems through an FPGA chip and an RS485 chip of the central processing unit;

the DSP chip uses a core to run a flight control program, and the output of 19 paths of level signals is controlled by sending an instruction to the FPGA chip, so that the control of a power system is realized;

the DSP chip uses a core to run a monitoring program, and the monitoring program monitors the working state of the computer processing chip through a system internal communication link;

the image processing unit comprises an image processing SIP, an FPGA chip, a target identification DSP chip, an NPU chip and a storage chip, wherein the SIP comprises a DSP1+FPGA1, the FPGA chip is named as FPGA2, and the target identification DSP chip is named as DSP2;

the image processing unit board light-carrying module receives an image input by an external part system in a physical form of an optical signal, the optical module converts the optical signal into a differential electrical signal and provides the differential electrical signal for the FPGA2, the FPGA2 receives 4 paths of image signals, 2 paths of visible light images and 2 paths of infrared images from the optical module through an SRIO interface, and four groups of DDR3 SRAM (double data rate) with the size of 2GB are arranged outside the FPGA2 and used for caching an original image;

the FPGA2 is connected with the NPU through a PCIE interface, provides visible light image signals for the NPU, performs distortion correction and image denoising on the 2 paths of infrared original images, and provides corrected and enhanced images for the FPGA1 through an SRIO interface;

the FPGA1 receives 2 paths of infrared images through an SRIO interface, carries out mean value filtering and median filtering on the images, then carries out binarization processing and row line segment extraction, and stores the processing results into a dual-port RAM for reading by the DSP1 through an EMIF interface;

four groups of DDR3 SRAMs are arranged outside the FPGA1, the capacity is 2GB, and the DDR3 SRAMs are used for caching batch image data;

an HDLC protocol transceiver is arranged in the FPGA1 to support the instruction communication between the DSP1 and an external part system; an HDLC protocol transceiver is arranged in the FPGA1 to support the DSP1 to respectively complete internal communication with the DSP and the FPGA2.

2. The miniature intelligent missile-borne computer architecture of claim 1, wherein:

the FPGA chip is connected with the external interface chip through the GPIO, the FPGA chip is connected with the central processing unit DSP chip through the EMIF interface, the FPGA chip is connected with the image processing unit DSP2 through the EMIF interface, a dual-port RAM supporting information exchange between the DSP chip and the DSP2 is arranged in the FPGA chip, level control logic is provided in the FPGA chip, the external interface chip is controlled according to instructions of the DSP chip, and further the external level is controlled, an HDLC protocol transceiver is provided in the central processing unit FPGA chip, and communication between the DSP chip and an external subsystem is supported through an RS485 level interface.

3. A miniature intelligent missile-borne computer architecture according to claim 1 or 2, wherein:

the external interface chips comprise 20 level isolation chips, 5 switching value output chips and 14 RS485 chips, wherein each switching value output chip can support at most 6 paths of switching value signal output, and the level isolation chips and the RS485 chips jointly provide a low-speed communication interface.

4. A miniature intelligent missile-borne computer architecture according to claim 3, wherein:

the 8-path synchronous RS485 interface chip and the 27-path output switching value interface chip are packaged into an integrated interface SIP.

5. The miniature intelligent missile-borne computer architecture of claim 1, wherein:

the DSP1 reads a row line segment processing result of the FPGA1 through an EMIF interface and calculates a target position;

the DSP1 sends the target position information to the DSP and an external part system through an HDLC protocol transceiver provided by the FPGA1;

the DSP2 acquires the result of extracting the FPGA1 line segment through the SRIO interface, and the DSP2 performs target type identification and authenticity identification according to preset parameters by utilizing a multi-core framework of the DSP2;

the NPU acquires two paths of visible light images through a PCIE interface, and the intelligent recognition and situation awareness processing is completed by utilizing a dual-core neural network acceleration core at the bottom layer.