CN116090401A

CN116090401A - Standard cell, design method of integrated circuit, standard cell, and integrated circuit

Info

Publication number: CN116090401A
Application number: CN202310027813.9A
Authority: CN
Inventors: 赵强; 郑军
Original assignee: Shanghai Weijing Technology Co ltd
Current assignee: Shanghai Weijing Technology Co ltd
Priority date: 2023-01-09
Filing date: 2023-01-09
Publication date: 2023-05-09

Abstract

The application discloses a design method of a standard cell and an integrated circuit, the standard cell and the integrated circuit, and the design method of the standard cell comprises the following steps: customizing N buffers; customizing signal lines respectively connected with the N buffers, wherein the N signal lines are arranged in parallel; and a power line is arranged between each two adjacent signal lines. The method and the device can effectively reduce the coupling capacitance between the signal lines, shield the interference of the coupling capacitance to the signals, and further eliminate crosstalk noise interference.

Description

Standard cell, design method of integrated circuit, standard cell, and integrated circuit

Technical Field

The present disclosure relates to the field of integrated circuits, and in particular, to a standard cell, a design method of an integrated circuit, a standard cell, and an integrated circuit.

Background

The integrated circuit industry has entered the SoC (Systemon Chip) era of ultra-deep submicron processes, the design scale has been larger and larger, the feature size of the process has been smaller and smaller, and the integrated circuit design method faces many new challenges. Especially, as the integrated functions of the chip are continuously increased, the area of the chip is continuously increased, and a large number of long-distance connection lines are inevitably generated. When the automatic placement and routing tool routes an extra-long placement and routing path, the situations of uneven routing length, layer jump, excessive via holes and buffers are faced. Some solutions are to solve the problems of uneven tool wiring, kong Guoduo, large timing delay, etc., and to deeply customize a standard cell in an IC design. The standard unit comprises N equal-length parallel lines and a buffer correspondingly connected with each line. The developer can call the standard unit for a plurality of times in the subsequent layout and wiring stage, and put the standard unit in parallel to obtain a uniform and fixed wiring. However, in such circuits, crosstalk noise generated by the coupling capacitance between the wires can lead to a large number of timing violations, even logic errors. The crosstalk coupling between signal lines has become a problem for integrated circuit back-end design engineers to carefully consider during the design phase.

Disclosure of Invention

In view of this, the present application provides a standard cell, a design method of an integrated circuit, a standard cell, and an integrated circuit, so as to solve the problem of coupling crosstalk between signal lines during wiring of the integrated circuit.

The design method of the standard unit comprises the following steps:

customizing N buffers;

customizing signal lines respectively connected with the N buffers, wherein the N signal lines are arranged in parallel;

and a power line is arranged between each two adjacent signal lines.

Optionally, the power lines include a first power line and a second power line, the first power line and the second power line are alternately distributed, and the types of the first power line and the second power line are different.

Optionally, the first power line is a VDD line, and the second power line is a VSS line.

The application also provides a design method of the integrated circuit, which comprises the following steps:

integrating a plurality of standard cells designed by adopting the design method of any standard cell.

Optionally, the method for designing an integrated circuit further includes: and arranging the standard units in parallel to obtain a wiring structure with uniform length and uniform time sequence delay.

Optionally, the method for designing an integrated circuit further includes: and extracting time sequence information of each standard unit, and generating a design layout according to the time sequence information.

The present application also provides a standard cell, comprising:

n buffers;

the signal lines are respectively connected with the N buffers, and the N signal lines are arranged in parallel;

and power supply lines respectively positioned between two adjacent signal lines.

The present application also provides an integrated circuit comprising a plurality of any of the standard cells described above.

According to the design method of the standard unit and the integrated circuit, the power line is arranged between two adjacent signal lines of each group, so that voltage drop (IR-drop) can be effectively relieved, and electromigration Effect (EM) can be avoided; the power lines are arranged between the signal lines, so that the coupling capacitance between the original signal lines can be effectively reduced, the interference of the coupling capacitance on the signals is shielded, and further, the crosstalk noise interference is eliminated; a power line is uniformly inserted between every two signal lines, redundancy design is considered, and the metal signal line has stronger electromigration resistance and can help the whole metal signal line resist the problem of disconnection caused by electromigration; the design mode of the standard cell has the advantages of short design period, low cost, high success rate, good system expansibility and the like, and when the layout design is carried out under the corresponding standard cell mode, the cells are arranged in rows according to the design targets of the interconnection requirement of the circuit, the minimization of the layout area, the optimization of time delay and the like, so that the layout design of the corresponding integrated circuit can be rapidly completed.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of wiring during the course of the inventors' study;

FIG. 2 is a flow chart of a design method of a standard cell according to an embodiment of the present application;

FIG. 3 is a standard cell routing schematic of an embodiment of the present application;

FIG. 4 is a standard cell routing schematic of another embodiment of the present application;

fig. 5 is a schematic diagram of a standard cell integrated structure according to an embodiment of the present application.

Detailed Description

The inventor researches a large-scale digital circuit, and finds how to solve the problem of long-line delay, and how to effectively reduce the problem of long-line crosstalk, which is a challenge that must be reached in the design process. As integrated circuit process nodes continue to decrease, crosstalk noise has long become a critical factor affecting chip function and performance, crosstalk being essentially an energy coupling. Crosstalk in signal line structures is basically caused by the interaction of electromagnetic fields between different interconnect structures with each other. In some schemes, the same crosstalk problem exists for uniformly fixed ultra-long distance placement and routing made up of standard cells. As shown in fig. 1: first, a relation between a victim line and an victim line is defined. In an interconnection system, an interference line refers to a line which can interfere with other wires, and a disturbed line refers to a line which suffers from interference of other wires, because signal lines interfere with each other, any one metal line is an interference line and is a disturbed line. In order to study the mutual interference interrelation between the interference line and the victim line, it is mainly considered that (1) the coupling capacitance value between the interference line and the victim line is the same. The larger the coupling capacitance value between the interference line and the disturbed line, the larger the mutual interference intensity between the interference line and the disturbed line. (2) The strength of the input signal of the disturbance line and the signal jump speed. The higher the intensity of the input signal on the interference line is, the faster the high and low level changes are; the faster the signal changes, the more noise is more easily transferred through the coupling capacitor between the two, affecting the victim line signal propagation. (3) capacitance to the substrate; the smaller the capacitance of the interfered wire to the substrate, the weaker the tamper resistance. (4) drive signal strength of the disturbed wire; the weaker the input signal strength of the disturbed wire, the more susceptible it is.

Under the current inventive process, the problem of crosstalk coupling between wires becomes very prominent. Crosstalk noise can be categorized into two categories depending on its behavior in terms of its impact on circuit performance: (1) Functional noise, as the name implies, is noise that may affect logic functions. The signal of the victim line initially remains unchanged in a static state, but due to the change in the signal of the aggressor line, a corresponding glitch is created on the corresponding victim line by the effect of the coupling capacitance. When the glitch is greater than the noise margin and is able to change the signal logic value of the original receive line, at this point if that signal value is just recorded by the memory device, the subsequent logic state will change, resulting in a functional bias. (2) Delay noise, as the name implies, is the generation of delay-related noise. When the disturbance line changes, the disturbance line is also in the process of voltage change, and the voltage change of the disturbance line may accelerate or slow down the change of the signal on the disturbance line. In particular, whether to accelerate or decelerate depends on whether the direction of signal change on the victim and victim lines is the same or opposite, and the same transition direction accelerates the signal change on the victim line, and if the transition direction is opposite, slows down the signal change on the victim line, which can lead to timing instability. In the stage of ultra-long distance layout and wiring, how to effectively reduce the influence of the connection lines on the signal integrity is a problem to be solved. But either increasing the line width or increasing the line spacing consumes more wiring resources.

In addition, in the ultra-long distance layout and wiring stage, after standard units are placed and wired, the power distribution network is modified, which is a very time-consuming and labor-consuming task. So to avoid repeated modifications and verification between the layout stage and the analysis of the layout results, the power distribution network should be designed and optimized at an early layout planning stage. In some schemes, since the distribution of the power source is not considered, the original power supply network distribution of the chip is likely to be uneven, if voltage fluctuation or burr noise occurs, misoperation of the logic function of the chip is likely to be caused, or the speed of the logic action of the chip is affected, and the performance of the chip is reduced.

Based on the finding, the power supply line is arranged between each group of two adjacent signal lines, so that voltage drop (IR-drop) can be effectively relieved, and electromigration Effect (EM) can be avoided; the power lines are arranged between the signal lines, so that the coupling capacitance between the original signal lines can be effectively reduced, the interference of the coupling capacitance on the signals is shielded, and further, the crosstalk noise interference is eliminated; a power line is uniformly inserted between every two signal lines, redundancy design is considered, and the metal signal line has stronger electromigration resistance and can help the whole metal signal line resist the problem of disconnection caused by electromigration; the design mode of the standard unit has the advantages of short design period, low cost, high success rate, good system expansibility and the like, and when the layout design is carried out under the corresponding standard unit mode, the units are arranged in rows according to the interconnection requirement of the circuit, the design targets of the minimum layout area, the time delay optimization and the like, so that the layout design of the corresponding integrated circuit can be rapidly completed.

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application. The various embodiments described below and their technical features can be combined with each other without conflict.

A first aspect of the present application provides a method for designing a standard cell, which includes S110 to S130, referring to fig. 2.

S110, customizing N buffers.

The buffer is a cell with delay driving capability, and is used for enhancing the driving force of a next-stage signal in an ultra-long-distance layout wiring structure, so as to prevent inaccurate delay information on a signal line due to too long wiring. The number of buffers N is determined by the number of specific wires, and the number of signal wires N can be determined according to the wire requirements in the design stage, so as to obtain the number of custom buffers.

S120, customizing signal lines respectively connected with the N buffers, wherein the N signal lines are arranged in parallel.

In the step S120, N signal lines with equal length and parallel to each other are customized, the line length of each signal line is the shortest possible, the necessary via holes are the smallest, the signal lines are in one-to-one correspondence with the buffers, and the N signal lines are connected to the corresponding buffers respectively. The line length of each signal line is the shortest possible, and the necessary via holes are the least, so that more accurate timing information can be obtained by calculation, specifically, the step 120 can minimize the line length of the customized standard cell according to the type and the driving capability of the buffer under the condition that the requirement of signal delay integrity in design is met, thereby minimizing the number of via holes on the signal line. The signal lines may also be referred to as interconnect lines for transmitting related signals such as electrical signals.

S130, a power line is respectively arranged between every two adjacent signal lines.

Specifically, referring to fig. 3, the power line may be located between two adjacent signal lines, parallel to the signal lines.

According to the design method of the standard unit, one power line is arranged between each group of two adjacent signal lines, so that voltage drop (IR-drop) can be effectively relieved, and electromigration Effect (EM) can be avoided; the power lines are arranged between the signal lines, so that the coupling capacitance between the original signal lines can be effectively reduced, the interference of the coupling capacitance on the signals is shielded, and further, the crosstalk noise interference is eliminated; a power line is uniformly inserted between every two signal lines, redundancy design is considered, and the metal signal line has stronger electromigration resistance and can help the whole metal signal line to resist the problem of disconnection caused by electromigration.

In one embodiment, the power lines include first power lines and second power lines that are alternately arranged, i.e., first between a first set of adjacent signal lines, then between a second set of adjacent signal lines, then between a third set of adjacent signal lines, then between a fourth set of adjacent signal lines, and so on, so that the first power lines and the second power lines are alternately arranged. Wherein the first power line and the second power line are different in type.

Specifically, the first power line is a VDD line, and the second power line is a VSS line, for example, as shown in fig. 4, two power lines, VDD and VSS, are adopted to sequentially isolate N parallel signal lines with equal length; the types of power lines used as the isolation are alternately distributed with VDD and VSS in turn, and finally appear as an alternate wiring structure with "signal line-VDD-signal line-VSS" as a period.

In this embodiment, VDD lines or VSS lines are inserted between adjacent signal lines, respectively, as shielding lines, so that coupling capacitance between the signal lines is reduced, and pulse signals generated by the coupling capacitance are reduced, so that crosstalk noise can be successfully shielded. The metal layers of the VDD line or the VSS line are inserted between the signal lines, so that the coupling capacitance between the original lines can be effectively converted into the capacitance to the ground, the interference of the coupling capacitance to the signal is shielded, and further the crosstalk noise interference is eliminated. In addition, a power line is uniformly inserted between every two signal lines, and VDD and VSS are alternately distributed, so that the crosstalk problem can be improved, and the problem of no power line resource in the design can be solved.

According to the design method of the standard unit, one power line is arranged between each group of two adjacent signal lines, so that voltage drop (IR-drop) can be effectively relieved, and electromigration Effect (EM) can be avoided; the power lines are arranged between the signal lines, so that the coupling capacitance between the original signal lines can be effectively reduced, the interference of the coupling capacitance on the signals is shielded, and further, the crosstalk noise interference is eliminated; a power line is uniformly inserted between every two signal lines, redundancy design is considered, and the metal signal line has stronger electromigration resistance and can help the whole metal signal line resist the problem of disconnection caused by electromigration; the design mode of the standard cell has the advantages of short design period, low cost, high success rate, good system expansibility and the like, and when the layout design is carried out under the corresponding standard cell mode, the cells are arranged in rows according to the design targets of the interconnection requirement of the circuit, the minimization of the layout area, the optimization of time delay and the like, so that the layout design of the corresponding integrated circuit can be rapidly completed.

In a second aspect, the present application provides a method for designing an integrated circuit, including: and integrating a plurality of standard cells designed by adopting the design method of the standard cell in any embodiment so as to obtain a corresponding integrated circuit by layout.

Alternatively, the above process of integrating a plurality of standard cells may be shown in fig. 5, and in this embodiment, the standard cells capable of eliminating crosstalk noise interference are obtained first in the IC design stage, so that the time sequence and the area utilization rate can be optimized, the wiring is ensured to be regular and uniform, no additional process is added in the whole design, and the efficiency is improved.

In one embodiment, the method for designing an integrated circuit further includes: and arranging the standard units in parallel to obtain a wiring structure with uniform length and uniform time sequence delay. Specifically, in the embodiment, a corresponding number of standard units can be placed in parallel at a designated position in advance according to actual conditions by a layout wiring PR tool, so that a high-uniformity ultra-long distance wiring with uniform length, no redundant via hole and consistent time sequence delay is obtained; the problem of long-line crosstalk can be improved as much as possible, and the problem of no power supply wiring resource is solved.

In one embodiment, the method for designing an integrated circuit further includes: and extracting time sequence information of each standard unit, and generating a design layout according to the time sequence information. Specifically, in the back-end PR tool, delay information can be automatically calculated by extracting RC parasitic parameters of specific standard units and connecting lines on a layout; i.e. the layout generated at this stage can be used to obtain timing information for the standard cells we have customized by extracting parasitic parameters on the cell interconnect lines.

According to the design method of the integrated circuit, the advantages of short design period, low cost, high success rate, good system expansion and the like of the standard cells are utilized, when the layout design is carried out in the standard cell mode, the cells are arranged in rows according to the design targets of the circuit, such as the interconnection requirement, the layout area minimization, the time delay optimization and the like, so that the layout design of the corresponding cells in the integrated circuit is completed, the timeliness in the design process of the integrated circuit can be improved, and the performance of the obtained integrated circuit is improved. In addition, the design method of the integrated circuit needs to integrate a plurality of standard cells designed by adopting the design method of the standard cell described in any one of the embodiments, and has all the advantages of the standard cell described in any one of the embodiments, which are not repeated here.

The present application provides in a third aspect a standard cell comprising:

n buffers;

According to the standard unit, one power line is arranged between each group of two adjacent signal lines, so that voltage drop (IR-drop) can be effectively relieved, electromigration Effect (EM) is avoided, the power lines are arranged between the signal lines, coupling capacitance between original signal lines can be effectively reduced, signal interference caused by the coupling capacitance is shielded, and crosstalk noise interference is further eliminated; a power line is uniformly inserted between every two signal lines, redundancy design is considered, and the metal signal line has stronger electromigration resistance and can help the whole metal signal line to resist the problem of disconnection caused by electromigration.

The standard cell may be designed by using the design method of the standard cell described in any of the foregoing embodiments, and has all the beneficial effects of the standard cell described in any of the foregoing embodiments, which are not described herein again.

In a fourth aspect, the present application provides an integrated circuit, including a plurality of standard cells according to any one of the embodiments, where the standard cells have advantages of short design period, low cost, high success rate, and good system scalability, and when performing layout design in a standard cell mode, the cells are arranged in rows according to design targets such as interconnect requirements of the circuit, minimizing layout area, and optimizing delay, so as to complete layout design of corresponding cells in the integrated circuit, which has the beneficial effects of the standard cells according to any one of the embodiments, and is not repeated herein.

Although the application has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. This application is intended to cover all such modifications and variations, and is limited only by the scope of the appended claims. In particular regard to the various functions performed by the above described components, the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the specification.

That is, the foregoing embodiments are merely examples of the present application, and are not intended to limit the scope of the patent application, and all equivalent structures or equivalent processes using the descriptions and the contents of the present application, such as the combination of technical features of the embodiments, or direct or indirect application to other related technical fields, are included in the scope of the patent protection of the present application.

In addition, in the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. In addition, the present application may use the same or different reference numerals for structural elements having the same or similar characteristics. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In this application, the term "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The previous description is provided to enable any person skilled in the art to make or use the present application. In the above description, various details are set forth for purposes of explanation. It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes have not been shown in detail to avoid unnecessarily obscuring the description of the present application. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Claims

1. A method of designing a standard cell, comprising:

customizing N buffers;

and a power line is arranged between each two adjacent signal lines.

2. The method of designing a standard cell according to claim 1, wherein the power lines include a first power line and a second power line, the first power line and the second power line are alternately distributed, and types of the first power line and the second power line are different.

3. The method of claim 2, wherein the first power line is a VDD line and the second power line is a VSS line.

4. A method of designing an integrated circuit, comprising:

integrating a plurality of standard cells designed by the design method of the standard cell according to any one of claims 1 to 3.

5. The method of designing an integrated circuit according to claim 4, further comprising:

and arranging the standard units in parallel to obtain a wiring structure with uniform length and uniform time sequence delay.

6. The method of designing an integrated circuit according to claim 4, further comprising:

and extracting time sequence information of each standard unit, and generating a design layout according to the time sequence information.

7. A standard cell, comprising:

n buffers;

8. The standard cell of claim 7, wherein the power lines comprise a first power line and a second power line, the first power line and the second power line being alternately distributed, the first power line and the second power line being of different types.

9. The standard cell of claim 8, wherein the first power line is a VDD line and the second power line is a VSS line.

10. An integrated circuit comprising a plurality of standard cells according to any one of claims 7 to 9.