CN116089778A - FFT (fast Fourier transform) internal memory multiplexing method and device - Google Patents

FFT (fast Fourier transform) internal memory multiplexing method and device Download PDF

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CN116089778A
CN116089778A CN202310384375.1A CN202310384375A CN116089778A CN 116089778 A CN116089778 A CN 116089778A CN 202310384375 A CN202310384375 A CN 202310384375A CN 116089778 A CN116089778 A CN 116089778A
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CN116089778B (en
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刘永昌
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Gaotuoxunda Beijing Microelectronics Co ltd
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Abstract

The application provides a method and a device for multiplexing memories in FFT, wherein the method comprises the following steps: obtaining a time domain signal, taking a first symbol in the time domain signal as a first input signal, performing operation processing on the first input signal to obtain a first output signal, taking a second symbol in the time domain signal as a second input signal after the operation processing on the first input signal is finished, performing frequency domain processing on the first output signal, performing operation processing on the second input signal to obtain a second output signal, and stopping performing frequency domain processing on the second output signal until the processing result starts to be output before the processing result of performing frequency domain processing on the first output signal is output. The method and the device can temporarily store the data of one symbol through the memory in the FFT, inhibit the FFT output, reduce the area and reduce the delay.

Description

FFT (fast Fourier transform) internal memory multiplexing method and device
Technical Field
The present disclosure relates to the field of signal processing technologies, and in particular, to a method and an apparatus for multiplexing a memory in an FFT.
Background
In an OFDM wireless communication baseband chip, because of the complexity of a wireless channel and a lot of interference, the complexity of a physical layer receiver algorithm is often very high, resulting in difficulty and high cost of chip implementation. For cost and performance considerations, common implementations are realized by Application Specific Integrated Circuits (ASICs). The size of the chip determines the competitiveness of the product while satisfying the physical layer performance.
The OFDM physical layer receiver algorithm flow generally includes downsampling, time domain synchronization, FFT windowing and FFT, channel estimation, frequency domain equalization and demodulation, decoding. The time domain synchronization uses training sequence in the frame to complete frame detection and find the frame beginning, and frequency offset and DC estimation are performed. Where time domain synchronization requires memory (memory) to store data, the main sources are the two time domain algorithms themselves and the frequency domain implementation delays. The FFT is used for completing the conversion from a time domain signal to a frequency domain signal and realizing OFDM demodulation, and is characterized in that after all data are input, the first data can be output, then the next data is input, and the next data is output.
Disclosure of Invention
In view of this, the embodiments of the present application provide a method, apparatus, electronic device, and storage medium for multiplexing an FFT internal memory, which can temporarily store data of one symbol through the FFT internal memory, and inhibit FFT output, so as to reduce the area and delay.
The technical scheme of the embodiment of the application is realized as follows:
in a first aspect, an embodiment of the present application provides an FFT internal memory multiplexing method, including the following steps:
acquiring a time domain signal, wherein the time domain signal comprises at least one symbol;
taking a first symbol in the time domain signal as a first input signal, carrying out operation processing on the first input signal to obtain a first output signal, and carrying out operation processing on a second input signal by taking a second symbol in the time domain signal as a second input signal when carrying out frequency domain processing on the first output signal;
and performing frequency domain processing on the first output signal, and if the operation processing on the second input signal is finished and a second output signal is obtained when the first output signal is subjected to frequency domain processing, suspending the frequency domain processing on the second output signal until the processing result of the frequency domain processing on the first output signal starts to be output.
In one possible implementation, the FFT includes a time domain memory module for providing a time domain memory function and performing time domain signal processing.
In one possible implementation manner, the FFT includes a signal input module, taking a first symbol in the time domain signal as a first input signal, and performing an operation process on the first input signal to obtain a first output signal, where the operation process includes:
the operation module inputs the first input signal into FFT through the signal input module;
and the operation module is used for carrying out operation on the first input signal and obtaining a first output signal.
In one possible implementation manner, the processing the second input signal by using the second symbol in the time domain signal as the second input signal includes:
reading a second symbol in the time domain signal through the signal input module;
and carrying out operation processing on the second input signal through the operation module.
In a possible implementation manner, the FFT includes a frequency domain processing module, and the performing frequency domain processing on the first output signal includes:
and carrying out frequency domain processing on the first output signal through the frequency domain processing module.
In one possible embodiment, if the operation processing on the second input signal ends and a second output signal is obtained when the frequency domain processing is performed on the first output signal, suspending the frequency domain processing on the second output signal until the processing result of the frequency domain processing on the first output signal starts to be output, the method includes:
and if the frequency domain processing module performs frequency domain processing on the first output signal, the operation module performs operation processing on the second input signal to obtain a second output signal, the frequency domain processing module pauses performing frequency domain processing on the second output signal, and after the frequency domain processing module finishes performing frequency domain processing on the first output signal and obtains the processing result, the processing result is output, and the frequency domain processing module performs frequency domain processing on the second output signal.
In a second aspect, an embodiment of the present application further provides an FFT internal memory multiplexing apparatus, where the apparatus includes:
a time domain storage module, configured to obtain a time domain signal, where the time domain signal includes at least one symbol;
the operation module is used for taking a first symbol in the time domain signal as a first input signal, carrying out operation processing on the first input signal to obtain a first output signal, and carrying out operation processing on a second input signal by taking a second symbol in the time domain signal as a second input signal when carrying out frequency domain processing on the first output signal;
and the frequency domain processing module is used for carrying out frequency domain processing on the first output signal, and if the operation processing on the second input signal is finished and the second output signal is obtained when the first output signal is subjected to the frequency domain processing, the frequency domain processing on the second output signal is suspended until the processing result of the first output signal subjected to the frequency domain processing starts to be output.
In a third aspect, embodiments of the present application further provide an electronic device, including: a processor, a storage medium, and a bus, the storage medium storing machine-readable instructions executable by the processor, the processor in communication with the storage medium via the bus when the electronic device is running, the processor executing the machine-readable instructions to perform the FFT internal memory multiplexing method of any of the first aspects.
In a fourth aspect, embodiments of the present application further provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the FFT internal memory multiplexing method of any of the first aspects.
The embodiment of the application has the following beneficial effects:
the invention provides a method which does not depend on the implementation mode of FFT internal storage, but can send the time domain data of 1OFDM symbol to an operation module of FFT in advance, and after the number is sent, hold the internal pipeline of FFT and prevent the FFT from outputting, to process the last symbol in the frequency domain, but the time domain can read the data of memory in the time domain to the FFT. The method has two advantages, namely, the time domain processing module does not need to wait for the completion of processing by the frequency domain processing module, the next symbol is given to the FFT by the time domain processing module, the FFT input time and the frequency domain processing time can be overlapped, delay is reduced, and the scattered memory in the FFT can be used for storing one symbol, so that memory storage of the time domain processing module is reduced.
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In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting the scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of steps S101-S103 provided in an embodiment of the present application;
FIG. 2 is a prior art schematic diagram provided by an embodiment of the present application;
FIG. 3 is a schematic diagram of the present application provided by an embodiment of the present application;
fig. 4 is a schematic structural diagram of an FFT internal memory multiplexing device according to an embodiment of the present application;
fig. 5 is a schematic diagram of a composition structure of an electronic device according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it should be understood that the accompanying drawings in the present application are only for the purpose of illustration and description, and are not intended to limit the protection scope of the present application. In addition, it should be understood that the schematic drawings are not drawn to scale. A flowchart, as used in this application, illustrates operations implemented according to some embodiments of the present application. It should be understood that the operations of the flow diagrams may be implemented out of order and that steps without logical context may be performed in reverse order or concurrently. Moreover, one or more other operations may be added to the flow diagrams and one or more operations may be removed from the flow diagrams as directed by those skilled in the art.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.
In addition, the described embodiments are only some, but not all, of the embodiments of the present application. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.
In the following description, the terms "first", "second", "third" and the like are merely used to distinguish similar objects and do not represent a particular ordering of the objects, it being understood that the "first", "second", "third" may be interchanged with a particular order or sequence, as permitted, to enable embodiments of the application described herein to be practiced otherwise than as illustrated or described herein.
It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the presence of the features stated hereinafter, but not to exclude the addition of other features.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the present application and is not intended to be limiting of the present application.
Referring to fig. 1, fig. 1 is a schematic flow chart of steps S101 to S103 of the FFT internal memory multiplexing method provided in the embodiment of the present application, and will be described with reference to steps S101 to S103 shown in fig. 1.
Acquiring a time domain signal, wherein the time domain signal comprises at least one symbol;
taking a first symbol in the time domain signal as a first input signal, carrying out operation processing on the first input signal to obtain a first output signal, and carrying out operation processing on a second input signal by taking a second symbol in the time domain signal as a second input signal when carrying out frequency domain processing on the first output signal;
and performing frequency domain processing on the first output signal, and if the operation processing on the second input signal is finished and a second output signal is obtained when the first output signal is subjected to frequency domain processing, suspending the frequency domain processing on the second output signal until the processing result of the frequency domain processing on the first output signal starts to be output.
The method for multiplexing the memory in the FFT is provided, which is independent of the implementation mode of the memory in the FFT, but can send the time domain data of 1OFDM symbol to an operation module of the FFT in advance, and the method for holding the internal pipeline of the FFT and preventing the FFT from outputting after the number is sent is provided, so that the last symbol which is not processed in the frequency domain is processed, but the time domain can read the data of the memory in the FFT. The method has two advantages, namely, the time domain processing module does not need to wait for the completion of processing by the frequency domain processing module, the next symbol is given to the FFT by the time domain processing module, the FFT input time and the frequency domain processing time can be overlapped, delay is reduced, and the scattered memory in the FFT can be used for storing one symbol, so that memory storage of the time domain processing module is reduced.
The following describes the above exemplary steps of the embodiments of the present application, respectively.
In step S101, a time domain signal is acquired, wherein the time domain signal comprises at least one symbol.
In some embodiments, the FFT includes a time domain memory module for providing time domain memory functions and performing time domain signal processing.
In step S102, a first symbol in the time domain signal is used as a first input signal, the first input signal is subjected to operation processing to obtain a first output signal, and when the first output signal is subjected to frequency domain processing, a second symbol in the time domain signal is used as a second input signal, and operation processing is performed on the second input signal.
In some embodiments, the FFT includes a signal input module, taking a first symbol in the time domain signal as a first input signal, and performing an operation on the first input signal to obtain a first output signal, including:
the operation module inputs the first input signal into FFT through the signal input module;
and the operation module is used for carrying out operation on the first input signal and obtaining a first output signal.
In some embodiments, the processing the second input signal by using the second symbol in the time domain signal as the second input signal includes:
reading a second symbol in the time domain signal through the signal input module;
and carrying out operation processing on the second input signal through the operation module.
In step S103, the first output signal is subjected to frequency domain processing, and if the operation processing on the second input signal is completed and a second output signal is obtained while the first output signal is subjected to frequency domain processing, the frequency domain processing on the second output signal is suspended until the processing result of the frequency domain processing on the first output signal starts to be output.
In some embodiments, the FFT includes a frequency domain processing module, the frequency domain processing the first output signal, comprising:
and carrying out frequency domain processing on the first output signal through the frequency domain processing module.
In some embodiments, if the operation processing on the second input signal ends and a second output signal is obtained when the first output signal is subjected to the frequency domain processing, suspending the frequency domain processing on the second output signal until the processing result of the frequency domain processing on the first output signal starts to be output, including:
and if the frequency domain processing module performs frequency domain processing on the first output signal, the operation module performs operation processing on the second input signal to obtain a second output signal, the frequency domain processing module pauses performing frequency domain processing on the second output signal, and after the frequency domain processing module finishes performing frequency domain processing on the first output signal and obtains the processing result, the processing result is output, and the frequency domain processing module performs frequency domain processing on the second output signal.
It should be noted that, in the embodiment of the present application, the FFT refers to an FFT in a physical layer chip design in an 802.11OFDM system.
Referring to fig. 2, symbol0, symbol1, symbol2 represent a Symbol after a period of time is equally divided, IN the prior art, after the first input signal sym0_fft_in (a Symbol) is processed by the time domain storage module, the first input signal sym0_fft_out is obtained by inputting the first input signal sym0_fft_in to the operation module inside the FFT for operation, at this time, because of the operation mechanism inside the FFT, the second Symbol, that is, the second input signal sym1_fft_in, needs to wait for the output of the processing result after the first output signal sym0_fft_out is processed IN the frequency domain, therefore, the period of time (the time domain storage IN the dashed frame) stores the second input signal sym1_fft_in and waits for the output module fft_out to input the first output signal m0_fft_out to the frequency domain processing module for m0 frequency domain processing, and after the processing is completed (that is, the time T2), the second input signal sym1_fft_out is output, and the second input signal sym1_fft_out is repeatedly input to the pipeline 1, and the operation is repeated after the processing is completed.
IN contrast, referring to fig. 3, after the first input signal sym0_fft_in (one symbol) is processed by the time domain storage module, the first input signal sym0_fft_in is input to the operation module inside the FFT to perform operation, so as to obtain the first output signal sym0_fft_out, at this time, the output module fft_out takes the first output signal sym0_fft_out as the input of the frequency domain processing module, and inputs the first input signal sym1_fft_in to the operation module of the FFT through the input module fft_in and participates IN operation, and then the operation module performs operation on the second input signal sym1_fft_in, so that the frequency domain processing module performs frequency domain processing on the first output signal sym0_fft_out synchronously. In general, the time of the frequency domain processing is longer than the operation time of the operation module, that is, after the second input signal sym1_fft_in is also operated, sym0 frequency domain processing is still performed, at this time, the output module needs to be stopped to output the operated second output signal sym1_fft_out, that is, hold (hold) the second output signal sym1_fft_out (fft_hold), and when the processing result is obtained (that is, the time T2 time), the time stored in the dashed frame is greatly reduced, and at this time, the processing result is output, and because the second output signal sym1_fft_out has been calculated, the second output signal sym1_fft_out is directly input by the output module fft_out as the input of the frequency domain processing module to be input into the frequency domain processing module for frequency domain processing.
In practical application, the frame structure of HE SU PPDU pre-HE (a packet type in the physical layer protocol) in 802.11ax (wifi 6 protocol) is that STF1, STF2, l-lTF1, l-lTF2, l-SIG, RLSIG, HE-SIGA1, HE-SIGA2, HE-STF are sequentially arranged, where STF1, STF2, l-lTF1, l-lTF2, l-SIG, RLSIG, HE-SIGA1, HE-SIGA2, HE-STF can be regarded as one symbol, the frequency domain processing in signaling SIG (l-SIG, RLSIG, etc.) such as mode detection delay is relatively large, new frequency domain data cannot be received, at this time, a part of data needs to be stored in the time domain, and the data of these SIG symbols can be input into FFT first, and Hold holds the output of FFT, so that memory can be saved.
The frame structure of the HE SU PPDU HE part in 802.11ax is HE-LTF and Data, and usually, the HE-LTF is used for some operations in the time domain, then the HE-LTF is used for operations in the channel, the delay is very long, the memory is often required to store the HE-LTF and the Data of the Data symbol in the time domain, and the memory capacity is very large. At this time, the frequency domain cannot receive new data, or the time domain data can be output to the memory in the FFT, and meanwhile, hold holds the output of the FFT, so that the memory can be saved.
In summary, the embodiment of the application has the following beneficial effects:
the FFT can send the time domain data of 1OFDM symbol to the FFT module in advance, after the number is sent, hold the method that the pipeline in the FFT does not let the FFT output, process the last symbol of the frequency domain, but the time domain can read the data of the memory in the FFT. The method has two advantages, namely, the time domain processing module does not need to wait for the completion of processing by the frequency domain processing module, the next symbol is given to the FFT by the time domain processing module, the FFT input time and the frequency domain processing time can be overlapped, delay is reduced, and the scattered memory in the FFT can be used for storing one symbol, so that memory storage of the time domain processing module is reduced.
Based on the same inventive concept, the embodiment of the present application further provides an FFT internal memory multiplexing device corresponding to the FFT internal memory multiplexing method in the first embodiment, and since the principle of solving the problem of the device in the embodiment of the present application is similar to that of the above-mentioned FFT internal memory multiplexing method, the implementation of the device may refer to the implementation of the method, and the repetition is omitted.
As shown in fig. 4, fig. 4 is a schematic structural diagram of an FFT internal memory multiplexing device 400 provided in an embodiment of the present application. The FFT internal memory multiplexing device 400 includes:
a time domain storage module 401, configured to obtain a time domain signal, where the time domain signal includes at least one symbol;
an operation module 402, configured to take a first symbol in the time domain signal as a first input signal, perform an operation process on the first input signal to obtain a first output signal, and perform an operation process on a second input signal with a second symbol in the time domain signal as a second input signal when performing a frequency domain process on the first output signal;
the frequency domain processing module 403 is configured to perform frequency domain processing on the first output signal, and if the operation processing on the second input signal is finished and a second output signal is obtained when the first output signal is subjected to frequency domain processing, suspend performing frequency domain processing on the second output signal until a processing result of performing frequency domain processing on the first output signal starts to be output.
Those skilled in the art will appreciate that the implementation functions of the units in the FFT internal memory multiplexing device 400 shown in fig. 4 can be understood with reference to the description of the aforementioned FFT internal memory multiplexing method. The functions of the units in the FFT internal memory multiplexing device 400 shown in fig. 4 may be implemented by a program running on a processor or by a specific logic circuit.
In one possible implementation, the time domain storage module 401 is configured to provide a time domain storage function and perform time domain signal processing.
In one possible implementation manner, the operation module 402 uses a first symbol in the time domain signal as a first input signal, performs an operation process on the first input signal, and obtains a first output signal, where the operation process includes:
the operation module inputs the first input signal into FFT through the signal input module;
and the operation module is used for carrying out operation on the first input signal and obtaining a first output signal.
In one possible implementation, the operation module 402 uses a second symbol in the time domain signal as a second input signal, and performs an operation process on the second input signal, including:
reading a second symbol in the time domain signal through the signal input module;
and carrying out operation processing on the second input signal through the operation module.
In a possible implementation manner, the frequency domain processing module 403 performs frequency domain processing on the first output signal, including:
and carrying out frequency domain processing on the first output signal through the frequency domain processing module.
In one possible implementation manner, if the frequency domain processing module 403 finishes the operation processing on the second input signal and obtains the second output signal when performing the frequency domain processing on the first output signal, pausing the frequency domain processing on the second output signal until the processing result of the frequency domain processing on the first output signal starts to be output, including:
and if the frequency domain processing module performs frequency domain processing on the first output signal, the operation module performs operation processing on the second input signal to obtain a second output signal, the frequency domain processing module pauses performing frequency domain processing on the second output signal, and after the frequency domain processing module finishes performing frequency domain processing on the first output signal and obtains the processing result, the processing result is output, and the frequency domain processing module performs frequency domain processing on the second output signal.
The FFT internal memory multiplexing device can process the last symbol which is not processed in the frequency domain by the method that the FFT internal pipeline is not output by holding after the FFT can send the time domain data of 1OFDM symbol to an operation module of the FFT in advance, but the time domain can read the data of the internal memory to the FFT. The method has two advantages, namely, the time domain processing module does not need to wait for the completion of processing by the frequency domain processing module, the next symbol is given to the FFT by the time domain processing module, the FFT input time and the frequency domain processing time can be overlapped, delay is reduced, and the scattered memory in the FFT can be used for storing one symbol, so that memory storage of the time domain processing module is reduced.
As shown in fig. 5, fig. 5 is a schematic diagram of a composition structure of an electronic device 500 according to an embodiment of the present application, where the electronic device 500 includes:
the device comprises a processor 501, a storage medium 502 and a bus 503, wherein the storage medium 502 stores machine-readable instructions executable by the processor 501, when the electronic device 500 is running, the processor 501 communicates with the storage medium 502 through the bus 503, and the processor 501 executes the machine-readable instructions to execute the steps of the FFT internal memory multiplexing method described in the embodiments of the present application.
In practice, the various components of the electronic device 500 are coupled together via a bus 503. It is understood that the bus 503 is used to enable connected communication between these components. The bus 503 includes a power bus, a control bus, and a status signal bus in addition to a data bus. But for clarity of illustration the various buses are labeled as bus 503 in fig. 5.
The electronic equipment can process the last symbol which is not processed in the frequency domain by the method that the FFT can send the time domain data of 1OFDM symbol to an operation module of the FFT in advance, and the like, after the number is sent, hold the internal pipeline of the FFT and prevent the FFT from being output, but the time domain can read the data of the memory in the time domain to the FFT. The method has two advantages, namely, the time domain processing module does not need to wait for the completion of processing by the frequency domain processing module, the next symbol is given to the FFT by the time domain processing module, the FFT input time and the frequency domain processing time can be overlapped, delay is reduced, and the scattered memory in the FFT can be used for storing one symbol, so that memory storage of the time domain processing module is reduced.
The present embodiment also provides a computer readable storage medium, where executable instructions are stored, and when the executable instructions are executed by at least one processor 501, the method for multiplexing FFT internal memory according to the present embodiment is implemented.
In some embodiments, the storage medium may be a magnetic random Access Memory (FRAM, ferromagneticRandom Access Memory), read Only Memory (ROM), programmable Read Only Memory (PROM, programmable Read-Only Memory), erasable programmable Read Only Memory (EPROM, erasableProgrammable Read-Only Memory), electrically erasable programmable Read Only Memory (EEPROM, electricallyErasable Programmable Read-Only Memory), flash Memory (Flash Memory), magnetic surface Memory, optical disk, or compact disk Read Only Memory (CD-ROM, compact Disc Read-Only Memory), or the like; but may be a variety of devices including one or any combination of the above memories.
In some embodiments, the executable instructions may be in the form of programs, software modules, scripts, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and they may be deployed in any form, including as stand-alone programs or as modules, components, subroutines, or other units suitable for use in a computing environment.
As an example, the executable instructions may, but need not, correspond to files in a file system, may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a hypertext markup Language (HTML, hyperTextMarkup Language) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub-programs, or portions of code).
As an example, executable instructions may be deployed to be executed on one computing device or on multiple computing devices located at one site or, alternatively, distributed across multiple sites and interconnected by a communication network.
The computer readable storage medium can process the last symbol which is not processed in the frequency domain by the method that the FFT can send the time domain data of 1OFDM symbol to an operation module of the FFT in advance, and the method that the FFT is not output by the internal pipeline of the FFT is held after the data is sent, but the time domain can read the data of the memory in the FFT. The method has two advantages, namely, the time domain processing module does not need to wait for the completion of processing by the frequency domain processing module, the next symbol is given to the FFT by the time domain processing module, the FFT input time and the frequency domain processing time can be overlapped, delay is reduced, and the scattered memory in the FFT can be used for storing one symbol, so that memory storage of the time domain processing module is reduced.
In several embodiments provided in the present application, it should be understood that the disclosed method and electronic device may be implemented in other manners. The above described device embodiments are only illustrative, e.g. the division of the units is only one logical function division, and there may be other divisions in practice, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the various components shown or discussed may be coupled or directly coupled or communicatively coupled to each other via some interface, whether indirectly coupled or communicatively coupled to devices or units, whether electrically, mechanically, or otherwise.
The modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical units, may be located in one place, or may be distributed over multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a non-volatile computer readable storage medium executable by a processor. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a platform server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk, etc.
The foregoing is merely a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes or substitutions are covered in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (9)

1. An FFT intra memory multiplexing method, comprising the steps of:
acquiring a time domain signal, wherein the time domain signal comprises at least one symbol;
taking a first symbol in the time domain signal as a first input signal, carrying out operation processing on the first input signal to obtain a first output signal, and carrying out operation processing on a second input signal by taking a second symbol in the time domain signal as a second input signal when carrying out frequency domain processing on the first output signal;
and performing frequency domain processing on the first output signal, and if the operation processing on the second input signal is finished and a second output signal is obtained when the first output signal is subjected to frequency domain processing, suspending the frequency domain processing on the second output signal until the processing result of the frequency domain processing on the first output signal starts to be output.
2. The method of claim 1, wherein the FFT includes a time domain memory module for providing a time domain memory function and performing time domain signal processing.
3. The method of claim 1, wherein the FFT includes a signal input module that uses a first symbol in the time domain signal as a first input signal, and wherein the performing an operation on the first input signal to obtain a first output signal includes:
the operation module inputs the first input signal into FFT through the signal input module;
and the operation module is used for carrying out operation on the first input signal and obtaining a first output signal.
4. A method according to claim 3, wherein said operating on a second symbol in said time domain signal as a second input signal comprises:
reading a second symbol in the time domain signal through the signal input module;
and carrying out operation processing on the second input signal through the operation module.
5. The method of claim 4, wherein the FFT comprises a frequency domain processing module, the frequency domain processing the first output signal comprising:
and carrying out frequency domain processing on the first output signal through the frequency domain processing module.
6. The method according to claim 5, wherein if the operation processing on the second input signal ends and a second output signal is obtained while the frequency domain processing is performed on the first output signal, suspending the frequency domain processing on the second output signal until the processing result of the frequency domain processing on the first output signal starts to be output, comprising:
and if the frequency domain processing module performs frequency domain processing on the first output signal, the operation module performs operation processing on the second input signal to obtain a second output signal, the frequency domain processing module pauses performing frequency domain processing on the second output signal, and after the frequency domain processing module finishes performing frequency domain processing on the first output signal and obtains the processing result, the processing result is output, and the frequency domain processing module performs frequency domain processing on the second output signal.
7. An intra-FFT memory multiplexing device, the device comprising:
a time domain storage module, configured to obtain a time domain signal, where the time domain signal includes at least one symbol;
the operation module is used for taking a first symbol in the time domain signal as a first input signal, carrying out operation processing on the first input signal to obtain a first output signal, and carrying out operation processing on a second input signal by taking a second symbol in the time domain signal as a second input signal when carrying out frequency domain processing on the first output signal;
and the frequency domain processing module is used for carrying out frequency domain processing on the first output signal, and if the operation processing on the second input signal is finished and the second output signal is obtained when the first output signal is subjected to the frequency domain processing, the frequency domain processing on the second output signal is suspended until the processing result of the first output signal subjected to the frequency domain processing starts to be output.
8. An electronic device, comprising: a processor, a storage medium, and a bus, the storage medium storing machine-readable instructions executable by the processor, the processor in communication with the storage medium via the bus when the electronic device is running, the processor executing the machine-readable instructions to perform the FFT internal memory multiplexing method of any of claims 1 to 6.
9. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, performs the FFT internal memory multiplexing method according to any of claims 1 to 6.
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