CN116089329A - Memory controller, memory access system, electronic device and memory training method - Google Patents
Memory controller, memory access system, electronic device and memory training method Download PDFInfo
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Abstract
The invention provides a memory controller, a memory access system, electronic equipment and a memory training method. The memory controller includes: the first sampling module is used for continuously sampling a first reference signal sent by the memory chip and judging whether sampling fails according to sampling data in the process that the memory controller reads data from the memory chip, the period and initial phase of the first reference signal are the same as those of the first data signal, and the first reference signal has a dynamically configured phase compensation value; the first phase offset determining module is used for determining a first phase offset of the middle position of the normal sampling interval of the first reference signal relative to the jump position of the first gating signal according to the phase compensation value configured when the sampling of the first reference signal fails; and the first phase compensation module is used for carrying out phase compensation on the first data signal according to the first phase offset so as to align the middle position of the first data signal with the jump position of the first gating signal.
Description
Technical Field
The present invention relates to the field of memory training technologies, and in particular, to a memory controller, a memory access system, an electronic device, and a memory training method.
Background
In the existing memory access system, a memory controller is connected with a memory chip through a memory bus, and the memory bus mainly comprises at least one data signal line and a gating signal line. Each data signal line may transmit a data signal, which in this application is represented by DQ, which is an abbreviation for data signals defined within the DDR protocol. The strobe signal line may transmit a data strobe signal (data strobe signal), which is represented in this application by DQS, which is an acronym for data strobe signal defined within the DDR protocol. DQ and DQS are both periodic signals, both typically having the same period length.
The memory controller transmits data through DQ and DQS in the process of accessing the memory chip data. In the process that the memory controller writes data into the memory chip, the memory controller can send DQ and DQS to the memory chip, the DQ can bear the data to be written into the memory chip by the memory controller, the DQS can trigger the memory chip to recognize the level state of the DQ, and then the data borne in the DQ can be written into the memory chip. In contrast, in the process that the memory controller reads data from the memory chip, the memory chip sends DQ and DQS to the memory controller, and the memory controller collects DQ data according to the DQS.
And according to the working principles of DQ and DQS, the DQ receiving end acquires the instantaneous level state of DQ as data when the DQS jumps. In order to enable DQ to have enough timing margin, the optimal working state is that the middle position of DQ is aligned to the jump position of DQS, so that the DQ receiving end has lower error rate, thereby ensuring the accuracy of data transmission. Therefore, DQS and DQ phase position adjustment, i.e., memory training, is a common strategy for improving memory reliability. The existing memory training method needs to transmit training data by utilizing a data signal line, so that the application cannot access the memory during memory training, thereby influencing the memory access performance.
Disclosure of Invention
In view of the above, the present invention provides a memory controller, a memory access system, an electronic device and a memory training method.
In a first aspect, the present invention provides a memory controller, comprising:
the first sampling module is used for continuously sampling a first reference signal sent by the memory chip and judging whether sampling fails according to sampling data in the process that the memory controller reads data from the memory chip, the period of the first reference signal is identical to that of the first data signal, the initial phase of the first reference signal is aligned with that of the first data signal, the first reference signal has a dynamically configured phase compensation value, and the first data signal is a data signal sent to the memory controller by the memory chip;
The first phase offset determining module is used for determining a first phase offset which exists at the middle position of a normal sampling interval of the first reference signal relative to the jump position of a first gating signal according to a phase compensation value configured when the sampling of the first reference signal fails, wherein the first gating signal is a gating signal sent to a memory controller by a memory chip;
and the first phase compensation module is used for carrying out phase compensation on the first data signal according to the first phase offset so as to align the middle position of the first data signal with the jump position of the first gating signal.
Optionally, the method further includes a first phase shifting module configured to configure different phase compensation values for the first reference signal during a process of reading data from the memory chip by the memory controller.
Optionally, the first phase shifting module is configured to configure different first compensation values for the first reference signal, so that the first reference signal moves different phases in a first direction until sampling of the first reference signal fails, and is configured to configure different second compensation values for the first reference signal, so that the first reference signal moves different phases in a second direction until sampling of the first reference signal fails, where the first direction and the second direction are opposite directions;
The first phase offset determining module is configured to determine, according to a first compensation value and a second compensation value configured when sampling of the first reference signal fails, a first phase offset that exists at a middle position of a normal sampling interval of the first reference signal relative to a jump position of a first strobe signal.
Optionally, the first phase shifting module is configured to increase, according to a set step length, a first compensation value of the first reference signal when the first strobe signal hops each time, so that the first reference signal moves right in sequence according to the set step length until sampling of the first reference signal fails, and decrease, according to a set step length, a second compensation value of the first reference signal when the first strobe signal hops each time, so that the first reference signal moves left in sequence according to the set step length until sampling of the first reference signal fails.
In a second aspect, the present invention provides a memory controller, comprising:
the first driving module is used for sending a second reference signal to the memory chip in the process of writing data into the memory chip by the memory controller, so that the memory chip continuously samples the second reference signal and judges whether sampling fails according to sampling data, the period of the second reference signal is the same as that of the second data signal, the initial phase of the second reference signal is aligned with the initial phase of the second data signal, the second reference signal has a dynamically configured phase compensation value, and the second data signal is the data signal sent to the memory chip by the memory controller;
A second phase offset determining module, configured to determine, according to a phase compensation value configured when sampling of the second reference signal fails, a second phase offset that exists at a middle position of a normal sampling interval of the second reference signal relative to a jump position of a second strobe signal, where the second strobe signal is a strobe signal sent to a memory chip by a memory controller;
and the second phase compensation module is used for carrying out phase compensation on the second data signal according to the second phase offset so as to align the middle position of the second data signal with the jump position of the second gating signal.
Optionally, the memory controller further comprises a second phase shifting module, configured to configure different phase compensation values for the second reference signal during the process of writing data into the memory chip by the memory controller.
Optionally, the second phase shifting module is configured to configure a third different compensation value for the second reference signal, so that the second reference signal moves different phases towards a first direction until the second reference signal fails to sample, and is configured to configure a fourth different compensation value for the second reference signal, so that the second reference signal moves different phases towards a second direction until the second reference signal fails to sample, where the first direction and the second direction are opposite directions;
The second phase offset determining module is configured to determine, according to a third compensation value and a fourth compensation value configured when the second reference signal fails to be sampled, a second phase offset that exists at a middle position of a normal sampling interval of the second reference signal relative to a jump position of a second gating signal.
Optionally, the second phase shifting module is configured to increase a third compensation value of the second reference signal according to a set step length when the second strobe signal hops each time, so that the second reference signal moves right in sequence according to the set step length until sampling of the second reference signal fails, and decrease a fourth compensation value of the second reference signal according to the set step length when the second strobe signal hops each time, so that the second reference signal moves left in sequence according to the set step length until sampling of the second reference signal fails.
In a third aspect, the present invention provides a memory access system, including a memory controller and a memory chip as provided in the first aspect, and a signal line for transmitting signals between the memory controller and the memory chip, wherein the signal line includes:
a data signal line for transmitting the first data signal;
A gate signal line for transmitting the first gate signal, an
And the reference signal line is used for transmitting the first reference signal.
In a fourth aspect, the present invention provides a memory access system, including the memory controller and the memory chip as provided in the second aspect, and a signal line for transmitting signals between the memory controller and the memory chip, wherein the signal line includes:
a data signal line for transmitting the second data signal;
a gate signal line for transmitting the second gate signal, an
And the reference signal line is used for transmitting the second reference signal.
In a fifth aspect, the present invention provides an electronic device, including the memory access system provided in the third aspect or the fourth aspect.
In a sixth aspect, the present invention provides a memory training method, applied to a memory controller, where the memory training method includes:
continuously sampling a first reference signal sent by a memory chip and judging whether sampling fails according to sampling data in the process that the memory controller reads data from the memory chip, wherein the period of the first reference signal is identical to that of a first data signal, the initial phase of the first reference signal is aligned with that of the first data signal, the first reference signal has a dynamically configured phase compensation value, and the first data signal is a data signal sent to the memory controller by the memory chip;
Determining a first phase offset of the middle position of a normal sampling interval of the first reference signal relative to a jump position of a first strobe signal according to a phase compensation value configured when the first reference signal fails to be sampled, wherein the first strobe signal is a strobe signal sent to a memory controller by a memory chip;
and performing phase compensation on the first data signal according to the first phase offset to align the middle position of the first data signal with the jump position of the first strobe signal.
In a seventh aspect, the present invention provides a memory training method, applied to a memory controller, where the memory training method includes:
in the process that the memory controller writes data into the memory chip, a second reference signal is sent to the memory chip, so that the memory chip continuously samples the second reference signal and judges whether sampling fails according to sampling data, the period of the second reference signal is identical to that of the second data signal, the initial phase of the second reference signal is aligned with that of the second data signal, the second reference signal has a dynamically configured phase compensation value, and the second data signal is a data signal sent to the memory chip by the memory controller;
Determining a second phase offset of the middle position of a normal sampling interval of the second reference signal relative to a jump position of a second strobe signal according to a phase compensation value configured when the second reference signal fails to be sampled, wherein the second strobe signal is a strobe signal sent to a memory chip by a memory controller;
and carrying out phase compensation on the second data signal according to the second phase offset so as to align the middle position of the second data signal with the jump position of the second gating signal.
Compared with the prior art, the memory controller provided by the invention uses the corresponding reference signal to perform memory training in the process that the memory controller reads data from the memory chip and in the process that the memory controller writes data into the memory chip, and the memory training and the memory access are not interfered with each other, so that the memory chip can continuously perform memory training when in operation, and the memory chip can work more stably.
Drawings
FIG. 1 is a schematic diagram of a memory controller according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a memory controller according to an embodiment of the invention;
FIG. 3 is a schematic diagram of an ideal sampling state of a data signal according to an embodiment of the present invention;
FIG. 4 is a schematic diagram showing phase shifts of reference signals and data signals relative to strobe signals according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a memory controller according to an embodiment of the invention;
FIG. 6 is a schematic diagram of a memory controller according to an embodiment of the invention;
FIG. 7 is a schematic diagram illustrating a memory access system according to an embodiment of the invention;
FIG. 8 is a schematic diagram illustrating a memory access system according to an embodiment of the invention;
fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the present application described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Some embodiments of the present invention are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
One embodiment of the present invention provides a memory controller, as shown in fig. 1, comprising:
the first sampling module 101 is configured to continuously sample a first reference signal sent by the memory chip and determine whether sampling fails according to sampling data in a process that the memory controller reads data from the memory chip, where a period of the first reference signal is the same as a period of the first data signal, an initial phase of the first reference signal is aligned with an initial phase of the first data signal, and the first reference signal has a dynamically configured phase compensation value, and the first data signal is a data signal sent by the memory chip to the memory controller;
a first phase offset determining module 102, configured to determine, according to a phase compensation value configured when sampling of the first reference signal fails, a first phase offset that exists at a middle position of a normal sampling interval of the first reference signal relative to a transition position of a first strobe signal, where the first strobe signal is a strobe signal sent by a memory chip to a memory controller;
The first phase compensation module 103 is configured to perform phase compensation on the first data signal according to the first phase offset, so that the intermediate position of the first data signal is aligned with the transition position of the first strobe signal.
Specifically, in the process that the memory controller reads data from the memory chip, the memory chip is a transmitting end, and the memory controller is a receiving end. The memory chip sends a first data signal DQ and a first strobe signal DQs to the memory controller, where the strobe signal DQs is referred to herein as a data strobe signal DQs, and both have the same meaning.
In this process, the memory chip also sends a first reference signal to the memory controller. The first sampling module 101 continuously samples the first reference signal according to the first strobe signal and judges whether sampling fails according to sampling data, and the specific sampling mode is as follows: the first sampling module 101 collects an instantaneous level state of the first reference signal as data at the time of the first strobe signal transition.
When the sampling data of the first reference signal appears in succession two identical data, for example, in succession two 0 s or in succession two 1 s, the first reference signal fails to sample. The phase compensation value at this time is a critical state of normal sampling of the first reference signal. The first sampling module 101 records the phase compensation value of the current first reference signal configuration.
After the sampling failure, the first sampling module 101 may notify the first phase offset determining module 102, for example, may send a specific sampling feedback signal, and notify the first phase offset determining module 102 of the sampling failure. At this time, the first phase offset determining module 102 needs to acquire a phase compensation value configured when the sampling of the first reference signal fails, and determine, according to the phase compensation value configured when the sampling of the first reference signal fails, a first phase offset in which an intermediate position of a normal sampling interval of the first reference signal exists with respect to a transition position of the first strobe signal. After determining the first phase offset, the first phase compensation module 103 performs phase compensation on the first data signal according to the first phase offset, so that the intermediate position of the first data signal is aligned with the transition position of the first strobe signal.
As an embodiment, as shown in fig. 2, the memory controller includes: the first phase shift module 100 is configured to configure different phase compensation values for the first reference signal during the process of reading data from the memory chip by the memory controller. The first reference signal may be made to have a dynamically configured phase compensation value by the first phase shift module 100.
Further, in one embodiment, the first phase shifting module 100 is configured to configure different first compensation values for the first reference signal, such that the first reference signal moves different phases in a first direction until sampling of the first reference signal fails, and is configured to configure different second compensation values for the first reference signal, such that the first reference signal moves different phases in a second direction until sampling of the first reference signal fails, where the first direction and the second direction are opposite directions;
the first phase offset determining module 102 is configured to determine, according to the first compensation value and the second compensation value configured when the sampling of the first reference signal fails, a first phase offset in which a middle position of a normal sampling interval of the first reference signal exists relative to a transition position of the first strobe signal.
Further, in one embodiment, the first phase shifting module 100 is configured to increase the first compensation value of the first reference signal according to a set step size when the first strobe signal hops each time, so that the first reference signal moves right in turn according to the set step size until the first reference signal fails to sample, and decrease the second compensation value of the first reference signal according to the set step size when the first strobe signal hops each time, so that the first reference signal moves left in turn according to the set step size until the first reference signal fails to sample.
It should be noted that, in the phase shifting process, the step size (may also be referred to as granularity) of the increment or decrement of the first reference signal may be configured by the memory controller according to needs. The sampling of the reference signal does not affect the sampling of the data signal.
Assuming that a first compensation value configured when sampling of the first reference signal fails is a and a second compensation value configured when sampling fails is B, the expression of the first phase offset is: (A+B)/2-A.
It will be further appreciated that the first reference signal is compensated synchronously after the first data signal is compensated according to the first phase offset. Thus, the first data signal and the first reference signal are always aligned in phase, and memory training can be continuously realized in the subsequent memory access process.
A specific example is given below to illustrate the memory training process of the memory controller.
Fig. 3 is a schematic diagram of an ideal sampling state of the data signal DQ. As shown in fig. 3, clk is a memory chip clock, DQS is a data strobe signal, dq+0 is a data signal of an initial phase, ref+0 is a reference signal of the initial phase, the reference signal ref and the data signal are all periodically alternating high and low level signals, the periods are the same, and the initial phases are aligned. In fig. 3, the intermediate position of the data signal DQ is aligned with the transition position of the strobe signal DQs, which is an ideal sampling state, without the need for compensation of the reference signal ref and the data signal.
Fig. 4 is a schematic diagram of the data signal when there is a phase shift with respect to the strobe signal, in which case the sampling position of the data signal DQ is not in the middle of the data signal DQ (the black area of the data signal indicates the target area of interest in the figure) when the strobe signal DQS jumps, so the goal of the memory training is to compensate the data signal DQ, and finally the goal is to make the jump position of the strobe signal DQS correspond to the middle position of the compensated data signal DQ.
The memory training process is briefly described as follows:
the initial phase of the reference signal ref is aligned with the initial phase of the data signal DQ;
the memory controller uses several clocks to shift ref phase to the right by 0.3 (+0.3) post-sampling failures (e.g., one clock shifted by 0.1, requiring 3 clock sampling failures);
the memory controller uses several clocks to shift ref phase left by 0.7 (-0.7) and then samples fail (similarly, if one clock is shifted by 0.1, 7 clock sampling fails);
from the expression (0.3+0.7)/2-0.3=0.2, it can be derived that the initial phase of ref has a phase shift of 0.2 to the right with respect to the optimal sampling point. The initial phase of the data signal DQ is aligned with the initial phase of ref, so the initial phase of the data signal DQ is shifted to the right by 0.2 phase with respect to the optimum sampling point.
Therefore, the ideal sampling can be realized by only shifting the data signal DQ to the left by 0.2 phase based on the initial phase. The left shifted DQ signals are not shown in fig. 4.
In the discussion above, 0.3 represents 0.3 clock cycles, 0.7 represents 0.7 clock cycles, and 0.2 represents 0.2 clock cycles.
According to the memory controller provided by the embodiment of the invention, memory training is carried out in the process that the memory controller reads data from a memory chip, the first reference signal is continuously sampled, the first phase offset which exists in the middle position of the normal sampling interval of the first reference signal relative to the jump position of the first gating signal is determined according to the phase compensation value configured when the first reference signal fails to sample, and then the first data signal is subjected to phase compensation according to the first phase offset, so that the middle position of the first data signal is aligned with the jump position of the first gating signal. Compared with the prior art, the memory training is performed by using the first reference signal, the memory training and the memory access are not interfered with each other, and the memory training can be continuously performed when the memory chip works, so that the memory chip works more stably.
In another aspect, an embodiment of the present invention provides a memory controller, as shown in fig. 5, including:
The first driving module 500 is configured to send a second reference signal to the memory chip during the process of writing data into the memory chip by the memory controller, so that the memory chip continuously samples the second reference signal and determines whether sampling fails according to the sampled data, the period of the second reference signal is the same as the period of the second data signal, the initial phase of the second reference signal is aligned with the initial phase of the second data signal, the second reference signal has a dynamically configured phase compensation value, and the second data signal is the data signal sent to the memory chip by the memory controller;
a second phase offset determining module 502, configured to determine, according to a phase compensation value configured when sampling of the second reference signal fails, a second phase offset that exists at a middle position of a normal sampling interval of the second reference signal relative to a transition position of the second strobe signal, where the second strobe signal is a strobe signal sent to the memory chip by the memory controller;
and a second phase compensation module 503, configured to perform phase compensation on the second data signal according to the second phase offset, so that the intermediate position of the second data signal is aligned with the transition position of the second strobe signal.
Specifically, in the process of writing data into the memory chip by the memory controller, the memory controller is a transmitting end, and the memory chip is a receiving end. The memory controller sends a second data signal and a second strobe signal to the memory chip. In this process, the memory controller also sends a second reference signal to the memory chip. The memory chip is provided with a corresponding sampling module, and continuously samples a second reference signal according to a second gating signal and judges whether sampling fails according to sampling data, and the specific sampling mode is as follows: and the memory chip acquires the instantaneous level state of the second reference signal as data when the second gating signal jumps.
When the sampling data of the second reference signal appears in succession two identical data, for example, in succession two 0 s or in succession two 1 s, the second reference signal fails to sample. The memory chip records the current phase compensation value of the second reference signal configuration.
After the memory chip fails to sample, the memory chip may notify the second phase offset determination module 502, for example, may send a specific sampling feedback signal to notify the second phase offset determination module 502 that the sampling fails. At this time, the second phase offset determining module 502 needs to acquire the phase compensation value configured when the second reference signal fails to sample, and determine, according to the phase compensation value configured when the second reference signal fails to sample, the second phase offset existing in the middle position of the normal sampling interval of the second reference signal relative to the jump position of the second strobe signal. After the second phase offset is determined, the second phase compensation module 503 performs phase compensation on the second data signal according to the second phase offset, so that the intermediate position of the second data signal is aligned with the transition position of the second strobe signal.
As an embodiment, as shown in fig. 6, the memory controller includes: the second phase shift module 501 is configured to configure different phase compensation values for the second reference signal during the process of writing data into the memory chip by the memory controller. The second reference signal may be made to have a dynamically configured phase compensation value by the second phase shifting module 501.
Further, in one embodiment, the second phase shifting module 501 is configured to configure a third different compensation value for the second reference signal, so that the second reference signal moves different phases in the first direction until the second reference signal fails to sample, and is configured to configure a fourth different compensation value for the second reference signal, so that the second reference signal moves different phases in the second direction until the second reference signal fails to sample, where the first direction and the second direction are opposite directions;
the second phase offset determining module 502 is configured to determine, according to the third compensation value and the fourth compensation value configured when the second reference signal fails to sample, a second phase offset that exists at a middle position of a normal sampling interval of the second reference signal relative to a transition position of the second strobe signal.
Further, in one embodiment, the second phase shifting module 501 is configured to increase the third compensation value of the second reference signal according to a set step size when the second strobe signal hops, so that the second reference signal sequentially shifts right according to the set step size until the second reference signal fails to sample, and decrease the fourth compensation value of the second reference signal according to the set step size when the second strobe signal hops, so that the second reference signal sequentially shifts left according to the set step size until the second reference signal fails to sample.
It is noted that, in the phase shifting process, the step size (also referred to as granularity) of the increment or decrement of the second reference signal may be configured by the memory controller according to needs. The sampling of the reference signal does not affect the sampling of the data signal.
Assuming that the third compensation value configured when the sampling of the second reference signal fails is a and the fourth compensation value configured when the sampling fails is B, the expression of the second phase offset is: (A+B)/2-A.
It will be further appreciated that the second reference signal is compensated synchronously after the second data signal is compensated according to the second phase offset. Thus, the second data signal and the second reference signal are always aligned in phase, and memory training can be continuously realized in the subsequent memory access process.
The memory controller according to the embodiment of the present invention may refer to the description of the foregoing embodiment for the exemplary description of the memory training process, which is not further developed herein.
The memory controller provided by the embodiment of the invention performs memory training in the process of writing data into the memory chip by the memory controller, sends the second reference signal to the memory chip, continuously samples the second reference signal by the memory chip, determines a second phase offset of the middle position of the normal sampling interval of the second reference signal relative to the jump position of the second gating signal according to the phase compensation value configured when the sampling of the second reference signal fails, and performs phase compensation on the second data signal according to the second phase offset, so that the middle position of the second data signal is aligned with the jump position of the second gating signal. Compared with the prior art, the memory training is performed by using the second reference signal, the memory training and the memory access are not interfered with each other, and the memory training can be continuously performed when the memory chip works, so that the memory chip works more stably.
In another aspect, an embodiment of the present invention provides a memory access system, as shown in fig. 7, including a memory controller and a memory chip, and a signal line for transmitting signals between the memory controller and the memory chip, wherein the memory controller is configured to perform memory training during a process that the memory controller reads data from the memory chip, and has a structure as shown in fig. 1 or fig. 2, and the signal line includes:
a data signal line for transmitting a first data signal (e.g., DQ signal);
a gate signal line for transmitting a first gate signal (e.g., DOS signal), an
A reference signal line for transmitting a first reference signal (e.g., ref signal).
In another aspect, an embodiment of the present invention provides a memory access system, as shown in fig. 8, including a memory controller and a memory chip, and a signal line for transmitting signals between the memory controller and the memory chip, where the memory controller is configured to perform memory training during a process of writing data to the memory chip by the memory controller, and has a structure as shown in fig. 5 or fig. 6, and the signal line includes:
a data signal line for transmitting a second data signal (e.g., DQ signal);
A gate signal line for transmitting a second gate signal (e.g., DOS signal), an
And a reference signal line for transmitting a second reference signal (e.g., ref signal).
It will be appreciated that in actual operation, it is necessary for a memory controller to operate bi-directionally, both as a receiving end and a transmitting end, and thus the structure shown in fig. 1 or fig. 2 and the structure shown in fig. 5 or fig. 6 are integrated at the same time. In addition, in one embodiment, from the viewpoint of circuit design, the first phase shift module and the second phase shift module that are similar in function may be the same circuit, and similarly, the first phase deviation determining module and the second phase deviation determining module may be the same circuit, and the first phase compensating module and the second phase compensating module may be the same circuit.
Compared with the prior art, the memory access system provided by the embodiment of the invention has the advantages that the reference signal line is added between the memory controller and the memory chip and is used for transmitting the reference signal, and the memory controller realizes memory training by using the reference signal. The memory training and the memory access are not interfered with each other, and the memory training can be continuously carried out when the memory chip works, so that the memory chip works more stably.
In another aspect, an embodiment of the present invention provides an electronic device, as shown in fig. 9, including a processor and a memory access system of the foregoing embodiment, where the processor may send a command to a memory controller, and the memory controller uses the first reference signal or the second reference signal to perform memory training.
In another aspect, an embodiment of the present invention provides a memory training method, applied to a memory controller, including the following steps:
in the process that the memory controller reads data from the memory chip, continuously sampling a first reference signal sent by the memory chip and judging whether sampling fails according to sampling data, wherein the period of the first reference signal is identical to that of a first data signal, the initial phase of the first reference signal is aligned with that of the first data signal, the first reference signal has a dynamically configured phase compensation value, and the first data signal is a data signal sent to the memory controller by the memory chip;
according to a phase compensation value configured when the sampling of the first reference signal fails, determining a first phase offset existing at the middle position of a normal sampling interval of the first reference signal relative to a jump position of a first strobe signal, wherein the first strobe signal is a strobe signal sent to a memory controller by a memory chip;
And performing phase compensation on the first data signal according to the first phase offset to align the middle position of the first data signal with the jump position of the first strobe signal.
The implementation of the memory training method has been described in the previous embodiments, and will not be further described herein.
According to the memory training method provided by the embodiment of the invention, memory training is carried out in the process that the memory controller reads data from the memory chip, the first reference signal is continuously sampled, the first phase offset which exists in the middle position of the normal sampling interval of the first reference signal relative to the jump position of the first gating signal is determined according to the phase compensation value configured when the first reference signal fails to sample, and then the first data signal is subjected to phase compensation according to the first phase offset, so that the middle position of the first data signal is aligned with the jump position of the first gating signal. Compared with the prior art, the memory training is performed by using the first reference signal, the memory training and the memory access are not interfered with each other, and the memory training can be continuously performed when the memory chip works, so that the memory chip works more stably.
In another aspect, an embodiment of the present invention provides a memory training method, applied to a memory controller, including the following steps:
In the process that the memory controller writes data into the memory chip, a second reference signal is sent to the memory chip, so that the memory chip continuously samples the second reference signal and judges whether sampling fails according to sampling data, the period of the second reference signal is identical to that of the second data signal, the initial phase of the second reference signal is aligned with that of the second data signal, the second reference signal has a dynamically configured phase compensation value, and the second data signal is a data signal sent to the memory chip by the memory controller;
determining a second phase offset of the middle position of the normal sampling interval of the second reference signal relative to the jump position of the second strobe signal according to the phase compensation value configured when the sampling of the second reference signal fails, wherein the second strobe signal is a strobe signal sent to the memory chip by the memory controller;
and performing phase compensation on the second data signal according to the second phase offset to align the middle position of the second data signal with the jump position of the second strobe signal.
According to the memory training method provided by the embodiment of the invention, memory training is carried out in the process that the memory controller writes data into the memory chip, the second reference signal is sent to the memory chip, the memory chip continuously samples the second reference signal, the second phase offset of the middle position of the normal sampling interval of the second reference signal relative to the jump position of the second gating signal is determined according to the phase compensation value configured when the second reference signal fails to sample, and then the second data signal is subjected to phase compensation according to the second phase offset, so that the middle position of the second data signal is aligned with the jump position of the second gating signal. Compared with the prior art, the memory training is performed by using the second reference signal, the memory training and the memory access are not interfered with each other, and the memory training can be continuously performed when the memory chip works, so that the memory chip works more stably.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims (13)
1. A memory controller, the memory controller comprising:
the first sampling module is used for continuously sampling a first reference signal sent by the memory chip and judging whether sampling fails according to sampling data in the process that the memory controller reads data from the memory chip, the period of the first reference signal is identical to that of the first data signal, the initial phase of the first reference signal is aligned with that of the first data signal, the first reference signal has a dynamically configured phase compensation value, and the first data signal is a data signal sent to the memory controller by the memory chip;
the first phase offset determining module is used for determining a first phase offset which exists at the middle position of a normal sampling interval of the first reference signal relative to the jump position of a first gating signal according to a phase compensation value configured when the sampling of the first reference signal fails, wherein the first gating signal is a gating signal sent to a memory controller by a memory chip;
And the first phase compensation module is used for carrying out phase compensation on the first data signal according to the first phase offset so as to align the middle position of the first data signal with the jump position of the first gating signal.
2. The memory controller of claim 1, further comprising a first phase shifting module for configuring different phase compensation values for the first reference signal during a process of the memory controller reading data from the memory chip.
3. The memory controller of claim 2, wherein the first phase shifting module is configured to configure different first compensation values for the first reference signal such that the first reference signal is shifted by different phases in a first direction until sampling of the first reference signal fails, and is configured to configure different second compensation values for the first reference signal such that the first reference signal is shifted by different phases in a second direction until sampling of the first reference signal fails, wherein the first direction and the second direction are opposite directions;
the first phase offset determining module is configured to determine, according to a first compensation value and a second compensation value configured when sampling of the first reference signal fails, a first phase offset that exists at a middle position of a normal sampling interval of the first reference signal relative to a jump position of a first strobe signal.
4. The memory controller of claim 3, wherein the first phase shifting module is configured to increase a first compensation value of the first reference signal according to a set step size when the first strobe signal hops each time, so that the first reference signal sequentially shifts right according to the set step size until the first reference signal fails to sample, and decrease a second compensation value of the first reference signal according to a set step size when the first strobe signal hops each time, so that the first reference signal sequentially shifts left according to the set step size until the first reference signal fails to sample.
5. A memory controller, the memory controller comprising:
the first driving module is used for sending a second reference signal to the memory chip in the process of writing data into the memory chip by the memory controller, so that the memory chip continuously samples the second reference signal and judges whether sampling fails according to sampling data, the period of the second reference signal is the same as that of the second data signal, the initial phase of the second reference signal is aligned with the initial phase of the second data signal, the second reference signal has a dynamically configured phase compensation value, and the second data signal is the data signal sent to the memory chip by the memory controller;
A second phase offset determining module, configured to determine, according to a phase compensation value configured when sampling of the second reference signal fails, a second phase offset that exists at a middle position of a normal sampling interval of the second reference signal relative to a jump position of a second strobe signal, where the second strobe signal is a strobe signal sent to a memory chip by a memory controller;
and the second phase compensation module is used for carrying out phase compensation on the second data signal according to the second phase offset so as to align the middle position of the second data signal with the jump position of the second gating signal.
6. The memory controller of claim 5, further comprising a second phase shifting module for configuring different phase compensation values for the second reference signal during the memory controller writing data to the memory chip.
7. The memory controller of claim 6, wherein the second phase shifting module is configured to configure a third different compensation value for the second reference signal such that the second reference signal is shifted by a different phase in a first direction until the second reference signal fails to sample, and is configured to configure a fourth different compensation value for the second reference signal such that the second reference signal is shifted by a different phase in a second direction until the second reference signal fails to sample, wherein the first direction and the second direction are opposite directions;
The second phase offset determining module is configured to determine, according to a third compensation value and a fourth compensation value configured when the second reference signal fails to be sampled, a second phase offset that exists at a middle position of a normal sampling interval of the second reference signal relative to a jump position of a second gating signal.
8. The memory controller of claim 7, wherein the second phase shifting module is configured to increase a third compensation value of the second reference signal according to a set step size when the second strobe signal hops each time, so that the second reference signal sequentially shifts right according to the set step size until the second reference signal fails to sample, and to decrease a fourth compensation value of the second reference signal according to a set step size when the second strobe signal hops each time, so that the second reference signal sequentially shifts left according to the set step size until the second reference signal fails to sample.
9. A memory access system comprising the memory controller and memory chip of any one of claims 1 to 4 and a signal line for transmitting signals between the memory controller and memory chip, wherein the signal line comprises:
A data signal line for transmitting the first data signal;
a gate signal line for transmitting the first gate signal, an
And the reference signal line is used for transmitting the first reference signal.
10. A memory access system comprising the memory controller and the memory chip as claimed in any one of claims 5 to 8 and a signal line for transmitting signals between the memory controller and the memory chip, wherein the signal line comprises:
a data signal line for transmitting the second data signal;
a gate signal line for transmitting the second gate signal, an
And the reference signal line is used for transmitting the second reference signal.
11. An electronic device comprising the memory access system of claim 9 or 10.
12. A memory training method, applied to a memory controller, comprising:
continuously sampling a first reference signal sent by a memory chip and judging whether sampling fails according to sampling data in the process that the memory controller reads data from the memory chip, wherein the period of the first reference signal is identical to that of a first data signal, the initial phase of the first reference signal is aligned with that of the first data signal, the first reference signal has a dynamically configured phase compensation value, and the first data signal is a data signal sent to the memory controller by the memory chip;
Determining a first phase offset of the middle position of a normal sampling interval of the first reference signal relative to a jump position of a first strobe signal according to a phase compensation value configured when the first reference signal fails to be sampled, wherein the first strobe signal is a strobe signal sent to a memory controller by a memory chip;
and performing phase compensation on the first data signal according to the first phase offset to align the middle position of the first data signal with the jump position of the first strobe signal.
13. A memory training method, applied to a memory controller, comprising:
in the process that the memory controller writes data into the memory chip, a second reference signal is sent to the memory chip, so that the memory chip continuously samples the second reference signal and judges whether sampling fails according to sampling data, the period of the second reference signal is identical to that of the second data signal, the initial phase of the second reference signal is aligned with that of the second data signal, the second reference signal has a dynamically configured phase compensation value, and the second data signal is a data signal sent to the memory chip by the memory controller;
Determining a second phase offset of the middle position of a normal sampling interval of the second reference signal relative to a jump position of a second strobe signal according to a phase compensation value configured when the second reference signal fails to be sampled, wherein the second strobe signal is a strobe signal sent to a memory chip by a memory controller;
and carrying out phase compensation on the second data signal according to the second phase offset so as to align the middle position of the second data signal with the jump position of the second gating signal.
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