CN116074456A

CN116074456A - Method for synchronizing image processing components

Info

Publication number: CN116074456A
Application number: CN202211376753.3A
Authority: CN
Inventors: D·安布罗西奥
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 2021-11-04
Filing date: 2022-11-04
Publication date: 2023-05-05
Also published as: DE102021212406A1

Abstract

The invention relates to a method for synchronizing image processing components. The image processing means comprises a deserializer (14) to receive the data stream of at least one camera, a central computing unit (22) for image interpretation and image processing, an image preprocessing device (18), and a serializer (26) for outputting the processed image. All image processing components (14, 18, 22, 26) are synchronized with each other by at least one clock signal (30) output by a single image processing component (14, 18, 22, 26).

Description

Method for synchronizing image processing components

Technical Field

The present invention relates to a method for synchronizing image processing means and to a device for performing such a method.

Background

Vehicles, particularly cars and trucks, may be equipped with one or more cameras. The camera is connected to an Electronic Control Unit (ECU) for processing video data. Further, video data may be transmitted from the camera to the ECU via a cable. Thus, video data from the camera is serially transmitted to the ECU. This requires a serializer on the camera side and a deserializer on the control device side. In order to synchronize the components with each other, a clock signal is required, which can be generated clock-wise from the clock signal by means of an external clock generator, such as an oscillator, or by means of an oscillating crystal on the respective component and its circuitry.

A camera system for a vehicle is disclosed in US 10,343,606B2, which has a camera unit with a serializer and a control unit with a deserializer connected to the serializer. The deserializer contains multiple data contacts for parallel data output. The pixel clock may be used for data transfer from the data contacts of the deserializer to the data processing unit. For this purpose, a clock contact may be provided on the deserializer and the data processing unit.

Such synchronization of components is complex and cost-intensive. Additionally, errors may occur due to the large number of parts.

The object of the invention is therefore to specify a method which makes it possible to carry out synchronization more simply and economically. Additionally, the object is to specify a device capable of carrying out such a method.

This object is achieved by a method according to the invention for synchronizing image processing means. The invention additionally relates to a device according to the invention for carrying out such a method. Preferred embodiments are described below.

Disclosure of Invention

The present invention describes a method for synchronizing image processing components. The image processing means comprise a deserializer by means of which a data stream of at least one camera is received, a central computing unit for image interpretation and image processing, an image preprocessing device and a serializer for outputting the processed image. All image processing components are synchronized with each other by at least one clock signal output by a unique image processing component.

"deserializer" is understood to be the following components: the component converts serial data transmitted over the serial connection into objects or, in this case, images. In the image preprocessing device, certain attributes or structures of the image are emphasized. Additionally, the image is processed in such a way that the processing of the image is simplified. The actual image processing and image interpretation takes place in a central computing unit. Here, the serializer is a component that functions in opposition to the deserializer, which forms serial data from an object for serial transmission.

As in the prior art, the image processing sections are synchronized with each other by a clock signal. Unlike the prior art, no additional external components are required to generate clock signals for all image processing components. Alternatively, the clock signal is generated by an already existing image processing section. Therefore, this has the following advantages: no externally arranged and cost-intensive components with respect to the image processing components are required. The reduced number of parts also reduces the error-prone and complexity of such devices.

In a preferred embodiment of the invention, the clock signal is output by a central computing unit. Thus, the clock signal is output from the central computing unit to the remaining image processing sections. This arrangement has the following advantages: the clock signal or the generation of the clock signal can be monitored directly by the central computing unit. Thereby simplifying the method for synchronizing the image processing means.

In another preferred embodiment of the present invention, the clock signal is output by a deserializer, an image preprocessing device, or a serializer. The clock signal may also be generated by these image processing means. Generating clock signals in different image processing components may lead to different advantages depending on the use of the image processing components.

Preferably, the plurality of clock signals are output by an image processing section that generates the clock signals. By generating a plurality of clock signals independent of each other, the working steps relating to the data of the plurality of cameras can be synchronized.

In an advantageous embodiment, the clock signal is generated in the image processing unit by means of a phase-locked loop. The phase-locked loop is a control loop with a controlled oscillator. Such a phase locked loop is easy to implement and has a high frequency stability so that an accurate clock signal can be economically generated.

Advantageously, the clock signal is generated within the image processing component by means of a clock manager. Here, the clock manager has the following advantages: still more accurate clock generation can be achieved. Thereby improving the synchronization of the image components with each other.

The object on which the invention is based is additionally achieved by a device for carrying out such a method. The device comprises at least one deserializer for receiving a data stream of at least one camera, a central computing unit for image interpretation and image processing, image preprocessing means and a serializer for outputting processed images, wherein one of the image processing components is constructed in such a way that at least one clock signal is generated to the remaining image processing components to synchronize them. The same advantages as mentioned for the method can be achieved with such a device. Such a device is therefore simpler and more economical than the prior art.

In an advantageous embodiment, the electrical connections from the image processing unit generating the clock signal to the remaining image processing units are of equal length. By using electrical connections of equal length, the signal propagation times between different image processing components are equal in length, so that no different signal propagation times occur. Thereby further improving the synchronicity of the image processing means.

Alternatively, the signal propagation times of the connections are matched accordingly. In other words, the (abgegeben) signal is released according to the length of the electrical connection so that all image processing components arrive at the clock at the same time. This can be achieved by: the clock signals to the different image processing components are released not simultaneously but in advance or retarded in correspondence with the line length. Although this difference is only in the range of a fraction of a microsecond, the accuracy of the synchronization is thereby greatly improved.

According to an advantageous embodiment, the central computing unit consists of one or more processors, a graphics processor and/or a free logic gate. With such a central computing unit, a high quality of image interpretation and image processing is achieved.

Drawings

Embodiments of the invention are illustrated in the accompanying drawings and described in more detail in the following description. The drawings show:

fig. 1 shows an embodiment of an apparatus for performing the method according to the invention.

Detailed Description

In the figure an embodiment of a device 10 for performing the method according to the invention is shown. The device 10 comprises a deserializer 14 by means of which a serial data stream of at least one camera is received. Furthermore, the device 10 comprises image preprocessing means 18 by means of which the image is preprocessed. The images are substantially interpreted and processed in a central computing unit 22, which may consist of a processor, a graphics processor and/or a free-form logic gate, not shown here.

The result of the central computing unit 22 is directed to a serializer 26 through which the processed image is output. In order to synchronize the

image processing components

14, 18, 22, 26 with each other, the central computing unit 22 outputs a clock signal 30 to the remaining image processing components. Here, the clock signal is output through a clock manager or phase locked loop 34 within the central computing unit 22. To avoid time delays due to connections 38 of different lengths, the connections 38 in this embodiment are constructed to be substantially equal in length.

Claims

1. Method for synchronizing image processing components comprising a deserializer (14), a central computing unit (22) for image interpretation and image processing, an image preprocessing device (18), and a serializer (26) by means of which a data stream of at least one camera is received, for outputting processed images, wherein all image processing components (14, 18, 22, 26) are synchronized with each other by means of at least one clock signal (30) output by a unique image processing component (14, 18, 22, 26).

2. The method according to claim 1, characterized in that the clock signal (30) is output by the central computing unit (22).

3. The method of claim 1, wherein the clock signal (30) is output by the deserializer (14), the image preprocessing device (18), or the serializer (26).

4. A method according to any of the preceding claims, characterized in that a plurality of clock signals (30) are output by the image processing means (14, 18, 22, 26).

5. The method according to any of the preceding claims, characterized in that the clock signal (30) is generated within the image processing component (14, 18, 22, 26) by means of a phase locked loop (34).

6. The method according to any one of claims 1 to 4, characterized in that the clock signal (30) is generated within the image processing component (14, 18, 22, 26) by means of a clock manager (34).

7. Apparatus (10) for performing the method according to any one of the preceding claims, comprising at least one deserializer (14) for receiving a data stream of at least one camera, a central computing unit (22) for image interpretation and image processing, an image preprocessing device (18) and a serializer (26) for outputting a processed image, wherein one of the image processing means (14, 18, 22, 26) is configured such that: at least one clock signal (30) is generated for the remaining image processing components (14, 18, 22, 26) for synchronizing the remaining image processing components.

8. The device (10) according to claim 7, characterized in that the electrical connections (38) from the image processing means (14, 18, 22, 26) generating the clock signal to the remaining image processing means (14, 18, 22, 26) are of equal length or the signal propagation times of the connections (38) are matched accordingly.

9. The device (10) according to claim 7 or 8, characterized in that the central computing unit (22) consists of one or more processors, graphics processors and/or freely selectable logic gates.