CN116072779A - Epitaxial wafer of LED device and preparation method thereof - Google Patents

Epitaxial wafer of LED device and preparation method thereof Download PDF

Info

Publication number
CN116072779A
CN116072779A CN202310179491.XA CN202310179491A CN116072779A CN 116072779 A CN116072779 A CN 116072779A CN 202310179491 A CN202310179491 A CN 202310179491A CN 116072779 A CN116072779 A CN 116072779A
Authority
CN
China
Prior art keywords
layer
light
face
type semiconductor
emitting unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310179491.XA
Other languages
Chinese (zh)
Inventor
王阳
林志宇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangsu Third Generation Semiconductor Research Institute Co Ltd
Original Assignee
Jiangsu Third Generation Semiconductor Research Institute Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Third Generation Semiconductor Research Institute Co Ltd filed Critical Jiangsu Third Generation Semiconductor Research Institute Co Ltd
Priority to CN202310179491.XA priority Critical patent/CN116072779A/en
Publication of CN116072779A publication Critical patent/CN116072779A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H01L33/325—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen characterised by the doping materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

The invention discloses an epitaxial wafer of an LED device and a preparation method thereof. The epitaxial wafer of the LED device comprises: the substrate, nucleation layer and epitaxial structure layer, the surface of the substrate has the first area and second area adjacent to first area; the nucleation layer is arranged in the first area; the epitaxial structure layer comprises a first light-emitting unit and a second light-emitting unit, wherein the first light-emitting unit is arranged on the nucleation layer, the second light-emitting unit is arranged in a second area on the surface of the substrate, the first light-emitting unit mainly consists of Ga-surface III-nitride materials, and the second light-emitting unit mainly consists of N-surface III-nitride materials. By adopting the invention, the luminous efficiency of the LED device is improved.

Description

Epitaxial wafer of LED device and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to an epitaxial wafer of a white light LED device with a bicolor active layer and a preparation method of the epitaxial wafer.
Background
Currently, there are two technical approaches for realizing white light illumination by using a light-emitting diode (LED): one is to use the LED to excite the fluorescent substance to form white light, which can be called as a secondary light conversion white light technology; another is to use LEDs to directly emit white light, which may be referred to as "direct-emission white light technology". The secondary light conversion white light technology mainly uses a blue light LED to excite yellow fluorescent powder, and yellow light emitted by the excited yellow fluorescent powder is mixed with blue light emitted by the LED to form white light, as shown in figure 1; the technical method is simple and practical, has good temperature stability, but has higher color temperature, poorer color rendering property and color uniformity related to angles. The 'direct-emitting white light technology' is to directly emit white light by utilizing a nitride LED without fluorescent substances, and the limitation of the light conversion efficiency and the service life of the fluorescent substances on the performance of the solid-state lighting source is eliminated.
At present, the technology of directly emitting white light can be realized in two ways: multichip and single chip types. The multi-chip scheme is shown in fig. 2, in which three LED chips emitting red light, green light and blue light are packaged on one substrate and are blended into white light by using three colors, and the scheme has the disadvantages of low integration level and high cost. The single chip scheme is to utilize a multi-active layer laminated quantum well LED structure on a single chip to emit multi-color light to synthesize white light, and a typical single chip double-active layer double-color LED device structure is shown In figure 3, wherein the active layer is an InGaN/GaN multi-quantum well with 5 periods, different In components are adopted to respectively emit blue light with the wavelength of 460nm and green light with the wavelength of 520nm, and white light is obtained without fluorescent substances. Fig. 4 shows the emission spectrum of a typical blue/yellow monolithic dual active layer LED device, which is currently the dominant solution in the "direct-emission white light technology".
However, disadvantages of monolithic dual active layer dual color LED devices include: first, since the In components of InGaN In the two active layers are different, the forbidden bandwidths are different, and the forbidden bandwidth of InGaN with higher In component (the light emitting wavelength is longer, such as yellow light) is smaller, so that the InGaN has a strong absorption effect on short wavelength light (such as blue light); in a conventional device structure, short-wavelength light emitted downwards by the quantum well can be reflected by the substrate to be emitted from the surface of the device again; however, in such a dual active layer dual color LED device, blue light emitted downward is absorbed in the process of passing through the active layer emitting yellow light, thereby reducing the final light emitting efficiency of the device; second, the solution places a long wavelength (e.g., yellow light) quantum well structure below and a short wavelength (e.g., blue light) quantum well structure above when the device is fabricated, and during the process of growing a long wavelength (e.g., blue light) quantum well structure, the growth temperature is generally higher than that of the long wavelength quantum well structure, and the elevated temperature can lead to decomposition of InGaN materials, so that the performance of the long wavelength quantum well structure can be degraded, and the device performance is affected.
Disclosure of Invention
The invention mainly aims to provide an epitaxial wafer of an LED device and a preparation method thereof, thereby overcoming the defects in the prior art.
In order to achieve the purpose of the invention, the technical scheme adopted by the invention comprises the following steps:
in one aspect, the present invention provides an epitaxial wafer of an LED device, including:
a substrate, the surface of the substrate having a first region and a second region adjacent to the first region;
a nucleation layer disposed in the first region;
and the epitaxial structure layer comprises a first light-emitting unit and a second light-emitting unit, the first light-emitting unit is arranged on the nucleation layer, the second light-emitting unit is arranged in the second region, wherein the first light-emitting unit comprises Ga-surface III-nitride materials, and the second light-emitting unit comprises N-surface III-nitride materials.
Further, the first light emitting unit includes a Ga-face N-type semiconductor layer, a Ga-face light emitting layer, a Ga-face electron blocking layer, and a Ga-face p-type semiconductor layer sequentially stacked on the nucleation layer, the second light emitting unit includes an N-face N-type semiconductor layer, an N-face light emitting layer, an N-face electron blocking layer, and an N-face p-type semiconductor layer sequentially stacked on the second region,
the Ga-surface N-type semiconductor layer and the N-surface N-type semiconductor layer, the Ga-surface light-emitting layer and the N-surface light-emitting layer, the Ga-surface electron blocking layer and the N-surface electron blocking layer, the Ga-surface p-type semiconductor layer and the N-surface p-type semiconductor layer are all integrally formed.
Further, the In component content In the Ga-face light-emitting layer is smaller than the In component content In the N-face light-emitting layer.
Further, the Ga-surface light-emitting layer and the N-surface light-emitting layer are located in the same plane.
Further, the Ga-face N-type semiconductor layer and the N-face N-type semiconductor layer, the Ga-face electron blocking layer and the N-face electron blocking layer, and the Ga-face p-type semiconductor layer and the N-face p-type semiconductor layer are also respectively located in the same plane.
Further, the epitaxial wafer further comprises a buffer layer, the buffer layer comprises a Ga surface buffer layer and an N surface buffer layer which are integrally formed, the Ga surface buffer layer is arranged between the nucleation layer and the first light-emitting unit, the N surface buffer layer is arranged between the second area and the second light-emitting unit, and the buffer layer can be made of GaN.
Further, the top surfaces of the Ga-face buffer layer and the N-face buffer layer facing away from the substrate are flush.
Further, the n-type semiconductor layer may be an n-type GaN layer, the light emitting layer may be an InGaN/GaN multiple quantum well light emitting layer, the electron blocking layer may be an AlGaN electron blocking layer, and the p-type semiconductor layer may be a p-type GaN layer; specifically, the light emitting layer may also be referred to as an active layer, an active region, or the like.
Further, the substrate may be a sapphire substrate or a silicon carbide substrate, etc., preferably, the substrate is a sapphire substrate having a chamfer angle, the chamfer angle direction of the sapphire substrate is c-plane offset m-axis, and the chamfer angle is 1 to 4 °.
Further, the material of the nucleation layer includes a group III nitride, and by way of example, the nucleation layer may be an AlN nucleation layer or a GaN nucleation layer.
The invention also provides a preparation method of the epitaxial wafer of the LED device, which comprises the following steps:
providing a substrate, wherein the surface of the substrate is provided with a first area and a second area adjacent to the first area;
forming a nucleation layer in the first region;
forming an epitaxial structure layer on the nucleation layer, wherein the epitaxial structure layer comprises a first light emitting unit and a second light emitting unit, the first light emitting unit is arranged on the nucleation layer, and the second light emitting unit is arranged on the second region; wherein the first light emitting unit comprises a Ga-face group III nitride material and the second light emitting unit comprises an N-face group III nitride material.
Further, the step of forming an epitaxial structure layer on the nucleation layer includes:
simultaneously, growing a III-nitride material on the surface of the nucleation layer and the second region, and adjusting the growth parameters of the III-nitride material in the growth process of the III-nitride material to enable the III-nitride material growing on the nucleation layer to form a Ga-surface III-nitride material and enable the III-nitride material growing on the second region to form an N-surface III-nitride material; wherein the growth parameters include at least one of growth temperature, growth pressure, and V-III ratio of the growth feedstock.
It is understood that the V-III ratio is the molar ratio of the group V element to the group III element.
Further, the first light emitting unit includes a Ga-face N-type semiconductor layer, a Ga-face light emitting layer, a Ga-face electron blocking layer, and a Ga-face p-type semiconductor layer sequentially stacked on the nucleation layer, and the second light emitting unit includes an N-face N-type semiconductor layer, an N-face light emitting layer, an N-face electron blocking layer, and an N-face p-type semiconductor layer sequentially stacked on the second region; wherein the Ga-face N-type semiconductor layer and the N-face N-type semiconductor layer, the Ga-face light-emitting layer and the N-face light-emitting layer, the Ga-face electron blocking layer and the N-face electron blocking layer, the Ga-face p-type semiconductor layer and the N-face p-type semiconductor layer are all integrally formed; the step of forming an epitaxial structure layer on the nucleation layer specifically comprises:
growing the Ga-surface N-type semiconductor layer and the N-surface N-type semiconductor layer under a first preset condition, wherein the first preset condition comprises the following steps: the growth temperature is 1000-1100 ℃, the growth pressure is 100-400 mbar, and the V-III ratio of the growth raw materials is 500-2000;
and growing the Ga surface light-emitting layer and the N surface light-emitting layer under a second preset condition, wherein the second preset condition comprises the following steps: the growth temperature is 700-900 ℃, the growth pressure is 100-400 mbar, and the V-III ratio of the growth raw materials is 10000-30000;
and growing the Ga-face electron blocking layer and the N-face electron blocking layer under a third preset condition, wherein the third preset condition comprises the following steps: the growth temperature is 1000-1100 ℃, the growth pressure is 100-200 mbar, and the V-III ratio of the growth raw materials is 500-2000;
and growing the Ga-surface p-type semiconductor layer and the N-surface p-type semiconductor layer under a fourth preset condition, wherein the fourth preset condition comprises the following steps: the growth temperature is 1000-1100 ℃, the growth pressure is 100-400 mbar, and the V-III ratio of the growth raw materials is 500-2000.
Further, the step of forming an epitaxial structure layer on the nucleation layer further comprises:
forming a buffer layer on the nucleation layer and the second region, and forming a flat surface on top of the buffer layer formed by growth;
and growing the epitaxial structure layer on the buffer layer.
Further, the buffer layer includes a Ga-face buffer layer and an N-face buffer layer, and the step of forming the buffer layer on the nucleation layer and the second region includes:
simultaneously growing the Ga-face buffer layer and the N-face buffer layer under a fifth preset condition to enable the Ga-face buffer layer to be flush with the top surface of the N-face buffer layer, wherein the fifth preset condition comprises the following steps: the growth temperature is 1050-1150 ℃, the growth pressure is 100-400 mbar, and the V-III ratio of the growth raw materials is 100-1000; the material of the buffer layer may be GaN, for example.
Further, the preparation method specifically comprises the following steps: forming a nucleation layer in the first region, and removing the nucleation layer covering the second region to expose the second region; or, covering a mask on the second area; forming a nucleation layer in the first region; the mask is removed to expose the second region.
Further, the substrate may be a sapphire substrate or a silicon carbide substrate, and preferably, the sapphire substrate is a sapphire substrate having a chamfer angle, the chamfer angle direction of the sapphire substrate is c-plane offset m-axis, and the chamfer angle is 1-4 °.
Further, the material of the nucleation layer includes a group III nitride, and by way of example, the nucleation layer may be an AlN nucleation layer or a GaN nucleation layer.
Compared with the prior art, the invention has the advantages that:
1) According to the invention, the Ga-surface active layer and the N-surface active layer obtained by adopting the preparation method of the epitaxial wafer of the LED device are arranged on the same plane, and the physical process that short-wavelength light passes through a long-wavelength quantum well and is absorbed does not exist in the light extraction process, so that the luminous efficiency of the device is improved.
2) The invention can control the area ratio of Ga-surface III-nitride material and N-surface III-nitride material by controlling the area ratio of the etched nucleation layer to the reserved nucleation layer, thereby realizing the control of the area ratio of the first light-emitting unit and the second light-emitting unit, further controlling the light-emitting area ratio of the light with two wavelengths emitted by the light-emitting units, finally obtaining the dual-color light meeting the requirements and realizing white light illumination.
Drawings
FIG. 1 is a schematic diagram of a prior art white light illumination using a blue LED and a yellow phosphor;
FIG. 2 is a schematic diagram of a prior art white light illumination using red, green and blue LEDs;
FIG. 3 is a schematic diagram of a monolithic dual active layer bi-color LED structure according to the prior art;
fig. 4 is a luminescence spectrum of a monolithic dual active layer bi-color LED device of the prior art;
FIG. 5 is a graph of the contrast of the emission wavelengths of Ga-face InGaN material and N-face InGaN material;
fig. 6 is a schematic structural diagram of an epitaxial wafer of a white LED device with a bi-color active layer according to the present invention;
fig. 7a to fig. 7f are schematic views of a process for preparing an epitaxial wafer of a white LED device with a dual-color active layer according to the present invention;
fig. 8 is a luminescence spectrum of an LED device integrated with Ga-face and N-face InGaN/GaN quantum well structures according to the present invention.
Detailed Description
In view of the shortcomings in the prior art, the inventor of the present invention has long studied and practiced in a large number of ways to propose the technical scheme of the present invention. The technical scheme, implementation process and principle of the present invention will be further explained with reference to the drawings and specific embodiments, and unless otherwise stated, the Metal-organic chemical vapor deposition (Metal-organic Chemical Vapor Deposition, MOCVD) equipment, physical vapor deposition (Physical Vapor Deposition, PVD) equipment, reactive ion etching (Reactive Ion Etching, RIE) equipment, and nitrogen source, group III source, carrier gas for growing epitaxial layers used in the embodiments of the present invention are known to those skilled in the art, and will not be repeated herein.
The inventor of the present application has found that the light emission wavelength of a GaN-based LED device is determined by the In composition of InGaN quantum wells In the device, and the higher the In composition is, the longer the light emission wavelength is. Since GaN is a polar semiconductor, a Ga-face GaN material and an N-face GaN material can be obtained by controlling a growth process, and the current devices such as LEDs mainly use a Ga-face GaN material, and since there is a difference In polarity, an In component of an InGaN material grown on the N-face GaN material is higher than that of the Ga-face GaN material at the same growth temperature, and as can be seen from fig. 5, the InGaN material grown on the N-face GaN material corresponds to a longer light emission wavelength, where "N-pole" is an N-face and "Ga-pole" is a Ga-face. According to the invention, the Ga-face GaN/InGaN quantum well material and the N-face GaN/InGaN quantum well material are simultaneously grown on the same substrate, so that the quantum well structure in the GaN-based LED device emits light with two different wavelengths simultaneously, and a single-chip double-color white LED device is obtained.
Example 1
Referring to fig. 6, fig. 6 is a schematic structural diagram of an epitaxial wafer of an LED device according to the present invention, where the epitaxial wafer includes a sapphire substrate 100, an AlN nucleation layer 200, a GaN buffer layer, and an epitaxial structural layer.
The surface of the sapphire substrate 100 has a first region and a second region adjacent to the first region. Specifically, the sapphire substrate 100 is a sapphire substrate having a chamfer angle, the chamfer angle direction of the sapphire substrate is c-plane offset m-axis, and the chamfer angle is 1 to 4 °.
The AlN nucleation layer 200 is disposed on a first region of the surface of the sapphire substrate 100, and the GaN buffer layer is disposed on the surface of the AlN nucleation layer 200 and a second region of the surface of the sapphire substrate 100.
The GaN buffer layer includes a Ga-face GaN buffer layer 310 and an N-face GaN buffer layer 320 integrally formed; the Ga-face GaN buffer layer 310 is stacked on the AlN nucleation layer 200, and the N-face GaN buffer layer 320 is stacked on the second region of the surface of the sapphire substrate 10. Further, the Ga-face GaN buffer layer 310 is a Ga-polarity GaN buffer layer composed of a Ga-face GaN material, and the N-face GaN buffer layer 320 is an N-polarity GaN buffer layer composed of an N-face GaN material.
Further, the surface of the GaN buffer layer is continuous and flat, i.e., the top surfaces of the Ga-face GaN buffer layer 310 and the N-face GaN buffer layer 320 (i.e., the side away from the sapphire substrate 100) are continuous and flat; specifically, since the AlN nucleation layer 200 is disposed between the Ga-face GaN buffer layer 310 and the sapphire substrate 100, the thickness of the Ga-face GaN buffer layer 310 is smaller than that of the N-face GaN buffer layer 320, and the sum of the thicknesses of the Ga-face GaN buffer layer 310 and the AlN nucleation layer 200 is equal to that of the N-face GaN buffer layer 320; illustratively, alN nucleation layer 200 has a thickness of 100nm, ga-face GaN buffer layer 310 has a thickness of 400nm, and N-face GaN buffer layer 320 has a thickness of 500nm. In this embodiment, the AlN nucleation layer 200 grown on the sapphire substrate 100 is controlled to be an Al surface (metal surface), and the GaN buffer layer grown on the AlN nucleation layer 200 is a Ga-surface GaN buffer layer 310; the N-face GaN buffer layer 320 is grown directly on the sapphire substrate 100 by controlling the growth conditions while not affecting the polarity of the Ga-face GaN buffer layer 310 on the AlN nucleation layer 200.
The epitaxial structure layer includes an n-type GaN layer, an InGaN/GaN multiple quantum well light emitting layer (multiple quantum well, MQW), an AlGaN electron-blocking layer (EBL), and a p-type GaN layer sequentially stacked on the GaN buffer layer.
Specifically, the N-type GaN layer includes a Ga-face N-type GaN layer 411 and an N-face N-type GaN layer 421 that are integrally formed; the InGaN/GaN multiple quantum well light emitting layer includes a Ga-face InGaN/GaN multiple quantum well layer (i.e., ga-face active layer or Ga-face light emitting layer) 412 and an N-face InGaN/GaN multiple quantum well layer (i.e., N-face active layer or N-face light emitting layer) 422 that are integrally formed; the AlGaN electron blocking layer includes a Ga-face AlGaN electron blocking layer 413 and an N-face AlGaN electron blocking layer 423 which are integrally formed; the p-type GaN layer includes a Ga-face p-type GaN layer 414 and an N-face p-type GaN layer 424 that are integrally formed.
Further, a Ga-face n-type GaN layer 411, a Ga-face InGaN/GaN multiple quantum well layer 412, a Ga-face AlGaN electron blocking layer 413, and a Ga-face p-type GaN layer 414 are sequentially stacked on the Ga-face GaN buffer layer 310, and constitute a first light emitting unit 410; an N-plane N-type GaN layer 421, an N-plane InGaN/GaN multiple quantum well layer 422, an N-plane AlGaN electron blocking layer 423, and an N-plane p-type GaN layer 424 are sequentially stacked on the N-plane GaN buffer layer 320, and constitute a second light emitting unit 420.
Further, the Ga-face N-type GaN layer 411 and the N-face N-type GaN layer 421 are formed by simultaneous growth, and the thicknesses are the same; the Ga-face InGaN/GaN multiple quantum well layer 412 and the N-face InGaN/GaN multiple quantum well layer 422 are formed by simultaneous growth and are the same thickness; the Ga-face AlGaN electron blocking layer 413 and the N-face AlGaN electron blocking layer 423 are formed by growing at the same time and have the same thickness; the Ga-face p-type GaN layer 414 and the N-face p-type GaN layer 424 are simultaneously grown and formed to the same thickness, and the content of In component In the Ga-face InGaN/GaN multiple quantum well layer 412 is smaller than that In the N-face InGaN/GaN multiple quantum well layer 422.
Compared with a single-chip double-active-layer double-color LED structure (shown In figure 3) In the traditional technical scheme, the epitaxial wafer of the LED device provided by the invention not only has a double-color active layer to emit white light, but also has the same height, so that the phenomenon that short-wavelength light passes through the long-wavelength active layer to be absorbed In the light extraction process is avoided, the light extraction efficiency of the LED device is improved, and the light emitting efficiency of the LED device is further improved.
Referring to fig. 7a to 7f, fig. 7a to 7f are a method for preparing an epitaxial wafer of an LED device according to the present invention, the method includes the following steps:
1) A sapphire substrate 100 is provided as shown in fig. 7 a.
In order to improve the surface morphology of the N-face GaN material, the invention adopts the chamfer sapphire substrate with the chamfer angle direction of the m-axis of the c-face and the chamfer angle of 1-4 degrees.
2) An AlN nucleation layer 200 is formed in a first region of the surface of the sapphire substrate 100, as shown in fig. 7 b.
Step 2) may specifically include:
2.1 Placing the sapphire substrate 100 in a reaction chamber of MOCVD equipment, heating the temperature in the reaction chamber to 1100 ℃, adjusting the pressure to 130mbar, taking hydrogen as carrier gas, and introducing TMAL and NH into the reaction chamber 3 Controlling the inflow rate of TMAL to be 100sccm and NH 3 The flow rate of the solution was 1000sccm to grow an AlN nucleation layer 200 having a thickness of 100nm on the surface of the sapphire substrate 100.
In an embodiment, the AlN nucleation layer 200 may be a high-temperature AlN nucleation layer, where the high-temperature AlN nucleation layer may obtain a high-quality Ga-face GaN material, and an etching process (e.g., RIE) may be used to well remove the high-temperature AlN nucleation layer, prevent the high-temperature AlN nucleation layer from remaining in the second area on the surface of the sapphire substrate, and ensure that the high-temperature AlN nucleation layer is only disposed in the first area on the surface of the sapphire substrate 100, thereby ensuring the quality of the device.
2.2 The temperature in the reaction chamber is reduced to room temperature, photoresist is covered on the AlN nucleation layer 200, the photoresist above part of the AlN nucleation layer 200 is exposed through a photoetching process, and the photoresist on part of the AlN nucleation layer 200 is reserved; the AlN nucleation layer 200 is then etched away in other areas using a reactive ion etching process, thereby exposing a second area of the surface of the sapphire substrate 100.
The etching gas adopted in the reactive ion etching process is Cl 2 The radio frequency power is 60WThe pressure was 10mTorr, the gas flow was 15sccm, the etching thickness was 120nm, and the remaining AlN nucleation layer 200 was coated on the first region of the surface of the sapphire substrate 100.
In another embodiment, the step 2) may further include: firstly, a layer of mask is grown on the surface of the sapphire substrate 100, and the mask can be made of SiO 2 Or SiN x The method comprises the steps of carrying out a first treatment on the surface of the Then, the mask in the first area on the surface of the sapphire substrate 100 is processed through photolithography and etching processes to remove the mask in the first area; an MOCVD process is then used to grow AlN nucleation layer 200 on the first region, and the mask of the remaining region (i.e., the second region) is removed.
In other embodiments, the AlN nucleation layer may be grown by a magnetron sputtering method.
3) A GaN buffer layer including a Ga-face GaN buffer layer 310 and an N-face GaN buffer layer 320 integrally formed as shown in fig. 7c is grown on a second region of the surface of the sapphire substrate 100 and the AlN nucleation layer 200.
The sapphire substrate 100 with the AlN nucleation layer 200 covered on the first area is placed in a reaction chamber of MOCVD equipment again, the temperature in the reaction chamber is regulated to 1050 ℃, the pressure is regulated to 260mbar, and the hydrogen is taken as carrier gas, and TMGa and NH are introduced into the reaction chamber 3 Controlling the inflow rate of TMGa to be 240sccm and NH 3 The flow rate of the opening is 30000sccm to grow an unintentionally doped GaN material on the second region and on the AlN nucleation layer 200, wherein the growth rate of the GaN material on the AlN nucleation layer is smaller than that on the second region of the sapphire substrate surface, so that the finally formed GaN buffer layer has a flat top surface. Specifically, the GaN material grown on AlN nucleation layer 200 is Ga-face GaN buffer layer 310, the GaN material grown on sapphire substrate 100 is N-face GaN buffer layer 320, the thickness of Ga-face GaN buffer layer 310 in the GaN buffer layer is 400nm, and the thickness of N-face GaN buffer layer 320 in the GaN buffer layer is 500nm.
Further, by controlling the growth temperature, the V-III ratio, the growth pressure and other parameters of the GaN material, the growth rates of the Ga-surface GaN buffer layer and the N-surface GaN buffer layer can be well controlled, so that a flat Ga-surface GaN buffer layer and an N-surface GaN buffer layer are generated, and further, a high-quality LED device is obtained.
4) An N-type GaN layer including a Ga-face N-type GaN layer 411 and an N-face N-type GaN layer 421 integrally formed on the GaN buffer layer is grown as shown in fig. 7 d.
Maintaining the temperature in the reaction chamber at 1050 deg.C and pressure at 260mbar, introducing TMGa and NH into the reaction chamber with hydrogen as carrier gas 3 SiH (SiH) 4 Controlling the inflow rate of TMGa to be 240sccm and NH 3 Is 30000sccm, siH 4 The flow rate of the gas was 100sccm to grow an n-type GaN material on the GaN buffer layer, thereby forming an n-type GaN layer having a thickness of 2500 nm. Specifically, the N-type GaN material grown on the Ga-face GaN buffer layer 310 in the GaN buffer layer is a Ga-face N-type GaN layer 411, and the N-type GaN material grown on the N-face GaN buffer layer 320 in the GaN buffer layer is an N-face N-type GaN layer 421.
5) An InGaN/GaN multiple quantum well is grown on the N-type GaN layer, which includes an integrally formed Ga-face InGaN/GaN multiple quantum well layer 412 and N-face InGaN/GaN multiple quantum well layer 422, as shown in fig. 7 e.
The temperature in the reaction chamber was adjusted to 900℃and the pressure to 400mbar, N 2 As carrier gas, TMGa, TMIn and NH are introduced into the reaction chamber 3 To alternately grow three periods of InGaN well layers and GaN barrier layers in sequence on the n-type GaN layer. Specifically, when the InGaN well layer is grown, the flow rate of TMGa is 240sccm, the flow rate of tmin is 100sccm, and nh 3 The flow rate of the InGaN well layer is 30000sccm, and the thickness of the InGaN well layer is 3nm; when growing the GaN barrier layer, the inflow rate of TMGa is 240sccm, NH 3 The flow rate of the GaN barrier layer is 30000sccm, and the thickness of the GaN barrier layer is 2nm; accordingly, the InGaN/GaN multiple quantum well material grown on the Ga-face N-type GaN layer 411 is a Ga-face InGaN/GaN multiple quantum well layer 412, the InGaN/GaN multiple quantum well material grown on the N-face N-type GaN layer 421 is an N-face InGaN/GaN multiple quantum well layer 422, and the content of In component In the Ga-face InGaN/GaN multiple quantum well layer 412 is smaller than that In component In the N-face InGaN/GaN multiple quantum well layer 422.
6) An AlGaN electron blocking layer is grown on the InGaN/GaN multiple quantum well layer, and includes a Ga-face AlGaN electron blocking layer 413 and an N-face AlGaN electron blocking layer 423 integrally formed as shown in fig. 7 f.
The temperature in the reaction chamber is regulated to 1050 ℃, the pressure is regulated to 200mbar, and TMGa, TMAL and NH are introduced into the reaction chamber by taking hydrogen as carrier gas 3 Controlling the TMGa flow rate to be 100sccm, TMAL flow rate to be 30sccm, NH 3 The flow rate of the AlGaN electron blocking layer is 30000scc, so that an AlGaN material grows on the InGaN/GaN multiple quantum well layer, and an AlGaN electron blocking layer with the thickness of 200nm is formed; accordingly, the AlGaN material grown on the Ga-face InGaN/GaN multiple quantum well layer 412 is the Ga-face AlGaN electron blocking layer 413, and the AlGaN material grown on the N-face InGaN/GaN multiple quantum well layer 422 is the N-face AlGaN electron blocking layer 423.
7) A p-type GaN layer is grown on the AlGaN electron blocking layer, and includes a Ga-face p-type GaN layer 414 and an N-face p-type GaN layer 424 integrally formed as shown in fig. 6.
The temperature in the reaction chamber was adjusted to 1050℃and the pressure to 260mbar, N 2 As carrier gas, TMGa and NH are introduced into the reaction chamber 3 And Cp2Mg, controlling the inflow rate of TMGa to be 240sccm and NH 3 The input flow rate of Cp2Mg is 30000sccm and the input flow rate of Cp2Mg is 10sccm, so as to grow p-type GaN material on the AlGaN electron blocking layer, thereby forming a p-type GaN layer with the thickness of 200 nm; accordingly, the p-type GaN material grown on the Ga-face AlGaN electron blocking layer 413 is a Ga-face p-type GaN layer 414, and the p-type GaN material grown on the N-face AlGaN electron blocking layer 423 is an N-face p-type GaN layer 424.
8) Maintaining N-feed to a reaction chamber of an MOCVD apparatus 2 And NH 3 NH is added to 3 The pressure in the reaction chamber was adjusted to 260mbar to activate p-type GaN, after which the temperature of the reaction chamber was reduced to room temperature and the grown epitaxial wafer was removed.
In a specific embodiment, a light emission spectrum of a white light LED device obtained based on an epitaxial wafer of the white light LED device with a bicolor active layer provided by the present invention is shown in fig. 8, wherein an abscissa in the figure is a light emission wavelength, and an ordinate in the figure is a normalized light emission intensity; as can be seen from fig. 8, the wavelengths of the two kinds of light are about 450nm and 550nm, respectively, so that white light can be emitted in a superimposed manner, and the light emission spectra of the two kinds of light show good gaussian curves, which indicates that the white light LED device prepared by the method has good light emission characteristics.
The scheme provided by the invention has the following advantages:
1) According to the preparation method of the epitaxial wafer of the LED device, the inclined sapphire substrate and the control of the growth conditions are adopted, so that the flat material surface is successfully obtained, the surface of the N-face GaN buffer layer is smooth (normally, the N-face GaN surface appearance is poor, the luminous efficiency of the N-face quantum well is low), the control of the growth conditions, the inclined sapphire substrate and the like are adopted to enable the N-face GaN surface to be smooth and flat, the luminous characteristic of the quantum well is improved, the luminous efficiency of the N-face GaN/InGaN multi-quantum well layer is improved, and photoelectric devices such as high-quality LEDs and electronic devices such as HEMTs can be prepared based on the smooth surface, so that the preparation method has practical application value.
2) According to the invention, gaN materials are simultaneously grown on the substrate and the nucleation layer, so that Ga-surface III-nitride materials and N-surface III-nitride materials are simultaneously obtained on the same substrate, and the preparation of a device based on mixed polarity of Ga-surface GaN materials and N-surface GaN materials is realized; and by utilizing the difference of the Ga-surface III-nitride material and the N-surface III-nitride material, the In components In the Ga-surface GaN/InGaN multi-quantum well layer and the N-surface GaN/InGaN multi-quantum well layer are different, the multi-quantum well layers with different light-emitting wavelengths are obtained, the integration of the two light-emitting wavelengths on the same substrate is realized, and the light-emitting characteristic of the device is improved.
3) According to the preparation method of the epitaxial wafer of the white light LED device with the double-color active layer, the Ga-surface active layer and the N-surface active layer are located on the same plane, and the physical process that short-wavelength light passes through the long-wavelength multi-quantum well layer and is absorbed in the light extraction process is avoided, so that the light emission of the two wavelengths is ensured not to be influenced mutually, and the luminous efficiency of the device is improved. Meanwhile, the area ratio of the Ga-surface III-nitride material to the N-surface III-nitride material (namely, the area ratio of the first light-emitting unit to the second light-emitting unit) can be controlled by controlling the area ratio of the etched nucleation layer to the reserved nucleation layer, so that the ratio of the light-emitting areas of the two wavelengths is controlled, the control of the light-emitting intensities of different light-emitting wavelengths is realized, the required double-color light is further obtained, and finally white light illumination is realized.
It should be understood that the above embodiments are merely for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the present invention and implement the same according to the present invention without limiting the scope of the present invention. All equivalent changes or modifications made in accordance with the spirit of the present invention should be construed to be included in the scope of the present invention.

Claims (10)

1. An epitaxial wafer of an LED device, comprising:
a substrate, the surface of the substrate having a first region and a second region adjacent to the first region;
a nucleation layer disposed in the first region;
and the epitaxial structure layer comprises a first light-emitting unit and a second light-emitting unit, the first light-emitting unit is arranged on the nucleation layer, the second light-emitting unit is arranged in the second region, wherein the first light-emitting unit comprises Ga-surface III-nitride materials, and the second light-emitting unit comprises N-surface III-nitride materials.
2. The epitaxial wafer of an LED device of claim 1, wherein: the first light-emitting unit comprises a Ga-surface N-type semiconductor layer, a Ga-surface light-emitting layer, a Ga-surface electron blocking layer and a Ga-surface p-type semiconductor layer which are sequentially stacked and arranged on the nucleation layer, and the second light-emitting unit comprises an N-surface N-type semiconductor layer, an N-surface light-emitting layer, an N-surface electron blocking layer and an N-surface p-type semiconductor layer which are sequentially stacked and arranged on the second area;
wherein the Ga-face N-type semiconductor layer and the N-face N-type semiconductor layer, the Ga-face light-emitting layer and the N-face light-emitting layer, the Ga-face electron blocking layer and the N-face electron blocking layer, the Ga-face p-type semiconductor layer and the N-face p-type semiconductor layer are all integrally formed;
and/or the Ga surface light-emitting layer and the N surface light-emitting layer are positioned in the same plane;
and/or the In component content In the Ga surface light-emitting layer is smaller than the In component content In the N surface light-emitting layer.
3. The LED device epitaxial wafer of claim 2, wherein: the epitaxial wafer further comprises a buffer layer, the buffer layer comprises a Ga surface buffer layer and an N surface buffer layer which are integrally formed, the Ga surface buffer layer is arranged between the nucleation layer and the first light-emitting unit, and the N surface buffer layer is arranged between the second area and the second light-emitting unit;
preferably, the Ga-face buffer layer and the N-face buffer layer are flush against the top surface of the substrate.
4. An epitaxial wafer of an LED device according to any one of claims 1-3, characterized in that: the substrate comprises a sapphire substrate or a silicon carbide substrate; preferably, the sapphire substrate is a sapphire substrate with a chamfer angle, the chamfer angle direction of the sapphire substrate is a c-plane offset m-axis, and the chamfer angle is 1-4 degrees;
and/or, the material of the nucleation layer comprises III nitride, preferably, the nucleation layer comprises AlN nucleation layer or GaN nucleation layer.
5. The preparation method of the epitaxial wafer of the LED device is characterized by comprising the following steps of:
providing a substrate, wherein the surface of the substrate is provided with a first area and a second area adjacent to the first area;
forming a nucleation layer in the first region;
forming an epitaxial structure layer on the nucleation layer, wherein the epitaxial structure layer comprises a first light emitting unit and a second light emitting unit, the first light emitting unit is arranged on the nucleation layer, and the second light emitting unit is arranged on the second region; wherein the first light emitting unit comprises a Ga-face group III nitride material and the second light emitting unit comprises an N-face group III nitride material.
6. The method of manufacturing an epitaxial wafer of an LED device of claim 5, wherein the step of forming an epitaxial structure layer on the nucleation layer comprises:
simultaneously, growing a III-nitride material on the surface of the nucleation layer and the second region, and adjusting the growth parameters of the III-nitride material in the growth process of the III-nitride material to enable the III-nitride material grown on the nucleation layer to form a Ga-surface III-nitride material and enable the III-nitride material grown on the second region to form an N-surface III-nitride material;
wherein the growth parameters include at least one of growth temperature, growth pressure, and V-III ratio of the growth feedstock.
7. The method for manufacturing an epitaxial wafer of an LED device according to claim 6, characterized in that: the first light-emitting unit comprises a Ga-surface N-type semiconductor layer, a Ga-surface light-emitting layer, a Ga-surface electron blocking layer and a Ga-surface p-type semiconductor layer which are sequentially stacked and arranged on the nucleation layer, and the second light-emitting unit comprises an N-surface N-type semiconductor layer, an N-surface light-emitting layer, an N-surface electron blocking layer and an N-surface p-type semiconductor layer which are sequentially stacked and arranged on the second area; wherein the Ga-face N-type semiconductor layer and the N-face N-type semiconductor layer, the Ga-face light-emitting layer and the N-face light-emitting layer, the Ga-face electron blocking layer and the N-face electron blocking layer, the Ga-face p-type semiconductor layer and the N-face p-type semiconductor layer are all integrally formed; the step of forming an epitaxial structure layer on the nucleation layer further comprises:
growing the Ga-surface N-type semiconductor layer and the N-surface N-type semiconductor layer under a first preset condition, wherein the first preset condition comprises the following steps: the growth temperature is 1000-1100 ℃, the growth pressure is 100-400 mbar, and the V-III ratio of the growth raw materials is 500-2000;
and growing the Ga surface light-emitting layer and the N surface light-emitting layer under a second preset condition, wherein the second preset condition comprises the following steps: the growth temperature is 700-900 ℃, the growth pressure is 100-400 mbar, and the V-III ratio of the growth raw materials is 10000-30000;
and growing the Ga-face electron blocking layer and the N-face electron blocking layer under a third preset condition, wherein the third preset condition comprises the following steps: the growth temperature is 1000-1100 ℃, the growth pressure is 100-200 mbar, and the V-III ratio of the growth raw materials is 500-2000;
and growing the Ga-surface p-type semiconductor layer and the N-surface p-type semiconductor layer under a fourth preset condition, wherein the fourth preset condition comprises the following steps: the growth temperature is 1000-1100 ℃, the growth pressure is 100-400 mbar, and the V-III ratio of the growth raw materials is 500-2000.
8. The method of manufacturing an epitaxial wafer of an LED device of claim 5, wherein the step of forming an epitaxial structure layer on the nucleation layer further comprises:
forming a buffer layer on the surface of the nucleation layer and the second region, and forming a flat surface on top of the buffer layer formed by growth;
and growing the epitaxial structure layer on the buffer layer.
9. The method for manufacturing an epitaxial wafer of an LED device according to claim 8, characterized in that: the buffer layer comprises a Ga surface buffer layer and an N surface buffer layer, and the step of forming the buffer layer on the nucleation layer and the substrate comprises the following steps:
and simultaneously growing the Ga surface buffer layer and the N surface buffer layer under a fifth preset condition, so that the Ga surface buffer layer formed by growth is flush with the top surface of the N surface buffer layer, wherein the fifth preset condition comprises the following steps: the growth temperature is 1050-1150 ℃, the growth pressure is 100-400 mbar, and the V-III ratio of the growth raw materials is 100-1000.
10. The method of manufacturing an epitaxial wafer of an LED device of claim 5, wherein the step of forming a nucleation layer in said first region comprises:
forming a nucleation layer on the surface of the substrate, and removing the nucleation layer covering the second region to expose the second region; or alternatively
Covering a mask on the second region; forming a nucleation layer in the first region; the mask is removed to expose the second region.
CN202310179491.XA 2023-02-28 2023-02-28 Epitaxial wafer of LED device and preparation method thereof Pending CN116072779A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310179491.XA CN116072779A (en) 2023-02-28 2023-02-28 Epitaxial wafer of LED device and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310179491.XA CN116072779A (en) 2023-02-28 2023-02-28 Epitaxial wafer of LED device and preparation method thereof

Publications (1)

Publication Number Publication Date
CN116072779A true CN116072779A (en) 2023-05-05

Family

ID=86183697

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310179491.XA Pending CN116072779A (en) 2023-02-28 2023-02-28 Epitaxial wafer of LED device and preparation method thereof

Country Status (1)

Country Link
CN (1) CN116072779A (en)

Similar Documents

Publication Publication Date Title
KR100532650B1 (en) Semiconductor luminous element of iii nitride group
US7638809B2 (en) Light emitting device
TWI416757B (en) Polychromatic wavelengths led and manufacturing method thereof
US8247791B2 (en) Compound semiconductor light emitting element, illuminating apparatus using compound semiconductor light emitting element, and method for manufacturing compound semiconductor light emitting element
US7910154B2 (en) Nitride-based light emitting devices and methods of manufacturing the same
US8716048B2 (en) Light emitting device and method for manufacturing the same
CN101208810A (en) III nitride white light LED
US6562646B2 (en) Method for manufacturing light-emitting device using a group III nitride compound semiconductor
JP3978858B2 (en) Gallium nitride compound semiconductor light emitting device
US20230215977A1 (en) Single chip multi band led
CN109755362B (en) Nitride light-emitting diode with high luminous efficiency
CN109841712B (en) Display-finger-adjustable single-chip white light LED based on pyramid-like type and preparation method thereof
CN116072779A (en) Epitaxial wafer of LED device and preparation method thereof
CN107546305A (en) A kind of GaN base light emitting epitaxial structure
CN113555475B (en) UVLED epitaxial structure, preparation method thereof and UVLED chip
KR100312019B1 (en) Fabrication Method for White Light Emitting Diode Using InGaN Phase Separation
CN106601878A (en) Preparation method for LED with high light efficiency
KR100608919B1 (en) Light-emitting device and method of manufacturing the same
KR20090003384A (en) Nitride light emitting device
CN117790486A (en) Micro-LED chip packaging structure and preparation method thereof
KR100608929B1 (en) Method for fabricating ?-? nitride compound semiconductor ultraviolet light-emitting device
JP4712153B2 (en) Method for producing GaN-based light emitting device
KR20120131147A (en) Light emitting device and method for fabricating the same
CN110707188A (en) Light emitting diode and light emitting diode manufacturing method
JP2004535687A (en) Gallium nitride based LED and method of manufacturing the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination