CN116072716A - Split gate trench MOS device structure and manufacturing method thereof - Google Patents
Split gate trench MOS device structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN116072716A CN116072716A CN202310358043.6A CN202310358043A CN116072716A CN 116072716 A CN116072716 A CN 116072716A CN 202310358043 A CN202310358043 A CN 202310358043A CN 116072716 A CN116072716 A CN 116072716A
- Authority
- CN
- China
- Prior art keywords
- layer
- groove
- trench
- gate
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 239000010410 layer Substances 0.000 claims description 313
- 238000000034 method Methods 0.000 claims description 69
- 230000008569 process Effects 0.000 claims description 60
- 238000002955 isolation Methods 0.000 claims description 41
- 238000000926 separation method Methods 0.000 claims description 36
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 34
- 210000003323 beak Anatomy 0.000 claims description 20
- 241000293849 Cordylanthus Species 0.000 claims description 19
- 230000000694 effects Effects 0.000 claims description 19
- 238000002347 injection Methods 0.000 claims description 19
- 239000007924 injection Substances 0.000 claims description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 19
- 229920005591 polysilicon Polymers 0.000 claims description 19
- 229910052721 tungsten Inorganic materials 0.000 claims description 15
- 239000010937 tungsten Substances 0.000 claims description 15
- 239000011229 interlayer Substances 0.000 claims description 14
- 239000011241 protective layer Substances 0.000 claims description 14
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000000227 grinding Methods 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 description 14
- 235000012239 silicon dioxide Nutrition 0.000 description 13
- 239000007943 implant Substances 0.000 description 12
- 230000008878 coupling Effects 0.000 description 11
- 238000010168 coupling process Methods 0.000 description 11
- 238000005859 coupling reaction Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 10
- 230000001965 increasing effect Effects 0.000 description 9
- 230000002708 enhancing effect Effects 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 210000000746 body region Anatomy 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000001808 coupling effect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
Abstract
A first groove is formed on a substrate in the manufacturing process of the split gate trench MOS device structure and then etching is further carried out from the bottom of the first groove to form a second groove, the bottom of the etched second groove is arc-shaped, the transverse dimension is larger than that of the first groove, and then a field plate layer with a second thickness is formed at the bottom and the side wall part of the second groove, so that the second thickness is larger than the first thickness.
Description
Technical Field
The invention relates to the field of semiconductor devices, in particular to a split gate trench MOS device structure and a manufacturing method thereof.
Background
Because of its charge coupling effect, the SGT (split-gate-trench) structure can obtain higher breakdown voltage under the condition of adopting the same doping concentration of epitaxy specification, and one main flow direction of the current SGT device design is to obtain lower specific on-resistance, and the size of unit cell needs to be reduced as much as possible. It is known that the conventional SGT structure is characterized by implementing charge coupling by growing a thick oxide layer on the inner wall of the trench, and especially for medium-high voltage SGT products, the higher the breakdown voltage of the device, the thicker the oxide layer is required, while the larger the size of the designed trench is for the polysilicon filling of the subsequent process to be more complete, which limits the further reduction of the cell size. In addition, due to the limitation of the accuracy of the photolithography and etching machine, such as the minimum photolithography line width, the minimum etching line width, and the alignment accuracy between layers, when the cell size is reduced to a certain extent, the cell size cannot be reduced again, otherwise, the process stability will be affected, so that the electric leakage of the device is increased, the breakdown voltage is reduced, and the uniformity of the device performance in the wafer surface is reduced, thereby greatly reducing the product yield. It is apparent that the structural features of conventional SGTs prevent further reductions in the unit cell size of medium-high voltage SGTs.
Disclosure of Invention
The invention mainly solves the technical problems by providing the structure and the manufacturing method of the split gate type MOS device, on the basis of not increasing the cost of the existing process, the existing equipment is utilized, a high-precision machine is not required to be additionally increased, the cell size can be effectively reduced, the on-resistance of the device is reduced, the performance of the device is ensured, and the stable high yield is ensured.
According to a first aspect, a method for manufacturing a split gate trench MOS device structure is provided, including the steps of: providing a substrate, and etching the substrate to form a first groove; sequentially forming a buffer layer with a first thickness and a side wall protection layer on the side wall of the first groove; further etching from the bottom of the first groove to form a second groove, wherein the bottom of the second groove is arc-shaped, and the transverse dimension of the second groove is larger than that of the first groove; forming a field plate layer with a second thickness at the bottom and the side wall part of the second groove, wherein the second thickness is larger than the first thickness, and a beak connecting part is formed at the joint of the field plate layer and the buffer layer, and comprises a part of the field plate layer close to the position of the first groove and a part of the buffer layer close to the field plate layer, and the part of the field plate layer and the part of the buffer layer have gradients in the thickness direction; the first groove and the second groove jointly form a separation gate groove, and a separation gate, an isolation layer and a control gate are formed in the separation gate groove.
Optionally, the forming the buffer layer and the sidewall protection layer with the first thickness on the sidewall of the first trench sequentially includes the steps of: a buffer layer grows on the surfaces of the bottom and the side wall parts of the first groove; forming a protective layer on the buffer layer; and removing the buffer layer and the protective layer at the bottom of the first groove by using an etching process, so that the protective layer is a side wall protective layer and the bottom of the first groove is exposed.
Optionally, the material of the buffer layer is silicon oxide, and the material of the side wall protection layer is silicon nitride.
Optionally, the etching is further performed from the bottom of the first trench to form a second trench, where the bottom of the second trench is arc-shaped, and the lateral dimension of the second trench is greater than that of the first trench, and the step of: and continuing etching from the bottom of the first groove to the vertical direction and the horizontal direction by using a dry etching process, and continuously adjusting etching conditions in the etching process to form a second groove, wherein the second groove is connected with the first groove, and the bottom and the top of the second groove are continuously etched into an arc shape by the continuously adjusted etching conditions.
Optionally, forming a field plate layer of a second thickness at the bottom and sidewall portions of the second trench includes: and growing silicon oxide on the bottom and the side wall surfaces of the second groove by using a furnace tube process, wherein the thickness of the field plate layer is a second thickness which is more than 20 times of the first thickness.
Optionally, the second thickness is determined according to a width of the second trench and a bird's beak effect when forming the field plate layer.
Optionally, after providing the substrate, before etching the substrate, the method further comprises the steps of: and forming a mask layer on the upper surface of the substrate, wherein the mask layer comprises an oxide layer, a nitride layer and an ONO film layer formed by the oxide layer, the nitride layer and the oxide layer which are deposited in sequence.
Optionally, the first trench and the second trench together form a separation gate trench, and forming a separation gate, an isolation layer and a control gate in the separation gate trench includes the steps of: depositing a layer of highly doped polysilicon in the separation gate trench by using a furnace tube process; the highly doped polysilicon is polished flush with the mask layer using a CMP process: etching the high-doped polysilicon to the depth of the first groove or below by using a dry etching process to form a separation gate; removing the side wall protection layer; removing the buffer layer; depositing an oxide layer over the separation gate; grinding the oxide layer to be flush with the mask layer through a CMP process, and then carrying out wet etching back on the oxide layer of a partial area through a photoetching process to form an isolation layer used for isolating between the control gate and the isolation gate; and growing a gate oxide layer on the side wall of the groove above the isolation layer by using a furnace tube process, depositing a layer of highly doped polysilicon, and etching the highly doped polysilicon back to be flush with or below the surface of the substrate again to form a control gate.
Optionally, the method further comprises the steps of: and sequentially forming a body junction injection layer, a source electrode injection layer, an interlayer dielectric layer, a tungsten plug and surface metal in the substrate to finish the manufacture of the MOS device.
According to a second aspect, in one embodiment, a split gate trench MOS device structure is provided, including: a substrate; the isolation gate groove comprises a first groove and a second groove, the second groove is positioned at the bottom of the first groove and is connected with the first groove, the bottom of the second groove is arc-shaped, and the transverse dimension of the second groove is larger than that of the first groove; the field plate layer is positioned at the bottom and the side wall surface of the second groove, the gate oxide layer is positioned at the side wall surface of the first groove, a beak connecting part is arranged at the joint of the field plate layer and the gate oxide layer, the beak connecting part comprises a part of field plate layer close to the position of the first groove and a part of gate oxide layer close to the field plate layer, and the part of field plate layer and the part of gate oxide layer have gradients in the thickness direction; the isolation layer is positioned in the isolation gate groove and is used for isolating the isolation gate and the control gate.
Optionally, the method further comprises: the semiconductor device comprises a body junction injection layer, a source electrode injection layer, an interlayer dielectric layer, a tungsten plug and a surface metal layer, wherein the body junction injection layer is positioned in the substrate, the source electrode injection layer is positioned in the body junction injection layer, the interlayer dielectric layer is positioned on the upper surface of the substrate, the tungsten plug penetrates from the body junction injection layer to the interlayer dielectric layer, and the surface metal layer is connected with the tungsten plug.
Optionally, the thickness of the field plate layer is 5000 a-7500 a, and the thickness of the field plate layer is more than 20 times of the thickness of the gate oxide layer.
Optionally, the separation grid is located below the first groove, the isolation layer is located above the separation grid, the upper surface of the isolation layer is higher than the upper part of the beak connecting part, and the control grid is located above the isolation layer.
According to the split gate trench MOS device structure and the manufacturing method thereof, since the first trench is formed on the substrate, the buffer layer and the sidewall protection layer with the first thickness are sequentially formed on the sidewall of the first trench, then the second trench is formed by further etching from the bottom of the first trench, the bottom of the etched second trench is arc-shaped, and the lateral dimension is larger than that of the first trench, and then the field plate layer with the second thickness is formed on the bottom and the sidewall of the second trench, so that the second thickness is larger than the first thickness, so that due to the beak effect, a beak connection part is formed at the connection part of the field plate layer and the buffer layer, and the beak connection part comprises a part of the field plate layer close to the position of the first trench, and a part of the gate oxide layer has a gradient in the thickness direction, which is favorable for enhancing charge coupling, and improving the breakdown voltage of the device.
Drawings
FIG. 1 is a schematic diagram of a cross-sectional structure of a middle stage in a manufacturing process according to the present embodiment;
FIG. 2 is a schematic diagram showing a cross-sectional structure of the middle stage of the manufacturing process according to the second embodiment;
FIG. 3 is a third schematic sectional view of the middle stage of the manufacturing process according to the present embodiment;
FIG. 4 is a schematic diagram showing a cross-sectional structure of the middle stage in the manufacturing process according to the present embodiment;
FIG. 5 is a schematic diagram showing a cross-sectional structure of the middle stage in the manufacturing process according to the present embodiment;
FIG. 6 is a schematic diagram showing a cross-sectional structure of the middle stage in the manufacturing process according to the present embodiment;
FIG. 7 is a schematic diagram of a middle stage cross-sectional structure of the manufacturing process according to the present embodiment;
FIG. 8 is a schematic diagram of a cross-sectional structure of a middle stage in the manufacturing process according to the present embodiment;
FIG. 9 is a schematic diagram of a middle stage cross-sectional structure of the manufacturing process according to the present embodiment;
FIG. 10 is a schematic cross-sectional view of a middle stage of the manufacturing process according to the present embodiment;
FIG. 11 is a schematic diagram of a cross-sectional structure of a middle stage of a manufacturing process according to the present embodiment;
fig. 12 is a schematic structural diagram of a split gate trench MOS device according to this embodiment;
fig. 13 is a schematic diagram of a bird's beak effect structure according to the present embodiment.
In the figure: 100-substrate; 200-masking layers; 110-a first trench; 120-a second trench; 300-a buffer layer; 400-a sidewall protection layer; 500-field plate layers; 600-beak connecting part; 701-a separation gate; 702-an isolation layer; 703-a control gate; 800-gate oxide layer; 900-body tie implant layer; 901-a source implant layer; 902-an interlayer dielectric layer; 903-tungsten plug; 904—surface metal; 10-silicon nitride; 20-silicon dioxide; 30-silicon.
Detailed Description
The invention will be described in further detail below with reference to the drawings by means of specific embodiments. Wherein like elements in different embodiments are numbered alike in association. In the following embodiments, numerous specific details are set forth in order to provide a better understanding of the present application. However, one skilled in the art will readily recognize that some of the features may be omitted, or replaced by other elements, materials, or methods in different situations. In some instances, some operations associated with the present application have not been shown or described in the specification to avoid obscuring the core portions of the present application, and may not be necessary for a person skilled in the art to describe in detail the relevant operations based on the description herein and the general knowledge of one skilled in the art.
Furthermore, the described features, operations, or characteristics of the description may be combined in any suitable manner in various embodiments. Also, various steps or acts in the method descriptions may be interchanged or modified in a manner apparent to those of ordinary skill in the art. Thus, the various orders in the description and drawings are for clarity of description of only certain embodiments, and are not meant to be required orders unless otherwise indicated.
The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The terms "coupled" and "connected," as used herein, are intended to encompass both direct and indirect coupling (coupling), unless otherwise indicated.
It is clear from the background that, at present, especially for medium-high voltage SGT products, the shrinking of the unit cell size is hindered due to the contradiction between the electrical properties and the structure of the SGT product itself.
According to analysis, the traditional SGT structure is characterized in that charge coupling is realized by growing a thick oxide layer on the inner wall of a groove, for medium-high voltage SGT products, the higher the breakdown voltage of the device is, the thicker the oxide layer is required, and for the completion of polysilicon filling in the subsequent process, the designed groove size is increased, so that the further reduction of the unit cell size is limited. In addition, due to the limitation of the accuracy of the photolithography and etching machine, such as the minimum photolithography line width, the minimum etching line width, and the alignment accuracy between layers, when the cell size is reduced to a certain extent, the cell size cannot be reduced any more, otherwise, the process stability will be affected, so that the electric leakage of the device is increased, the breakdown voltage is reduced, and the uniformity of the device performance in the wafer surface is reduced, thereby greatly reducing the product yield. Obviously, the shrinking of the unit cell size of the medium-high voltage SGT is limited by the structure of the current SGT, so that a new split gate trench MOS device structure is proposed, the cell size can be effectively reduced, the on-resistance of the device is reduced, the device performance is ensured, and the stable high yield is ensured by utilizing the existing equipment without increasing the cost of the existing process.
In the embodiment of the invention, the device needs to obtain lower specific on-resistance, and the size of a unit cell is reduced as much as possible, so that a first groove is formed on a substrate, a buffer layer with a first thickness and a side wall protection layer are sequentially formed on the side wall of the first groove, then etching is further performed from the bottom of the first groove to form a second groove, the bottom of the etched second groove is arc-shaped, the transverse size is larger than that of the first groove, a field plate layer with a second thickness is formed at the bottom and the side wall of the second groove, the second thickness is larger than the first thickness, and therefore, due to the beak effect, a beak connecting part is formed at the connecting part of the field plate layer and the buffer layer, the partial field plate layer and the partial gate oxide layer are provided with gradients in the thickness direction, the gradient is favorable for enhancing charge coupling, the breakdown voltage is improved, the size of the device does not need to be increased, the specific on-resistance of the device is reduced, and the on-cell can be reduced, and the on-resistance of the device is stable.
Referring to fig. 1 to 13 in combination, the present embodiment provides a method for manufacturing a split gate trench MOS device structure, including:
step 1, providing a substrate 100, and etching the substrate 100 to form a first trench 110.
Referring to fig. 1 in combination, the substrate 100 may be a silicon substrate, and the step of etching to form the first trench 110 includes: a mask layer 200 is formed on the upper surface of the substrate 100, then a photoresist is coated on the mask layer 200, and exposed and developed to define a position area of the first trench 110, that is, a patterned mask layer 200 is formed, and etching is performed by using the patterned mask layer 200 as a mask, so as to form the first trench 110.
In this embodiment, a dry etching process is used to etch the location area of the first trench 110 to form the first trench 110. The etching depth of the first trench 110 is controlled to be 1.3 μm to 3.5 μm, and in this embodiment, about 1.5 μm.
Step 2, a buffer layer 300 and a sidewall protection layer 400 with a first thickness are sequentially formed on the sidewalls of the first trench 110.
Referring to fig. 2 in combination, in this embodiment, forming the buffer layer 300 and the sidewall protection layer 400 with the first thickness on the sidewall of the first trench 110 sequentially includes:
first, a buffer layer 300 is grown on the bottom and sidewall surfaces of the first trench 110. Specifically, a layer of silicon dioxide is thermally grown on the bottom surface and the side wall surface of the first trench 110 by using a furnace tube, and the silicon dioxide is used as a material of the buffer layer 300, so that the stress during the subsequent deposition of the protective layer can be reduced, and the electrical performance of the device can be improved.
Second, a protective layer is formed on the buffer layer 300. Specifically, a NIT layer or silicon nitride layer can be deposited on the silicon dioxide layer as a protective layer. The thickness of the protective layer in this embodiment may be 2000 a-4000 a.
It will be appreciated that the thickness of the protection layer is determined by the width of the first trench 110 and the bird's beak effect in the subsequent process (i.e. in the LOCOS process, since oxygen diffusion in silicon dioxide is an isotropic process, oxygen will also diffuse laterally through the underlying silicon nitride layer, and silicon dioxide will grow under the silicon nitride layer near the etched window), the protection layer is too thick, the width of the trench is insufficient, the subsequent bird's beak effect will be small, if it is too thin, the bird's beak effect will be too strong, and the protection layer will not act as a barrier oxide layer. Therefore, the thickness of the protection layer needs to be estimated according to the device requirement, and the thickness of the protection layer in this embodiment may be 2000 a-4000 a, so that the device performance and the required beak effect can be considered.
Third, the buffer layer 300 and the protective layer at the bottom of the first trench 110 are removed by using an etching process, so that the buffer layer 300 and the protective layer on the surface of the sidewall of the first trench 110 remain, and the bottom of the first trench 110 is exposed. The silicon nitride layer located on the sidewall surface of the first trench 110 serves as a sidewall protection layer 400 capable of protecting the silicon oxide layer under the sidewall of the first trench 110.
And step 3, further etching from the bottom of the first trench 110 to form a second trench 120, wherein the bottom of the second trench 120 is arc-shaped, and the lateral dimension is larger than that of the first trench 110.
The etching may be continued from the bottom of the first trench 110 by using a dry etching process, which is a key step, and etching is continued from the bottom of the first trench 110 to the vertical direction and the horizontal direction by using a dry etching process, and etching conditions are continuously adjusted during the etching process to form a second trench 120, wherein the second trench 120 is connected with the first trench 110, and the bottom of the second trench 120 is in an arc shape, and the lateral dimension is larger than the shape of the lateral dimension of the first trench 110 in the previous step. It will be appreciated that, during the actual etching process, the top of the second trench 120 may be arc-shaped, or may be etched so that the top is parallel and square, which extends laterally like two sides.
In this embodiment, the second trench 120 is etched to be wider than the first trench 110, so that the device spacing between two adjacent cells located at the bottom (in the second trench 120) is smaller on the whole cell, so that the resistance of the device can be reduced by using a thicker epitaxy, and the window size of the process of the upper half of the device is not affected, which can also achieve the purpose of reducing the device resistance while guaranteeing the size of the device to a certain extent.
And 4, forming a field plate layer 500 with a second thickness at the bottom and the side wall of the second groove 120.
Referring to fig. 4 in combination, forming a field plate layer 500 of a second thickness at the bottom and sidewall portions of the second trench 120 includes: and growing SiO2 on the bottom and side wall surfaces of the second groove 120 by using a furnace tube process, wherein the thickness of the field plate layer 500 is a second thickness which is more than 20 times of the first thickness as the field plate layer 500.
It should be noted that the second thickness is determined according to the width of the second trench 120 and the bird's beak effect when forming the field plate layer 500.
The thickness of the field plate layer 500 is the second thickness, and varies with the thickness of the voltage-resistant layer, for example, the corresponding correspondence between the device voltage-resistant layer and the thickness of the field plate layer 500 may be: 80V to 150V, and the corresponding thickness is 5000A-7500A. For example, in this embodiment: about 80V corresponds to a thickness of 5000 a; about 100V is 6000A; approximately corresponding to a thickness of 7500 a around 150V.
The second thickness is larger than the first thickness. In forming the field plate layer 500, the bird's beak effect occurs due to the presence of the sidewall protection layer 400 near the first trench 110 (referred to as LOCOS process, since oxygen diffusion in silicon dioxide is an isotropic process, oxygen also diffuses laterally through the underlying liner silicon dioxide layer, silicon dioxide grows under the silicon nitride layer near the etched window, and reference is made to fig. 13), so that the field plate layer 500 has a gradient in the thickness direction near the first trench 110 and forms a connection with the buffer layer 300, and a bird's beak connection 600 is formed at the junction of the field plate layer 500 and the buffer layer 300, the bird's beak connection 600 includes a portion of the field plate layer 500 near the first trench 110 and a portion of the buffer layer 300 near the field plate layer 500, and the portion of the field plate layer 500 and the portion of the buffer layer 300 have a gradient in the thickness direction (the bird's beak effect can be combined with the shape of reference to fig. 13). The bird's beak connection part 600 is beneficial to enhancing charge coupling and improving breakdown voltage of the device, but does not need to enlarge the cell size, thus being beneficial to further shrinking the unit cell size, besides enhancing charge coupling by having a thicker field plate layer 500.
In step 5, the first trench 110 and the second trench 120 together form a separation gate 701trench, and a separation gate 701, an isolation layer 702 and a control gate 703 are formed in the separation gate 701 trench.
Referring to fig. 5 to 8 in combination, forming the separation gate 701, the isolation layer 702 and the control gate 703 in the separation gate 701trench includes the steps of:
first, as shown in fig. 5, a furnace process is used to deposit highly doped polysilicon in the isolation gate 701trench, and then a CMP process is used to polish the highly doped polysilicon to be level with the mask layer 200.
In the second step, as shown in fig. 6, the highly doped polysilicon is etched to a depth of the first trench 110 or less using a dry etching process to form a separation gate 701, and the sidewall protection layer 400 and the buffer layer 300 are etched away.
Third, as shown in fig. 7 (since the left trench only demonstrates the extraction to the separation gate 701, in reality the separation gate 701 of the right trench and the left trench is connected somewhere, the 0 potential is extracted through this left trench, and the present application is simplified, the demonstration is stopped from the trench on the left after fig. 7), the isolation layer 702 is formed.
The forming of the isolation layer 702 may specifically include the steps of: an oxide layer is deposited over the separation gate 701 to cover the separation gate 701, and then the oxide layer is polished down to be flush with the mask layer 200 by a CMP process, and then the oxide layer with a partial thickness is etched back by a wet process by a photolithography process, thereby forming an isolation layer 702 for isolating between the control gate 703 and the separation gate 701. The isolation layer 702 is an oxide layer with an insulating function, and may be silicon oxide.
In the process of manufacturing the isolation layer 702, the isolation layer 702 is etched back, and the position of the etching back is related to the depth of the body region, and the depth of the isolation layer is required to be slightly deeper than the depth of the body region, but not too deep, and not shallower than the depth of the body region. The body region is the body implant 900 in a subsequent fabrication step. In addition, since the top surface of the mask layer 200 is an oxide layer in the CMP process, when the CMP process is performed to planarize the entire upper surface of the device, the oxide layer on the top layer is polished off, polished to the surface of nitride, and then subjected to the photolithography process, and the oxide layer in a partial region in the trench is wet etched back to form the isolation layer 702 between the control gate 703 and the isolation gate 701.
Fourth, as shown in fig. 8, a gate oxide layer 800 is grown on the sidewall of the trench above the isolation layer 702 by a furnace process, a layer of highly doped polysilicon is deposited, and the highly doped polysilicon is etched back again to be flush with or below the surface of the substrate 100 to form a control gate 703.
After the deposition of the highly doped polysilicon, the upper surface of the entire device is polished down by a CMP process, which requires the entire upper mask layer 200 to be polished away, before the back-gouging of the highly doped polysilicon in the trench.
The formed gate oxide layer 800 can be further previously grown with a sacrificial layer and removed by a wet process, so that the buffer layer 300 on the surface of the side wall part is prevented from being damaged due to the lattice bombarded by plasma, therefore, a furnace tube process is used for growing a sacrificial layer, the damaged surface is removed by the sacrificial layer, and then the gate oxide layer 800 with better quality is grown, so that the protection effect is better. The gate oxide layer 800 may be an oxide metal layer having an insulating effect.
The material of the regrown gate oxide layer 800 is essentially the same as that of the buffer layer 300 in the foregoing, but the regrowth of the material in this embodiment can improve the effect and control the thickness of the material better to ensure the electrical performance of the device, and the thickness of the gate oxide layer 800 is the same as that of the buffer layer 300 and may be 200 a-500 a.
Note that the control gate 703 and the separation gate 701 in this embodiment are highly doped, so that parasitic resistance of the device can be reduced as much as possible. The high doping may also be understood as heavy doping, meaning that the amount of impurities incorporated into the semiconductor material is relatively large. The doping concentration is one thousandth or more and the heavy doping is calculated. For example, the impurity concentration in the silicon single crystal reaches more than 10-18 atoms per cubic centimeter. Light doping may be up to one part per billion.
After the above preparation, further steps are required to form a body junction injection layer 900, a source electrode injection layer 901, an interlayer dielectric layer 902, a tungsten plug 903 and a surface metal 904, so as to complete the manufacture of the MOS device.
As shown in fig. 9, a body implant layer 900 may be formed in the substrate 100 by a plurality of ion implantations, and a source implant layer 901 may be formed in a portion of the depth of the body implant layer 900 by a plurality of ion implantations. The source implant layer 901 is masked and has implants only in the cell region.
As shown in fig. 10, an oxide layer is deposited to form an interlayer dielectric layer 902 on the surface of the substrate 100, then a patterned photoresist is coated on the upper surface of the interlayer dielectric layer 902 to define a tungsten plug 903 region, a contact hole is formed by dry etching, and the contact hole is etched to the bottom of the source injection layer 901 to form a tungsten plug 903, and tungsten is filled for extraction.
As shown in fig. 11, the deposition of the surface metal 904 is performed, and the final implementation of the device is completed through a series of subsequent processes such as thinning of the surface metal 904 using a chemical polishing method, back gold and dicing.
The split gate trench MOS device obtained by the manufacturing method in this embodiment, due to optimization of the trench etching process, utilizes the beak effect to form the beak connection part 600 at the junction of the field plate layer 500 and the buffer layer 300, where the beak connection part 600 includes a part of the field plate layer 500 near the first trench 110 and a part of the gate oxide layer 800 near the field plate layer 500, where the part of the field plate layer 500 and the part of the gate oxide layer 800 have gradients in the thickness direction, and the gradients are beneficial to enhancing charge coupling and increasing the breakdown voltage of the device, so that the specific on-resistance of the device can be ensured without increasing the size of the trench, thereby achieving the purposes of effectively reducing the cell size, reducing the on-resistance of the device, guaranteeing the device performance and stable high yield, effectively reducing the cell size of the medium-high voltage SGT, thereby further reducing the on-resistance, and simultaneously taking into account the process window of the surface channel region, and guaranteeing the uniformity and yield of the device.
Referring to fig. 12, based on the foregoing embodiment, there is further provided a split gate 701trench MOS device structure in this embodiment, including: a base 100, the base 100 may be a silicon substrate.
The separation gate 701 comprises a first trench 110 and a second trench 120, the second trench 120 is located at the bottom of the first trench 110 and is connected with the first trench 110, the bottom of the second trench 120 is arc-shaped, and the lateral dimension of the second trench is larger than that of the first trench 110. The etching depth of the first trench 110 is controlled to be 1.3 μm to 3.5 μm, for example, about 1.5 μm.
The second trench 120 is etched to be wider than the first trench 110, so that the device spacing between two adjacent cells located at the bottom (in the second trench 120) is smaller on the whole cell, so that the resistance of the device can be reduced by using a thicker epitaxy, and the size of the window of the process of the device at the upper half is not affected, so that the size of the device is reduced to a certain extent.
The field plate layer 500 and the gate oxide layer 800, the field plate layer 500 is located on the bottom and the side wall surface of the second trench 120, the thickness of the field plate layer 500 is 5000 a-7500 a, and the thickness of the field plate layer is more than 20 times of the thickness of the gate oxide layer 800. The gate oxide layer 800 is located on a side wall surface of the first trench 110, wherein a bird's beak connection part 600 is formed at a junction of the field plate layer 500 and the gate oxide layer 800, the bird's beak connection part 600 includes a portion of the field plate layer 500 near the first trench 110 and a portion of the gate oxide layer 800 near the field plate layer 500, and the portion of the field plate layer 500 and the portion of the gate oxide layer 800 have a gradient in a thickness direction. The second thickness is greater than the first thickness. In forming the field plate layer 500, a bird's beak effect may occur (refer to LOCOS process, in which oxygen is diffused in silicon dioxide as an isotropic process, so oxygen is also diffused laterally through the pad silicon dioxide layer under the silicon nitride, and silicon dioxide grows under the silicon nitride layer near the etching window, and reference may be made to fig. 13, in which silicon nitride 10, silicon oxide, silicon dioxide 20, and silicon substrate 30) and a bird's beak connection 600 is formed at the junction of the field plate layer 500 and the gate oxide layer 800, and the bird's beak connection 600 includes a portion of the field plate layer 500 near the first trench 110 and a portion of the gate oxide layer 800 near the field plate layer 500, and may be combined to refer to the bird's beak effect in fig. 13. The bird's beak connection part 600 is beneficial to enhancing charge coupling and improving breakdown voltage of the device, but does not need to enlarge the cell size, thus being beneficial to further shrinking the unit cell size, besides enhancing charge coupling by having a thicker field plate layer 500.
A separation gate 701, an isolation layer 702 and a control gate 703 inside the separation gate 701trench, wherein the isolation layer 702 isolates the separation gate 701 and the control gate 703. The separation gate 701 is located below the first trench 110, the isolation layer 702 is located above the separation gate 701 and has an upper surface higher than the beak connection part 600, and the control gate 703 is located above the isolation layer 702.
Further comprises: the body implant layer 900 located inside the substrate 100, a source implant layer 901 located at a partial thickness inside the body implant layer 900, an interlayer dielectric layer 902 located on the upper surface of the substrate 100, a tungsten plug 903 penetrating from the body implant layer 900 to the interlayer dielectric layer 902, and a surface metal 904 layer connected to the tungsten plug.
In fig. 12, the left region 101 is a split gate lead-out, and in reality, the split gates of the right region 102 and the left region 101 are connected to each other at a certain place, and are led out through the left region 101 to be connected to a potential of 0.
In the split gate trench MOS device structure in this embodiment, since the split gate trench is divided into the first trench and the second trench, and the beak connection portion formed by using the beak effect is changed by changing the shape of the second trench, the field plate charge coupling effect is enhanced, so that a lower specific on-resistance is obtained in the same cell size. Meanwhile, the process window of the surface channel region is considered, and the consistency and the yield of the device are ensured.
The foregoing description of the invention has been presented for purposes of illustration and description, and is not intended to be limiting. Several simple deductions, modifications or substitutions may also be made by a person skilled in the art to which the invention pertains, based on the idea of the invention.
Claims (13)
1. The manufacturing method of the split gate trench MOS device structure is characterized by comprising the following steps:
providing a substrate, and etching the substrate to form a first groove;
sequentially forming a buffer layer with a first thickness and a side wall protection layer on the side wall of the first groove;
further etching from the bottom of the first groove to form a second groove, wherein the bottom of the second groove is arc-shaped, and the transverse dimension of the second groove is larger than that of the first groove;
forming a field plate layer with a second thickness at the bottom and the side wall part of the second groove, wherein the second thickness is larger than the first thickness, and a beak connecting part is formed at the joint of the field plate layer and the buffer layer, and comprises a part of the field plate layer close to the position of the first groove and a part of the buffer layer close to the field plate layer, and the part of the field plate layer and the part of the buffer layer have gradients in the thickness direction;
the first groove and the second groove jointly form a separation gate groove, and a separation gate, an isolation layer and a control gate are formed in the separation gate groove.
2. The method of manufacturing according to claim 1, wherein sequentially forming a buffer layer and a sidewall protection layer of a first thickness on the sidewall of the first trench comprises the steps of:
a buffer layer grows on the surfaces of the bottom and the side wall parts of the first groove;
forming a protective layer on the buffer layer;
and removing the buffer layer and the protective layer at the bottom of the first groove by using an etching process, so that the protective layer is a side wall protective layer and the bottom of the first groove is exposed.
3. The method of manufacturing according to claim 1 or 2, wherein the buffer layer material is silicon oxide and the sidewall protection layer material is silicon nitride.
4. The method of manufacturing of claim 1, wherein the further etching from the bottom of the first trench to form a second trench, the second trench bottom having an arc shape, the lateral dimension being greater than the lateral dimension of the first trench comprises:
and continuing etching from the bottom of the first groove to the vertical direction and the horizontal direction by using a dry etching process, and continuously adjusting etching conditions in the etching process to form a second groove, wherein the second groove is connected with the first groove, and the bottom and the top of the second groove are continuously etched into an arc shape by the continuously adjusted etching conditions.
5. The method of manufacturing of claim 1, wherein forming a field plate layer of a second thickness at a bottom and sidewall portion of the second trench comprises:
and growing silicon oxide on the bottom and the side wall surfaces of the second groove by using a furnace tube process, wherein the thickness of the field plate layer is a second thickness which is more than 20 times of the first thickness.
6. The method of claim 5, wherein the second thickness is determined based on a width of the second trench and a bird's beak effect in forming the field plate layer.
7. The method of manufacturing of claim 1, further comprising the step of, after providing the substrate, before etching the substrate:
and forming a mask layer on the upper surface of the substrate, wherein the mask layer comprises an oxide layer, a nitride layer and an ONO film layer formed by the oxide layer, the nitride layer and the oxide layer which are deposited in sequence.
8. The method of manufacturing of claim 7, wherein the first trench and the second trench together form a split gate trench, the split gate, isolation layer, and control gate being formed within the split gate trench comprising the steps of:
depositing a layer of highly doped polysilicon in the separation gate trench by using a furnace tube process;
the highly doped polysilicon is polished flush with the mask layer using a CMP process:
etching the high-doped polysilicon to the depth of the first groove or below by using a dry etching process to form a separation gate;
removing the side wall protection layer;
removing the buffer layer;
depositing an oxide layer over the separation gate;
grinding the oxide layer to be flush with the mask layer through a CMP process, and then carrying out wet etching back on the oxide layer of a partial area through a photoetching process to form an isolation layer used for isolating between the control gate and the isolation gate;
and growing a gate oxide layer on the side wall of the groove above the isolation layer by using a furnace tube process, depositing a layer of highly doped polysilicon, and etching the highly doped polysilicon back to be flush with or below the surface of the substrate again to form a control gate.
9. The method of manufacturing of claim 1, further comprising the step of:
and sequentially forming a body junction injection layer, a source electrode injection layer, an interlayer dielectric layer, a tungsten plug and surface metal in the substrate to finish the manufacture of the MOS device.
10. A split gate trench MOS device structure comprising:
a substrate;
the isolation gate groove comprises a first groove and a second groove, the second groove is positioned at the bottom of the first groove and is connected with the first groove, the bottom of the second groove is arc-shaped, and the transverse dimension of the second groove is larger than that of the first groove;
the field plate layer is positioned at the bottom and the side wall surface of the second groove, the gate oxide layer is positioned at the side wall surface of the first groove, a beak connecting part is arranged at the joint of the field plate layer and the gate oxide layer, the beak connecting part comprises a part of field plate layer close to the position of the first groove and a part of gate oxide layer close to the field plate layer, and the part of field plate layer and the part of gate oxide layer have gradients in the thickness direction;
the isolation layer is positioned in the isolation gate groove and is used for isolating the isolation gate and the control gate.
11. The split gate trench MOS device structure of claim 10, further comprising: the semiconductor device comprises a body junction injection layer, a source electrode injection layer, an interlayer dielectric layer, a tungsten plug and a surface metal layer, wherein the body junction injection layer is positioned in the substrate, the source electrode injection layer is positioned in the body junction injection layer, the interlayer dielectric layer is positioned on the upper surface of the substrate, the tungsten plug penetrates from the body junction injection layer to the interlayer dielectric layer, and the surface metal layer is connected with the tungsten plug.
12. The split gate trench MOS device structure of claim 10 wherein the field plate layer has a thickness of 5000 a-7500 a and a thickness that is more than 20 times the thickness of the gate oxide layer.
13. The split gate trench MOS device structure of claim 12 wherein the split gate is located below the first trench, the isolation layer is located above the split gate and has an upper surface above the beak connection, and the control gate is located above the isolation layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310358043.6A CN116072716A (en) | 2023-04-06 | 2023-04-06 | Split gate trench MOS device structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310358043.6A CN116072716A (en) | 2023-04-06 | 2023-04-06 | Split gate trench MOS device structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116072716A true CN116072716A (en) | 2023-05-05 |
Family
ID=86175331
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310358043.6A Withdrawn CN116072716A (en) | 2023-04-06 | 2023-04-06 | Split gate trench MOS device structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116072716A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030030104A1 (en) * | 2001-08-10 | 2003-02-13 | Darwish Mohamed N. | Trench MIS device with graduated gate oxide layer |
| CN101002330A (en) * | 2004-04-30 | 2007-07-18 | 西利康尼克斯股份有限公司 | Super trench mosfet including buried source electrode and method of fabricating the same |
| CN101320753A (en) * | 2007-05-29 | 2008-12-10 | 万国半导体股份有限公司 | Double gate manufactured with locos techniques |
| CN103295908A (en) * | 2012-02-28 | 2013-09-11 | 万国半导体股份有限公司 | Method for making gate-oxide with step-graded thickness in trenched DMOS device |
| CN111739936A (en) * | 2020-08-07 | 2020-10-02 | 中芯集成电路制造(绍兴)有限公司 | Semiconductor device and forming method thereof |
-
2023
- 2023-04-06 CN CN202310358043.6A patent/CN116072716A/en not_active Withdrawn
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030030104A1 (en) * | 2001-08-10 | 2003-02-13 | Darwish Mohamed N. | Trench MIS device with graduated gate oxide layer |
| CN101002330A (en) * | 2004-04-30 | 2007-07-18 | 西利康尼克斯股份有限公司 | Super trench mosfet including buried source electrode and method of fabricating the same |
| CN101320753A (en) * | 2007-05-29 | 2008-12-10 | 万国半导体股份有限公司 | Double gate manufactured with locos techniques |
| CN103295908A (en) * | 2012-02-28 | 2013-09-11 | 万国半导体股份有限公司 | Method for making gate-oxide with step-graded thickness in trenched DMOS device |
| CN111739936A (en) * | 2020-08-07 | 2020-10-02 | 中芯集成电路制造(绍兴)有限公司 | Semiconductor device and forming method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8067800B2 (en) | Super-junction trench MOSFET with resurf step oxide and the method to make the same | |
| TWI481030B (en) | Systems and devices including fin transistors and methods of using, making and operating the same | |
| US7494875B2 (en) | Gate etch process for a high-voltage FET | |
| TWI621216B (en) | Method of making embedded memory device with silicon-on-insulator substrate | |
| US8373224B2 (en) | Super-junction trench MOSFET with resurf stepped oxides and trenched contacts | |
| US8372717B2 (en) | Method for manufacturing a super-junction trench MOSFET with resurf stepped oxides and trenched contacts | |
| US9349867B2 (en) | Semiconductor devices and methods for manufacturing the same | |
| US9524910B2 (en) | Semiconductor device and method for manufacturing the same | |
| US20100244125A1 (en) | Power semiconductor device structure for integrated circuit and method of fabrication thereof | |
| US20150311123A1 (en) | Semiconductor device and method for manufacturing the same | |
| TWI509710B (en) | Semiconductor devices having improved gate height uniformity and methods for fabricating same | |
| JP2011071304A (en) | Semiconductor device, and method of manufacturing the same | |
| US10008602B2 (en) | Semiconductor devices and methods for manufacturing the same | |
| CN107994076A (en) | The manufacture method of groove grid super node device | |
| CN105826189B (en) | The forming method and ldmos transistor of ldmos transistor | |
| CN112786677A (en) | Super junction device and manufacturing method thereof | |
| KR20040059957A (en) | Method for fabricating MOS transistor | |
| CN111799161B (en) | Manufacturing method of low-voltage shielded gate field effect transistor | |
| US11869966B2 (en) | Method for forming an insulation layer in a semiconductor body and transistor device | |
| CN108807502A (en) | A kind of manufacturing method of NLDMOS device and LDMOS power devices | |
| TWI435373B (en) | Fully depleted soi device with buried doped layer | |
| CN105529263B (en) | The forming method and ldmos transistor of ldmos transistor | |
| CN116072716A (en) | Split gate trench MOS device structure and manufacturing method thereof | |
| TWI460823B (en) | Methods for fabricating trench metal oxide semiconductor field effect transistors | |
| WO2021223353A1 (en) | Manufacturing method for semiconductor super-junction device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20230505 |
|
| WW01 | Invention patent application withdrawn after publication |