CN116072557A - Chip packaging method and chip packaging structure - Google Patents

Chip packaging method and chip packaging structure Download PDF

Info

Publication number
CN116072557A
CN116072557A CN202211106194.4A CN202211106194A CN116072557A CN 116072557 A CN116072557 A CN 116072557A CN 202211106194 A CN202211106194 A CN 202211106194A CN 116072557 A CN116072557 A CN 116072557A
Authority
CN
China
Prior art keywords
conductive
material layer
photosensitive material
solid
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211106194.4A
Other languages
Chinese (zh)
Inventor
赖振楠
吴奕盛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hosin Global Electronics Co Ltd
Original Assignee
Hosin Global Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hosin Global Electronics Co Ltd filed Critical Hosin Global Electronics Co Ltd
Priority to CN202211106194.4A priority Critical patent/CN116072557A/en
Publication of CN116072557A publication Critical patent/CN116072557A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process

Abstract

The application relates to the technical field of semiconductor preparation, and provides a chip packaging method and a chip packaging structure, wherein the chip packaging method comprises the following steps: providing at least one chip, wherein a plurality of welding pins are arranged above the chip; providing a substrate, wherein a plurality of bonding pads and chips are arranged above the substrate, each welding leg corresponds to each bonding pad, and a conductive area is formed; forming a photosensitive material layer above the substrate, wherein the height of the photosensitive material layer is higher than that of the soldering leg, and forming a through hole at a position of the photosensitive material layer corresponding to each conductive region respectively; and filling the through holes with fluid conductors, and solidifying the fluid conductors to form solid conductors so that the solid conductors are bonded with the conductive areas. The fluid conductor is bonded to the through hole in a fluid transfer mode and solidified to form a solid conductor, so that the bonding efficiency is high.

Description

Chip packaging method and chip packaging structure
Technical Field
The present disclosure relates to semiconductor packaging technology, and more particularly, to a chip packaging method and a chip packaging structure.
Background
Since the advent of packaging technology, the application range has been becoming wider and wider due to its high reliability, convenience, ease of operation, etc., and as the requirements for heat dissipation of chips have become higher and higher, the thinner the package is, the better. In particular, the packaging substrate is gradually developed toward ultra-thin and compact packaging, and it is important for the substrate packaging process to increase the packaging capability of the ultra-thin substrate.
In the semiconductor packaging industry, wire bonding (WireBonding) is a process of using thin metal wires to tightly bond metal wires to bonding pads of a substrate by using heat, pressure and ultrasonic energy, so as to realize electrical interconnection between chips and the substrate and information communication between chips. Under ideal control conditions, electron sharing or atomic interdiffusion can occur between the lead and the substrate, thereby realizing atomic level bonding between the two metals.
At present, the welding feet of the traditional chip are bonded with the bonding pads in the packaging substrate in a forward mounting mode through wire bonding, the wire bonding mode needs wire bonding equipment to bond wires from the welding feet of the chip to the bonding pads of the packaging substrate one by one, bonding efficiency is low, and the conditions of tilting, cracking and the like can occur in the bonding process.
Disclosure of Invention
The main objective of the present application is to provide a chip packaging method and a chip packaging structure, which aim to improve bonding efficiency and prevent the occurrence of warpage, cracking and the like in the bonding process.
In a first aspect, the present application provides a chip packaging method, including:
providing at least one chip, wherein a plurality of welding pins are arranged above the chip;
providing a substrate, wherein a plurality of bonding pads and chips are arranged above the substrate, each welding leg corresponds to each bonding pad, and a conductive area is formed;
forming a photosensitive material layer above the substrate, wherein the height of the photosensitive material layer is higher than that of the soldering leg, and forming a through hole at a position of the photosensitive material layer corresponding to each conductive region respectively;
and filling the through holes with fluid conductors, and solidifying the fluid conductors to form solid conductors so that the solid conductors are bonded with the conductive areas.
In one embodiment of the present application, forming the through holes at the positions of the photosensitive material layer corresponding to each of the conductive regions includes:
coating a photosensitive material layer over the substrate;
placing a mask plate above the substrate, wherein the mask plate is provided with a plurality of light leakage areas, and the light leakage areas respectively correspond to the conductive areas;
and placing ultraviolet light above the mask plate, irradiating the photosensitive material layer corresponding to the light leakage area through the ultraviolet light, and forming a patterned photosensitive material layer through exposure and development.
In one embodiment of the present application, filling each of the through holes with a fluid conductive material includes:
and placing the fluid conductor into the through hole through a spin coater.
In one embodiment of the present application, the fluid conductor is a first fluid conductor or a second fluid conductor; the first fluid conductor is a mixture of a conductive material, a volatile solvent and an adhesive; the second fluid conductor is a mixture of a conductive material and a volatile solvent.
In one embodiment of the present application, the fluid conductor is a first fluid conductor, and the curing the fluid conductor to form a solid conductor comprises:
heating the first fluid conductor to enable conductive materials and adhesives to remain in the through holes;
and irradiating the through holes with ultraviolet light to cure the adhesive, wherein the cured adhesive and the conductive material form the solid conductive object.
In one embodiment of the present application, the fluid conductor is a second fluid conductor, and the curing the fluid conductor to form a solid conductor comprises:
heating the second fluid conductor to leave a conductive material remaining in the through hole;
and irradiating the through hole by laser to enable the conductive material to form the solid conductive object.
In one embodiment of the present application, after the solid conductive object is bonded to the conductive region, the method comprises:
removing the photosensitive material layer and the conductive particles remained above the photosensitive material layer, and filling packaging glue above the substrate; or filling packaging glue above the photosensitive material layer and covering the solid conductive object.
In a second aspect, the present application provides a chip package structure, including: the chip is provided with a plurality of welding pins above; the substrate is provided with a plurality of bonding pads and the chips above, and each bonding pad corresponds to each welding leg; and a plurality of solid conductive objects, wherein each solid conductive object is attached to the side surface of the chip and the upper part of the substrate at intervals, one end of each solid conductive object is bonded with the bonding pad, and the other end of each solid conductive object is bonded with the soldering leg corresponding to the bonding pad.
In an embodiment of the present application, the chip package structure further includes a photosensitive material layer, the photosensitive material layer is provided with a plurality of through holes, and the plurality of through holes respectively accommodate a plurality of the solid conductive objects.
In one embodiment of the present application, the chip packaging structure further includes a packaging adhesive, and the packaging adhesive covers a plurality of the solid conductive objects.
The chip packaging method provided by the application comprises the following steps of: providing at least one chip, wherein a plurality of welding pins are arranged above the chip; providing a substrate, wherein a plurality of bonding pads and chips are arranged above the substrate, each welding leg corresponds to each bonding pad, and a conductive area is formed; forming a photosensitive material layer above the substrate, wherein the height of the photosensitive material layer is higher than that of the soldering leg, and forming a through hole at a position of the photosensitive material layer corresponding to each conductive region respectively; and filling the through holes with fluid conductors, and solidifying the fluid conductors to form solid conductors so that the solid conductors are bonded with the conductive areas. According to the invention, the photosensitive material layer is formed above the substrate, wherein the height of the photosensitive material layer is higher than that of the welding pins, conduction between adjacent welding pins or adjacent welding pads is avoided, a through hole is formed in a conductive area between each corresponding welding pin and each welding pad, after the fluid conductive material is filled in the through hole in a fluid transfer mode, the through hole is solidified to form a solid conductive material, so that bonding of the solid conductive material and the conductive area (namely bonding between the welding pad and the welding pin) is completed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
Fig. 1 shows a flowchart of a chip packaging method according to an embodiment of the present application;
fig. 2 is a cross-sectional view of a chip package structure according to an embodiment of the present application after a photosensitive material layer is formed;
fig. 3 shows a cross-sectional view of a chip package structure provided in an embodiment of the present application when exposed and developed;
fig. 4 is a top view illustrating a through hole formed after exposure and development of a chip package structure according to an embodiment of the present application;
fig. 5 is a cross-sectional view of a chip package structure according to an embodiment of the present application after a fluid conductor is filled in a through hole;
FIG. 6 shows a cross-sectional view of a chip package structure according to an embodiment of the present application when heating a fluid conductor;
fig. 7 is a cross-sectional view of a chip package structure according to an embodiment of the present application, in which a fluid conductive material is cured by ultraviolet irradiation to form a solid conductive material;
fig. 8 is a cross-sectional view showing a chip package structure provided in an embodiment of the present application, with a photosensitive material layer removed and conductive particles remaining thereon;
FIG. 9 is a cross-sectional view of a chip package structure for solid conductive packages according to an embodiment of the present application;
FIG. 10 is a cross-sectional view of another chip package structure according to an embodiment of the present application, wherein a fluid conductor is liquefied and solidified by laser irradiation to form a solid conductor;
fig. 11 is a cross-sectional view of another chip package structure provided in an embodiment of the present application for packaging a substrate, a solid conductive material, and a photosensitive material layer and conductive particles remaining thereon.
The reference numerals are explained as follows:
1. a substrate; 11. a bonding pad; 2. a chip; 21. welding feet; 3. a through hole; 4. a photosensitive material layer; 5. a mask plate; 51. a light leakage area; 52. a light shielding region; 6. ultraviolet light; 61. a fluid conductor; 62. a solid conductive material; 63. conductive particles; 7. an adhesive; 8. packaging glue; 9. a heater.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present application based on the embodiments herein.
In the semiconductor packaging industry, wire bonding (WireBonding) is a process of using thin metal wires to tightly bond metal wires to bonding pads of a substrate by using heat, pressure and ultrasonic energy, so as to realize electrical interconnection between chips and the substrate and information communication between chips. Under ideal control conditions, electron sharing or atomic interdiffusion can occur between the lead and the substrate, thereby realizing atomic level bonding between the two metals.
At present, the welding feet of the traditional chip are bonded with the bonding pads in the packaging substrate in a forward mounting mode through wire bonding, the wire bonding mode needs wire bonding equipment to bond wires from the welding feet of the chip to the bonding pads of the packaging substrate one by one, bonding efficiency is low, and the conditions of tilting, cracking and the like can occur in the bonding process.
Based on the above-mentioned problems, please refer to fig. 1, the present application provides a chip packaging method, which includes:
s1, providing at least one chip 2, wherein a plurality of welding pins 21 are arranged above the chip 2;
s2, providing a substrate 1, wherein a plurality of bonding pads 11 and the chip 2 are arranged above the substrate 1, and each welding leg 21 corresponds to each bonding pad 11 and forms a plurality of conductive areas;
s3, forming a photosensitive material layer 4 above the substrate 1, wherein the height of the photosensitive material layer 4 is higher than that of the soldering leg 21, and forming a through hole 3 at a position of the photosensitive material layer 4 corresponding to each conductive region respectively;
and S4, filling the fluid conductors 61 into the through holes 3, and curing the fluid conductors 61 to form solid conductors 62, so that the solid conductors 62 are bonded with the conductive areas.
The step S1 is specifically that a plurality of fillets 21 are arranged above the chip 2, the fillets 21 are determined according to the electrodes led out from the chip 2, when the number of the led-out electrodes is large, the number of the fillets 21 is large, and when the number of the led-out electrodes is small, the number of the fillets 21 is small, wherein the led-out positions of the fillets 21 of the chip 2 are determined according to the led-out electrodes, and it can be understood that the pitches of the fillets 21 can be regularly distributed or irregularly distributed; s2, specifically, a plurality of bonding pads 11 and at least one chip 2 are arranged above the substrate 1, each bonding pad 11 corresponds to a bonding leg 21 above each chip 2, the corresponding bonding pad 11 and the corresponding bonding leg 21 are electrically connected through conductive bonding, a conductive area is formed through a conductive bonding area, it is to be noted that one surface of the substrate 1, on which the chip 2 and the bonding pad 11 are arranged, is a functional surface, the surface opposite to the functional surface is a non-functional surface, and one surface of the chip 2, on which the bonding leg 21 is arranged, is a functional surface, and the surface opposite to the functional surface is a non-functional surface; step S3, specifically, forming a photosensitive material layer 4 above the substrate 1, wherein the photosensitive material layer 4 covers the bonding legs 21 and all devices lower than the bonding legs 21, so that the overall height of the photosensitive material layer 4 is higher than the height of the bonding legs 21, covering all devices above the substrate 1, and forming a plurality of through holes 3 on the photosensitive material layer 4 through a photoetching development technology, wherein the height of the photosensitive material layer 4 is required to be higher than the height of the bonding legs 21, so that the photosensitive material layer 4 is prevented from flowing between adjacent bonding legs 21 or between adjacent bonding pads 11 when a later-stage fluid electric conductor 61 is introduced above the substrate 1, and the photosensitive material layer 4 does not completely cover all the bonding legs 21 and the bonding pads 11, thereby leading to conduction between the adjacent bonding legs 21 and between the adjacent bonding pads 11; then, the photosensitive material layer 4 of each conductive region is dissolved again, and a through hole 3 is formed, so that the conductive bonding of the conductive region is facilitated. In step S4, specifically, the solid conductive object 62 is bonded to the conductive area by filling the fluid conductive object 61 and curing the fluid conductive object to form the solid conductive object 62, so that the bonding between the plurality of fillets 21 and the plurality of pads 11 can be completed at one time, and the bonding efficiency is improved.
Thus, as shown in fig. 2, by forming the photosensitive material layer 4 above the substrate 1, the height of the photosensitive material layer 4 is higher than that of the bonding legs 21, conduction between adjacent bonding legs 21 or adjacent bonding pads 11 is avoided, a through hole 3 is formed in a conductive area between each corresponding bonding leg 21 and each bonding pad 11, after filling the fluid conductor 61 in the through hole 3 in a fluid transfer manner, the solid conductor 62 is formed by solidification, and thus bonding of the solid conductor 62 and the conductive area (i.e. bonding between the bonding pads 11 and the bonding legs 21) is completed.
Before the step S3, the method further includes: a primer (not shown in the figure) is first spin-coated on the substrate 1, the primer is made of hexamethyldisilane, and then a photosensitive material layer 4 is spin-coated on the primer, the effect of the primer is to increase the adhesion of the photosensitive material layer 4, when the spin-coating of the photosensitive material layer 4 is completed, a pre-baking treatment is performed to cure the surface of the photosensitive material layer 4, and because the photosensitive material layer 4 is in a semi-fluid state, the photosensitive material layer 4 is cured after the pre-baking treatment, is not easy to flow and has good sealing performance.
In one embodiment, the photosensitive material layer 4 is a positive photoresist, the positive photoresist is insoluble to a developing solution before exposure and becomes soluble after exposure, so that the light leakage area 51 of the mask plate 5 corresponds to each conductive area, the through holes 3 are processed in each conductive area through exposure and development, and the position of the corresponding positive photoresist of the light shielding area 52 is not exposed to be insoluble. In step S3, please continue to refer to fig. 3, a positive photoresist is coated over the substrate 1; a mask plate 5 is arranged above the substrate 1, wherein the mask plate 5 is provided with a light leakage area 51 and a light shielding area 52 which are arranged at intervals, the light leakage area 51 corresponds to a plurality of conductive areas respectively, an ultraviolet light 6 is arranged above the mask plate 5, positive photoresist corresponding to the light leakage area 51 is irradiated by the ultraviolet light 6, and a patterned photosensitive material layer 4 is formed through exposure and development.
Wherein, the formation of the patterned photosensitive material layer 4 by exposure and development includes: after the positive photoresist in the area irradiated by the ultraviolet light 6 is sensitive to the developing solution, the developing solution is added into the irradiated area for developing, so that the positive photoresist in the irradiated area is dissolved, and a plurality of through holes 3 are formed.
In another embodiment, the photosensitive material layer 4 is a negative photoresist, the negative photoresist is soluble to the developing solution before exposure and becomes insoluble after exposure, so that the light shielding region 52 of the mask 5 corresponds to the conductive region, the negative photoresist corresponding to other regions of the light leakage region 51 is insoluble, and the conductive region is blocked by the light shielding region 52 during exposure, and can be directly dissolved in the developing solution to form the through hole 3.
In step S3, please continue to refer to fig. 3, a negative photoresist is coated over the substrate 1; the mask 5 is disposed above the substrate 1, wherein the mask 5 has a light leakage area 51 and a light shielding area 52 which are disposed at intervals, the light shielding area 52 corresponds to a plurality of conductive areas, ultraviolet light 6 is disposed above the mask 5, the negative photoresist corresponding to the light shielding area 52 is irradiated by the ultraviolet light 6, and the patterned photosensitive material layer 4 as shown in fig. 4 is formed by exposure and development.
Wherein, the formation of the patterned photosensitive material layer 4 by exposure and development includes: the negative photoresist in the irradiated area is added with the developing solution for developing after the negative photoresist in the irradiated area is sensitive to the developing solution, so that the negative photoresist in the irradiated area is dissolved, and a plurality of through holes 3 are formed.
In any of the above embodiments, the patterned photosensitive material layer 4 can be formed by exposing and developing, and other positions (i.e. between the adjacent bonding pads 21 and between the adjacent bonding pads 11) can be protected by the photosensitive material layer 4, so as to prevent conduction between the adjacent bonding pads 21 and between the adjacent bonding pads 11, and improve the accuracy of conductive bonding of the conductive region between the bonding pads 21 and the bonding pads 11, thereby improving the yield of semiconductor products.
It should be noted that other materials than positive photoresist and negative photoresist may be used to form the photosensitive material layer 4, such as UV resin, UV monomer, and the like.
After the step S3, the method further includes: after development, the developer and water are removed by evaporation, the photosensitive material layer 4 forms a solid film, in the previous step, the photosensitive material layer 4 in a semi-fluid state is cured in a first step by pre-baking, after exposure and development, the developer and water are removed by evaporation, and simultaneously the photosensitive material layer 4 is cured in a second step, so that the photosensitive material layer 4 is more stable, prevented from flowing and has better sealing performance.
In one embodiment, the fluid conductor 61 is a first fluid conductor, which is a mixture of a conductive material, a volatile solvent, and an adhesive 7, wherein the ratio of the adhesive 7, the conductive material, and the volatile solvent is 2:4:4, and the first fluid conductor has conductivity and rheological properties.
In the step S4, referring to fig. 5 to 7, when the fluid conductor 61 is a first fluid conductor, the heater 9 heats the first fluid conductor to evaporate the volatile solvent in the first fluid conductor, so that the conductive material and the adhesive 7 remain in the through hole 3, wherein the adhesive 7 is made of a photo-curable material; the through-hole 3 is irradiated with ultraviolet light to cure the adhesive 7, and the cured adhesive 7 and the conductive material form the solid conductive object 62.
In another embodiment, the fluid conductor 61 is a second fluid conductor that is a mixture of a conductive material and a volatile solvent, wherein the ratio of conductive material to volatile solvent is 6:4, and the second fluid conductor also has conductivity and rheological properties.
In the step S4, as shown in fig. 10, when the fluid conductor 61 is a second fluid conductor, the heater heats 9 the second fluid conductor, evaporates the volatile solvent in the second fluid conductor, so that the conductive material remains in the through hole 3, irradiates the through hole 3 with laser, and liquefies and solidifies the conductive material to form the solid conductor 62.
Therefore, due to the different compositions of the first fluid conductor and the second fluid conductor, the materials left after heating are different, namely, the conductive material and the adhesive 7 are left in the through hole 3 after the first fluid conductor is heated, and the adhesive 7 is cured after ultraviolet irradiation to fix the conductive material on the soldering leg 21, the bonding pad 11 and the chip 2 to form a solid conductor 62; and only the conductive material remains in the through hole 3 after the second fluid conductive material is heated, and the conductive material is liquefied by laser irradiation and then automatically solidified to form a solid conductive material 62 which is fixed on the bonding pad 21, the bonding pad 11 and the chip 2. The fluid conductor 61 is placed in the through hole 3 in a fluid transferring manner, and the fluid conductor 61 in the through hole 3 is solidified in an illumination manner after being heated, so that the conductive bonding between the plurality of solder feet 21 and the plurality of bonding pads 11 can be completed at one time, and the conductive bonding efficiency is greatly improved.
Wherein, the conductive material can be particles, powder or other conductive materials capable of flowing along with the fluid; further, the composition of the fluid conductor 61 is not limited to the above two, as long as it can be cured to form the solid conductor 62.
In addition, as shown in fig. 6, the heating of the fluid conductor 61 is performed by the heater 9, the heater 9 may be an oven or a hot plate, and for convenience of heating, the heater 9 is located below the substrate 1 and is attached below the substrate 1, and the heat of the heater 9 is transferred to the fluid conductor 61 through the substrate 1, so as to achieve the heating effect, and the heating temperature of the fluid conductor 61 is maintained at 100-150 ℃ during the heating process, so as to ensure the heating stability.
In the step S4, further includes: the fluid conductor 61 is placed in the through hole 3 by a spin coater or the fluid conductor 61 is placed in the through hole 3 by an inkjet.
When the device is a spin coater, the fluid conductive material 61 is placed into the through hole 3 by the spin coater, the surface of the photosensitive material layer 4 has conductive residues, and the conductive residues are conductive materials or adhesives 7, and finally the processing is needed; the fluid conductive material 61 is placed in the through hole 3 by the ink jet machine, the fluid conductive material 61 can be precisely sprayed, and residues do not exist on the surface of the photosensitive material layer 4, but the ink jet machine has a limited number of ink jet at each time, and multiple ink jet treatments are needed.
Through the two methods, the fluid conductor 61 can be filled in all the through holes 3 at the same time, the soldering leg 21 and the bonding pad 11 are sequentially bonded without a single conductive lead, the photosensitive material layer 4 has good adhesion and sealing performance after being cured twice, and the fluid conductor 61 can be limited in the through holes 3 through the photosensitive material layer 4, so that the fluid conductor 61 is prevented from overflowing out of the through holes 3.
In addition, besides the above two modes, the fluid conductor 61 may be manually placed in the through hole 3, which will not be described herein.
After the step S004, please refer to fig. 8-9, further including: the photosensitive material layer 4 and the residual conductive particles 63 above the photosensitive material layer are removed by a corrosion or stripping method, and the encapsulation glue 8 is poured above the solid conductive object 62 for encapsulation. After the fluid conductive material 61 is placed in the through hole 3, a plurality of opaque conductive particles 63 remain on the surface of the photosensitive material layer 4, so that in order to avoid the influence of the photosensitive material layer 4 and the conductive particles 63 thereon on the performance of the chip 2 during the later packaging, the photosensitive material layer 4 and the conductive particles 63 thereon need to be removed, and in the above steps, the photosensitive material layer 4 is difficult to be removed after being solidified to form a film twice, so that the photosensitive material layer 4 and the conductive particles 63 remaining thereon are removed by adopting a chemical mode (corrosion) or a physical mode (stripping).
Further, as shown in fig. 9, after removing the photosensitive material layer 4 and the conductive particles 63 remaining thereon, since the conductive areas formed between each bonding pad 11 and each bonding leg 21 are bonded by the solid conductive material 62, in order to protect the solid conductive material 62 and improve the packaging reliability, the packaging adhesive 8 is filled above the solid conductive material 62 for packaging, and after packaging, the damage of the solid conductive material 62 caused by factors such as external vibration moisture can be avoided, thereby improving the bonding reliability.
Alternatively, after the step S004, please continue to refer to fig. 11, the photosensitive material layer 4 and the conductive particles 63 thereon may be optionally not removed, and the photosensitive material layer 4 and the conductive particles 63 thereon may be directly encapsulated by encapsulating compound 8 to protect the conductive particles 63 exposed in the air and the photosensitive material layer 4, and after encapsulation, the encapsulating compound 8 at least covers the solid conductive material 62, preferably, the encapsulating compound 8 needs to cover the solid conductive material 62, the photosensitive material layer 4 and the conductive particles 63 thereon, and the substrate 1, so that after encapsulation, damage to the semiconductor device caused by factors such as external vibration moisture may be avoided, and reliability of the semiconductor device is improved.
In the first packaging method, the photosensitive material layer 4 and the conductive particles 63 thereon are removed by etching or stripping, which is a preferred embodiment, so that the performance of the chip 2 is not affected during the later use or processing, and the product yield of the semiconductor device is improved.
With continued reference to fig. 9 and 11, the embodiment of the present application further provides a chip package structure, including a substrate 1, a chip 2, and a plurality of solid conductive objects 62; a plurality of welding pins 21 are arranged above the chip 2; a plurality of bonding pads 11 and chips 2 are arranged above the substrate 1, and each bonding pad 11 corresponds to each welding leg 21; each solid conductive object 62 is attached to the side surface of the chip 2 above the substrate 1 at intervals, one end of each solid conductive object 62 is bonded to the bonding pad 11, and the other end of each solid conductive object 62 is bonded to the corresponding bonding pad 21 of the bonding pad 11.
Further, the chip package structure further comprises a photosensitive material layer 4, the photosensitive material layer 4 is provided with a plurality of through holes 3, and the through holes 3 respectively accommodate a plurality of solid conductors 62. After the photosensitive material layer 4 is patterned, a through hole 3 is formed in a connection area between the corresponding soldering leg 21 and the bonding pad 11, and a solid conductive object 62 is contained in the through hole 3, so that conductive bonding between the soldering leg 21 and the bonding pad 11 is completed, and the patterned photosensitive material layer 4 is formed in an exposure and development mode, so that the solid conductive object 62 is contained in the corresponding through hole 3 in a later period, and the bonding efficiency is greatly improved.
Furthermore, the chip packaging structure further comprises a packaging adhesive 8, and the packaging adhesive 8 covers a plurality of the solid conductors 62, so that the solid conductors 62 can be prevented from being damaged due to factors such as external vibration water vapor and the like, and the bonding reliability is improved.
Referring to fig. 8-9, in one embodiment, after removing the photosensitive material layer 4 and the residual conductive particles 63 thereon, encapsulating the solid conductive material 62 with the encapsulating compound 8, and after encapsulating, encapsulating the solid conductive material 62 with the encapsulating compound 8 covering the solid conductive material 62, removing the photosensitive material layer 4 and the conductive particles 63 thereon, thereby avoiding influencing the performance of the chip 2 during later use or processing and improving the product yield of the semiconductor device.
In addition, the encapsulation adhesive 8 can also cover the substrate 1, the photosensitive material layer 4, the conductive particles 63 thereon and the solid conductive objects 62, thereby playing a better role in protecting the semiconductor device and improving the product yield.
With continued reference to fig. 11, in another embodiment, if the photosensitive material layer 4 and the conductive particles 63 thereon are not removed, the encapsulation compound 8 needs to cover the substrate 1, the photosensitive material layer 4 and the conductive particles 63 thereon, and the solid conductive object 62.
It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A method of packaging a chip, comprising:
providing at least one chip, wherein a plurality of welding pins are arranged above the chip;
providing a substrate, wherein a plurality of bonding pads and chips are arranged above the substrate, each welding leg corresponds to each bonding pad, and a conductive area is formed;
forming a photosensitive material layer above the substrate, wherein the height of the photosensitive material layer is higher than that of the soldering leg, and forming a through hole at a position of the photosensitive material layer corresponding to each conductive region respectively;
and filling the through holes with fluid conductors, and solidifying the fluid conductors to form solid conductors so that the solid conductors are bonded with the conductive areas.
2. The method of claim 1, wherein forming vias in the photosensitive material layer at locations corresponding to each of the conductive regions comprises:
coating a photosensitive material layer over the substrate;
placing a mask plate above the substrate, wherein the mask plate is provided with a plurality of light leakage areas, and the light leakage areas respectively correspond to the conductive areas;
and placing ultraviolet light above the mask plate, irradiating the photosensitive material layer corresponding to the light leakage area through the ultraviolet light, and forming a patterned photosensitive material layer through exposure and development.
3. The method of claim 1, wherein filling each of the through holes with a fluid conductor comprises:
and placing the fluid conductor into the through hole through a spin coater.
4. The chip packaging method according to claim 1, wherein the fluid conductor is a first fluid conductor or a second fluid conductor;
the first fluid conductor is a mixture of a conductive material, a volatile solvent and an adhesive;
the second fluid conductor is a mixture of a conductive material and a volatile solvent.
5. The method of claim 4, wherein the fluidic conductor is a first fluidic conductor, and wherein curing the fluidic conductor to form a solid conductor comprises:
heating the first fluid conductor to enable conductive materials and adhesives to remain in the through holes;
and irradiating the through holes with ultraviolet light to cure the adhesive, wherein the cured adhesive and the conductive material form the solid conductive object.
6. The method of claim 4, wherein the fluidic conductor is a second fluidic conductor, and wherein curing the fluidic conductor to form a solid conductor comprises:
heating the second fluid conductor to leave a conductive material remaining in the through hole;
and irradiating the through hole by laser to enable the conductive material to form the solid conductive object.
7. The chip packaging method according to claim 5 or 6, characterized by comprising, after the solid conductive object is bonded to the conductive region:
removing the photosensitive material layer and the conductive particles remained above the photosensitive material layer, and filling packaging glue above the substrate; or filling packaging glue above the photosensitive material layer and covering the solid conductive object.
8. A chip package structure, comprising:
the chip is provided with a plurality of welding pins above;
the substrate is provided with a plurality of bonding pads and the chips above, and each bonding pad corresponds to each welding leg; and
and each solid conductive object is attached to the side surface of the chip and the upper part of the substrate at intervals, one end of each solid conductive object is bonded with the bonding pad, and the other end of each solid conductive object is bonded with the corresponding welding leg of the bonding pad.
9. The chip packaging structure according to claim 8, further comprising a photosensitive material layer, wherein the photosensitive material layer is provided with a plurality of through holes, and wherein the plurality of through holes respectively accommodate the plurality of solid conductors.
10. The chip packaging structure according to claim 8 or 9, further comprising a packaging paste covering a plurality of the solid conductors.
CN202211106194.4A 2022-09-09 2022-09-09 Chip packaging method and chip packaging structure Pending CN116072557A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211106194.4A CN116072557A (en) 2022-09-09 2022-09-09 Chip packaging method and chip packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211106194.4A CN116072557A (en) 2022-09-09 2022-09-09 Chip packaging method and chip packaging structure

Publications (1)

Publication Number Publication Date
CN116072557A true CN116072557A (en) 2023-05-05

Family

ID=86168846

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211106194.4A Pending CN116072557A (en) 2022-09-09 2022-09-09 Chip packaging method and chip packaging structure

Country Status (1)

Country Link
CN (1) CN116072557A (en)

Similar Documents

Publication Publication Date Title
KR101022942B1 (en) A printed circuit board having a flow preventing dam and a manufacturing method of the same
KR101017508B1 (en) Method for advanced solder bumping and system manufactured by said method
JP6534948B2 (en) Method of manufacturing semiconductor device, method of manufacturing flip chip type semiconductor device, semiconductor device and flip chip type semiconductor device
US9287191B2 (en) Semiconductor device package and method
TW434848B (en) Semiconductor chip device and the packaging method
TWI728914B (en) Heat dissipation embedded packaging method
JPS59171130A (en) Method of producing polymer circuit board
KR20090080623A (en) Post bump and forming method of the same
JP2000058709A (en) Structure and formation of lump electrode
CN104064483B (en) Semiconductor device and its manufacture method
CN116072557A (en) Chip packaging method and chip packaging structure
TWI245597B (en) Printed circuit boards and method for fabricating the same
EP1232677A2 (en) Flip chip package, circuit board thereof and packaging method thereof
JP4416776B2 (en) Package substrate, semiconductor package, and semiconductor package manufacturing method
JPH11260954A (en) Semiconductor device and manufacture thereof
CN113594122B (en) Overflow type bump packaging structure and preparation method thereof
JP2005032820A (en) Method for manufacturing semiconductor device, and semiconductor device
TW591782B (en) Formation method for conductive bump
KR101069980B1 (en) Method for forming solder bump
TWI796089B (en) Package structure and manufacturing method thereof
JP2928755B2 (en) Electronic component manufacturing method
TW466648B (en) Method for preventing oxidation of aluminum pad in bumping process
JP4314760B2 (en) Photosensitive flux, solder joint using the same, flip chip, semiconductor package, printed wiring board, and method for manufacturing semiconductor device
KR100891530B1 (en) Semiconductor pacakge and method of manufacturing thereof
US10840161B2 (en) Method for manufacturing semiconductor package substrate

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination