CN116072165A - Signal sampling circuit and memory - Google Patents

Signal sampling circuit and memory Download PDF

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Publication number
CN116072165A
CN116072165A CN202310210367.5A CN202310210367A CN116072165A CN 116072165 A CN116072165 A CN 116072165A CN 202310210367 A CN202310210367 A CN 202310210367A CN 116072165 A CN116072165 A CN 116072165A
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signal
amplifier
clock
module
sampling
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CN202310210367.5A
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CN116072165B (en
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马鹏
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Changxin Storage Technology Xi'an Co ltd
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Changxin Memory Technologies Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay

Abstract

The embodiment of the disclosure provides a signal sampling circuit and a memory, wherein the signal sampling circuit receives a data signal and a gating clock signal from the outside, amplifies and delays the data signal to output an intermediate data signal, performs frequency division and delay processing on the gating clock signal to output a plurality of sampling clock signals, and finally performs sampling processing on the intermediate data signal by using the plurality of sampling clock signals through a sampling module to output a plurality of target data signals.

Description

Signal sampling circuit and memory
Technical Field
The present disclosure relates to the field of semiconductor memories, and in particular, to a signal sampling circuit and a memory.
Background
In order to transmit and receive data between the semiconductor chips at high speed, the strobe clock signal DQS is used to correctly identify the data signal DQ. Therefore, when the data signal DQ is received between the semiconductor chips, the strobe clock signal DQ needs to be synchronously received, and then the data signal DQ is sampled according to the strobe clock signal DQs to learn various instructions. However, due to the difference in transmission paths, there may be a delay (tDQS 2 DQ) between the strobe clock signal DQS and the data signal DQ, affecting data correctness.
Disclosure of Invention
The present disclosure provides a signal sampling circuit and a memory.
The technical scheme of the present disclosure is realized as follows:
in a first aspect, embodiments of the present disclosure provide a signal sampling circuit, the signal sampling circuit comprising:
an interface group configured to receive a data signal and a strobe clock signal from the outside;
the cascade amplification module is connected with the interface group and is configured to amplify and delay the data signals to generate and output intermediate data signals;
the clock processing module is connected with the interface group and is configured to carry out frequency division and time delay processing on the gating clock signal, and a plurality of sampling clock signals are generated and output;
and the sampling module is connected with the cascade amplification module and the clock processing module and is configured to sample the intermediate data signals by using a plurality of sampling clock signals and output a plurality of target data signals.
In some embodiments, the cascade amplification module comprises M cascade amplification units; the input end of the 1 st stage amplifying unit receives the data signal, the input end of the (i+1) th stage amplifying unit is connected with the output end of the (i) th stage amplifying unit, and the output end of the (M) th stage amplifying unit outputs the intermediate data signal; wherein i and M are both positive integers, and i is less than M.
In some embodiments, the number of sampling clock signals, the intermediate data signals, and the target data signals are all N; the phases of the N sampling clock signals are different from each other, and the clock periods of the N sampling clock signals are the same; the level states of the N intermediate data signals are the same; the sampling module comprises N sampling units; the jth sampling unit is configured to receive the jth sampling clock signal and the jth intermediate data signal, sample the jth intermediate data signal by using the jth sampling clock signal, and output the jth target data signal; wherein j and N are positive integers, and j is less than or equal to N.
In some embodiments, each stage of the amplifying unit comprises at least 1 amplifier; the number of the amplifiers of the amplifying units in the (i+1) th stage is not smaller than that of the amplifiers of the amplifying units in the (i) th stage.
In some embodiments, in the case of n=4, m=3, the total number of amplifiers is 7; the 1 st amplifier forms the 1 st stage of the amplifying unit, the 2 nd amplifier and the 3 rd amplifier are connected in parallel to form the 2 nd stage of the amplifying unit, and the 4 th amplifier, the 5 th amplifier, the 6 th amplifier and the 7 th amplifier are connected in parallel to form the 3 rd stage of the amplifying unit.
In some embodiments, the first input of the 1 st said amplifier receives said data signal, and the second input of the 1 st said amplifier receives a preset reference signal; the first input end of the 2 nd amplifier and the first input end of the 3 rd amplifier are connected with the first output end of the 1 st amplifier, and the second input end of the 2 nd amplifier and the second input end of the 3 rd amplifier are connected with the second output end of the 1 st amplifier; the first input end of the 4 th amplifier and the first input end of the 5 th amplifier are connected with the first output end of the 2 nd amplifier, and the second input end of the 4 th amplifier and the second input end of the 5 th amplifier are connected with the second output end of the 2 nd amplifier; the first input end of the 6 th amplifier, the first input end of the 7 th amplifier are connected with the first output end of the 3 rd amplifier, the second input end of the 6 th amplifier and the second input end of the 7 th amplifier are connected with the second output end of the 3 rd amplifier; the first output end and/or the second output end of the 4 th amplifier are used for outputting the 1 st intermediate data signal, the first output end and/or the second output end of the 5 th amplifier are used for outputting the 2 nd intermediate data signal, the first output end and/or the second output end of the 6 th amplifier are used for outputting the 3 rd intermediate data signal, and the first output end and/or the second output end of the 7 th amplifier are used for outputting the 4 th intermediate data signal.
In some embodiments, the signal sampling circuit further comprises a parameter module; the parameter module is configured to receive an offset detection signal and generate a first adjustment code based on the offset detection signal; wherein the offset detection signal indicates a timing offset between the sampling clock signal and the intermediate data signal; the cascade amplifying module is further configured to receive the first adjusting code and control the working state of the amplifying unit of each stage based on the first adjusting code; wherein the working state comprises an opening state and a closing state; if the amplifying unit is in an on state, the amplifying unit amplifies and delays an input signal to generate an output signal; if the amplifying unit is in a closed state, the amplifying unit directly transmits the input signal to generate an output signal.
In some embodiments, the signal sampling circuit further comprises a parameter module; the parameter module is configured to receive an offset detection signal and generate a second adjustment code based on the offset detection signal; wherein the second adjustment code indicates a timing offset between the sampling clock signal and the intermediate data signal; the cascade amplification module is further configured to receive the second adjustment code, and control delay parameters of the amplification units of each stage based on the second adjustment code; the amplifying unit amplifies and delays an input signal based on the second adjustment code to generate an output signal, and the delay time between the input signal and the output signal is controlled by the second adjustment code.
In some embodiments, the amplifier comprises a first resistor, a second resistor, a first switching tube, a second switching tube, a third switching tube, a fourth switching tube; the control end of the first switching tube forms a first input end of the amplifier, and the control end of the second switching tube forms a second input end of the amplifier; the first end of the first switching tube forms a first output end of the amplifier, and the first end of the second switching tube forms a second output end of the amplifier; the first end of the first resistor receives a first power supply signal, the second end of the first resistor is connected with the first end of the first switching tube, the second end of the first switching tube is connected with the first end of the third switching tube, and the second end of the third switching tube is connected with the grounding end; the first end of the second resistor receives a second power signal, the second end of the second resistor is connected with the first end of the second switching tube, the second end of the second switching tube is connected with the first end of the fourth switching tube, and the second end of the fourth switching tube is connected with the grounding end.
In some embodiments, the amplifier further comprises a third resistor and capacitor; the first end of the third resistor is connected with the second end of the first switching tube, and the second end of the third resistor is connected with the second end of the second switching tube; the first end of the capacitor is connected with the second end of the first switch tube, and the second end of the capacitor is connected with the second end of the second switch tube.
In some embodiments, the control terminal of the third switching tube receives a first clock control signal, and the control terminal of the fourth switching tube receives a second clock control signal.
In some embodiments, the set of interfaces includes a data interface, a first clock Zhong Jiekou, and a second clock interface; the data interface is configured to receive the data signal from the outside; the first clock Zhong Jiekou configured to receive a first strobe clock signal from the outside; the second clock interface is configured to receive a second gating clock signal from outside; the first gating clock signal and the second gating clock signal have the same clock period, the phases of the first gating clock signal and the second gating clock signal are opposite, and the first gating clock signal and the second gating clock signal form the gating clock signal.
In some embodiments, the clock processing module includes a comparator, a frequency dividing module, and a clock tree module; the comparator is configured to receive the first gating clock signal and the second gating clock signal and output a first clock signal; wherein a portion of the rising edge of the first clock signal is aligned with the rising edge of the first strobe clock signal and another portion of the rising edge of the first clock signal is aligned with the rising edge of the second strobe clock signal; the frequency dividing module is connected with the comparator and is configured to receive the first clock signal, perform frequency dividing processing on the first clock signal and output N second clock signals; the clock tree module is connected with the frequency division module and is configured to receive N second clock signals, delay and transmit the N second clock signals and output N sampling clock signals.
In some embodiments, the signal sampling circuit further comprises a replica analog module and a detection module; the replication simulation module is configured to receive the second clock signal, perform simulation delay processing on the second clock signal and generate a simulation delay signal; the detection module is connected with the replication simulation module and is configured to detect phase deviation of the simulation delay signal and the second clock signal and generate the deviation detection signal; the replication simulation module has the same structure as the clock tree module, the delay parameter of the replication simulation module is the same as the delay parameter of the clock tree module, and the simulation delay signal is used for simulating the waveform of the sampling clock signal.
In some embodiments, the jth of the sampling units includes a jth sampler; the input end of the jth sampler receives the jth intermediate data signal, the clock end of the jth sampler receives the jth sampling clock signal, and the output end of the jth sampler outputs the jth target data signal; alternatively, the jth sampling unit includes a jth adder and a jth sampler; a first input end of a j-th adder receives a j-th intermediate data signal, and a second input end of the j-th adder is connected with an output end of at least one sampler; the input end of the jth sampler is connected with the output end of the jth adder, the clock end of the jth sampler receives the jth sampling clock signal, and the output end of the jth sampler outputs the jth target data signal; the adder is used for reducing the influence of the first A intermediate data signals on the voltage value of the current intermediate data signals; a is a positive integer.
In a second aspect, embodiments of the present disclosure provide a memory comprising a signal sampling circuit as described in the first aspect.
The embodiment of the disclosure provides a signal sampling circuit and a memory, which not only can reduce time sequence offset between a data signal and a gating clock signal and improve sampling accuracy, but also can improve the strength of the data signal and improve signal transmission performance under high frequency.
Drawings
Fig. 1 is a schematic diagram of a signal sampling circuit according to an embodiment of the disclosure;
fig. 2 is a schematic diagram of a specific structure of a signal sampling circuit according to an embodiment of the disclosure;
fig. 3 is a schematic diagram of a specific structure of a sampling module according to an embodiment of the disclosure;
fig. 4 is a schematic structural diagram of a cascade amplifying module according to an embodiment of the disclosure;
fig. 5 is a schematic diagram ii of a cascade amplification module according to an embodiment of the disclosure;
fig. 6 is a schematic structural diagram III of a cascade amplifying module according to an embodiment of the disclosure;
fig. 7 is a schematic structural diagram of a cascade amplifying module according to an embodiment of the disclosure;
FIG. 8 is a schematic diagram of an amplifier according to an embodiment of the disclosure;
Fig. 9 is a schematic diagram ii of an amplifier according to an embodiment of the disclosure;
fig. 10 is a schematic diagram of a specific structure of a cascade amplification module according to an embodiment of the disclosure;
fig. 11 is a schematic diagram III of an amplifier according to an embodiment of the disclosure;
fig. 12 is a schematic diagram of an amplifier according to an embodiment of the disclosure;
fig. 13 is a schematic diagram of an amplifier according to an embodiment of the disclosure;
fig. 14 is a schematic diagram of a partial structure of a signal sampling circuit according to an embodiment of the disclosure;
fig. 15 is a schematic structural diagram of a memory according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the application and not limiting of the application. It should be noted that, for convenience of description, only a portion related to the related application is shown in the drawings. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure. In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict. It should be noted that the term "first/second/third" in relation to the embodiments of the present disclosure is merely used to distinguish similar objects and does not represent a particular ordering for the objects, it being understood that the "first/second/third" may be interchanged with a particular order or sequencing, if allowed, to enable the embodiments of the present disclosure described herein to be implemented in an order other than illustrated or described.
The following is a description of terms and relationships related to embodiments of the present disclosure:
dynamic random access memory (Dynamic Random Access Memory, DRAM);
a synchronous dynamic random access memory (Synchronous Dynamic Random Access Memory, SDRAM);
double Data Rate memory (DDR);
fourth generation DDR (4 th DDR, DDR 4);
fifth generation DDR (5 th DDR, DDR 5);
low Power DDR (LPDDR).
Currently, after a memory (for example, a DRAM) receives a strobe clock signal DQS and a data signal DQ, the strobe clock signal DQS needs to be adjusted through a clock tree (or referred to as DQS tree) to expect that the delay, the phase, the clock period, etc. of the adjusted strobe clock signal DQS meet the requirements, and at the same time, the adjusted strobe clock signal DQS and the data signal DQ need to be in an aligned state. However, since the strobe clock signal DQS needs to be processed by a clock tree, the delay of the strobe clock signal DQS is often greater than the data signal DQ, and the deviation (tDQS 2 DQ) between the two is easily beyond the specification of the industry standard document (SPEC), so that sampling errors occur, and the performance of the memory is degraded.
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
In one embodiment of the present disclosure, referring to fig. 1, a schematic diagram of a signal sampling circuit 10 provided in an embodiment of the present disclosure is shown. As shown in fig. 1, the signal sampling circuit 10 includes:
an interface group 11 configured to receive a data signal DQ and a strobe clock signal DQs from the outside;
a cascade amplification module 12 connected to the interface group 11 and configured to amplify and delay the data signal DQ to generate and output an intermediate data signal;
a clock processing module 13, connected to the interface group 11, configured to divide and delay the strobe clock signal DQS, and generate and output a plurality of sampling clock signals (e.g., clk_ I, CLK _ Q, CLK _ib, clk_qb in fig. 1);
the sampling module 14 is connected to the cascade amplifying module 12 and the clock processing module 13, and is configured to sample the intermediate data signal with a plurality of sampling clock signals, and output a plurality of target data signals (for example, out_ I, out _ Q, out _ib and out_qb in fig. 1).
The signal sampling circuit 10 may be applied to a memory, for example, DRAM, SDRAM, DDR, LPDDR, and will be described below by taking a DRAM as an example.
Here, the clock processing module 13 includes, but is not limited to, the aforementioned clock tree. In this way, after receiving the strobe clock signal DQS and the data signal DQ, the clock processing module 13 not only adjusts the strobe clock signal DQS, but also adjusts the data signal DQ through the cascade amplification module 12, so as to reduce the delay (tDQS 2 DQ) between the intermediate data signal and the sampling clock signal, better conform to the specification of the industry standard document (SPEC), and improve the sampling accuracy; in addition, the cascade amplification module 12 can also increase the signal strength and improve the signal transmission performance at high frequencies.
In some embodiments, as shown in FIG. 2, the cascode amplification module 12 includes M cascaded amplification units; the input end of the 1 st stage amplifying unit receives the data signal DQ, the input end of the i+1 th stage amplifying unit is connected with the output end of the i stage amplifying unit, and the output end of the M stage amplifying unit outputs an intermediate data signal.
It should be noted that, M is a positive integer, and i is a positive integer smaller than M depending on the application scenario. In addition, the amplifying unit may be implemented by a variable gain amplifier (Variable Gain Amplifier, VGA). It should be understood that the variable gain amplifier may be of various types, and any of the amplification units may be constructed.
In some embodiments, referring to fig. 2, the number of sampling clock signals, intermediate data signals, and target data signals is N. Here, N is a positive integer, and fig. 2 illustrates n=4 as an example.
Here, the level states of the N intermediate data signals are the same, the clock periods of the N sampling clock signals are the same, and the phases of the N sampling clock signals are different from each other. Taking fig. 2 as an example, the phases of two adjacent sampling clock signals are 90 degrees apart within the error tolerance range, that is, clk_q is delayed by 90 degrees from clk_i, clk_ib is delayed by 180 degrees from clk_i, and clk_qb is delayed by 270 degrees from clk_i with reference to clk_i.
As shown in fig. 2, the sampling module 14 includes N sampling units; a j-th sampling unit configured to receive the j-th sampling clock signal and the j-th intermediate data signal, sample the j-th intermediate data signal using the j-th sampling clock signal, and output a j-th target data signal; wherein j is a positive integer, and j is less than or equal to N.
In this way, sampling clock signals of different phases can sample the intermediate data signal at different times to obtain corresponding information.
In a specific embodiment, the sampling module 14 includes N samplers, i.e., the jth sampling unit includes the jth sampler; the input end of the jth sampler receives the jth intermediate data signal, the clock end of the jth sampler receives the jth sampling clock signal, and the output end of the jth sampler outputs the jth target data signal.
In another specific embodiment, as shown in fig. 2 or 3, the sampling module 14 includes N adders and N samplers (fig. 3 is also shown with n=4 as an example), that is, the jth sampling unit includes a jth adder and a jth sampler; a first input end of the j-th adder receives the j-th intermediate data signal, and a second input end of the j-th adder is connected with an output end of at least one sampler as shown in fig. 3; the input end of the jth sampler is connected with the output end of the jth adder, the clock end of the jth sampler receives the jth sampling clock signal, and the output end of the jth sampler outputs the jth target data signal.
In particular, in fig. 2, the input of the adder is also connected to the output of at least one sampler, but omitted.
It should be noted that, the adder mainly realizes the decision feedback balance function. It should be understood that each data interface receives a plurality of data signals DQ transmitted in serial, the level state of the data signal with the preceding timing will affect the level state of the data signal with the following timing, and the adder can eliminate the effect as much as possible, so as to avoid the error of the decision result of the data signal DQ; that is, the adder serves to reduce the influence of the first a intermediate data signals on the voltage value of the current intermediate data signal. Here, a=4 is shown in fig. 3.
In addition, the sampler may be implemented by a D-type flip-flop.
It should be noted that each stage of amplifying unit includes at least 1 amplifier, and the number of amplifiers of the i+1th stage of amplifying unit is not smaller than the number of amplifiers of the i th stage of amplifying unit.
In the amplifying unit of the same stage, different amplifiers are connected in parallel. The number of amplifiers in the preceding stage amplifying unit is not smaller than the number of amplifiers in the following stage amplifying unit, so that the output signal of each amplifier serves as at least the input signal of one of the following stage amplifiers.
It should be noted that, the input signals of all the amplifiers belonging to the same stage are in the same level state, and the output signals of all the amplifiers belonging to the same stage are in the same level state.
Assuming m=3, n=4, several examples of cascade amplification modules are given below:
example 1: as shown in fig. 4, the 1 st stage amplifying unit includes 1 amplifier, the 2 nd stage amplifying unit includes 2 amplifiers, and the 3 rd stage amplifying unit includes 4 amplifiers;
example 2: as shown in fig. 5, the 1 st stage amplifying unit includes 1 amplifier, the 2 nd stage amplifying unit includes 4 amplifiers, and the 3 rd stage amplifying unit includes 4 amplifiers;
Example 3: as shown in fig. 6, the 1 st stage amplifying unit includes 2 amplifiers, the 2 nd stage amplifying unit includes 2 amplifiers, and the 3 rd stage amplifying unit includes 4 amplifiers;
example 4: as shown in fig. 7, the 1 st stage amplifying unit includes 2 amplifiers, the 2 nd stage amplifying unit includes 3 amplifiers, and the 3 rd stage amplifying unit includes 4 amplifiers;
……
the present disclosure will be described in detail below with reference to the case shown in fig. 4, and other cases will be understood accordingly.
As shown in fig. 4, the total number of amplifiers is 7; the 1 st amplifier forms a 1 st stage amplifying unit, the 2 nd amplifier and the 3 rd amplifier are connected in parallel to form a 2 nd stage amplifying unit, and the 4 th amplifier, the 5 th amplifier, the 6 th amplifier and the 7 th amplifier are connected in parallel to form a 3 rd stage amplifying unit.
In a specific embodiment, each amplifier has 2 inputs and 2 outputs. That is, each amplifier needs to receive a pair of signals and output a pair of signals.
In one case, a pair of signals received by an amplifier in the 1 st stage amplifying unit is constituted by a data signal (logic potential of 0 or 1) and a preset reference signal (logic potential of 0.5) together.
In another case, after receiving the data signal, an inverted signal of the data signal is obtained through an inverter, and the data signal and the inverted signal thereof together constitute a pair of signals received by an amplifier in the 1 st stage amplifying unit. Correspondingly, a pair of signals output by the amplifier in the amplifying unit of the last stage are converted into single-ended intermediate data signals through the comparator.
Taking a pair of signals formed by the data signal and the preset reference signal as an example, a first input end of the 1 st amplifier receives the data signal, and a second input end of the 1 st amplifier receives the preset reference signal; the first input end of the 2 nd amplifier and the first input end of the 3 rd amplifier are connected with the first output end of the 1 st amplifier, and the second input end of the 2 nd amplifier and the second input end of the 3 rd amplifier are connected with the second output end of the 1 st amplifier; the first input end of the 4 th amplifier and the first input end of the 5 th amplifier are connected with the first output end of the 2 nd amplifier, and the second input end of the 4 th amplifier and the second input end of the 5 th amplifier are connected with the second output end of the 2 nd amplifier; the first input end of the 6 th amplifier and the first input end of the 7 th amplifier are connected with the first output end of the 3 rd amplifier, and the second input end of the 6 th amplifier and the second input end of the 7 th amplifier are connected with the second output end of the 3 rd amplifier.
Referring to fig. 4, for the output of the cascade amplification module, there may be the following cases depending on the type of amplifier used:
(1) The amplifier may be analogous to a buffer, in particular, the first output of the amplifier is the same as the logic potential of the first input (the particular voltage value may be different), and the second output is the same as the logic potential of the second input (the particular voltage value may be different); at this time, the first output terminal of the 4 th amplifier outputs the 1 st intermediate data signal, the first output terminal of the 5 th amplifier outputs the 2 nd intermediate data signal, the first output terminal of the 6 th amplifier outputs the 3 rd intermediate data signal, and the first output terminal of the 7 th amplifier outputs the 4 th intermediate data signal; or, the first output end and the second output end of the 4 th amplifier form a 1 st intermediate data signal after passing through the comparator, the first output end is connected to the positive phase end of the comparator, the second output end is connected to the negative phase end of the comparator, and the 5 th to 7 th amplifiers are similarly processed.
(2) The amplifier may be analogous to an inverter, in particular, the first output of the amplifier is opposite to the logic potential of the first input (or the first output of the amplifier is the same as the logic potential of the second input, the particular voltage value may be different), and the second output of the amplifier is opposite to the logic potential of the second input (or the second output of the amplifier is the same as the logic potential of the first input, the particular voltage value may be different); at this time, the second output terminal of the 4 th amplifier outputs the 1 st intermediate data signal, the second output terminal of the 5 th amplifier outputs the 2 nd intermediate data signal, the second output terminal of the 6 th amplifier outputs the 3 rd intermediate data signal, and the second output terminal of the 7 th amplifier outputs the 4 th intermediate data signal; or, the first output end and the second output end of the 4 th amplifier form a 1 st intermediate data signal after passing through the comparator, the second output end is connected to the positive phase end of the comparator, the first output end is connected to the negative phase end of the comparator, and the 5 th to 7 th amplifiers are similarly processed.
It should also be noted that in the cascade amplification module, the structure of each amplifier is similar.
In one example, as shown in fig. 8, the amplifier includes a first resistor 35, a second resistor 36, a first switching tube 31, a second switching tube 32, a third switching tube 33, and a fourth switching tube 34; wherein:
the control end of the first switching tube 31 forms a first input end of the amplifier, and the control end of the second switching tube 32 forms a second input end of the amplifier; the first end of the first switching tube 31 forms a first output end of the amplifier, and the first end of the second switching tube 32 forms a second output end of the amplifier; the first end of the first resistor 35 receives the first power signal, the second end of the first resistor 35 is connected with the first end of the first switching tube 31, the second end of the first switching tube 31 is connected with the first end of the third switching tube 33, and the second end of the third switching tube 33 is connected with the grounding end; the first end of the second resistor 36 receives the second power signal, the second end of the second resistor 36 is connected to the first end of the second switching tube 32, the second end of the second switching tube 32 is connected to the first end of the fourth switching tube 34, and the second end of the fourth switching tube 34 is connected to the ground.
In another example, as shown in fig. 9, the amplifier further includes a third resistor 38 and a capacitor 37; the first end of the third resistor 38 is connected with the second end of the first switching tube 31, and the second end of the third resistor 38 is connected with the second end of the second switching tube 32; a first end of the capacitor 37 is connected to the second end of the first switching tube 31 and a second end of the capacitor 37 is connected to the second end of the second switching tube 32.
It should be noted that, the control end of the third switching tube 33 receives the first clock control signal, the control end of the fourth switching tube 34 receives the second clock control signal, and the resistance values of the first resistor 35, the second resistor 36 and the third resistor 38 are fixed. Here, when the amplifier performs signal amplification processing, the first clock control signal controls the third switching transistor 33 to be turned on, and the second clock control signal controls the fourth switching transistor 34 to be turned on.
Based on the architecture of the amplifier shown in fig. 4 and the internal structure of the amplifier shown in fig. 9, please refer to fig. 10, which schematically illustrates a detailed structure of a cascade amplification module.
It should be noted that, because the process errors of the different memories are different, the timing offset (tDQS 2 DQ) generated by the data signal and the clock signal in the transmission process in the different memories is different, so the delay time generated by the cascade amplification module 12 may be set to be adjustable, so that the delay time is set according to the actual test result of each memory, and the timing offset problem is further improved.
In a first possible implementation, the delay time generated by each amplifying unit is fixed, and the cascade amplifying module 12 may adjust the number of turn-on stages of the amplifying units in each transmission link, thereby adjusting the delay time of the data signal DQ.
Correspondingly, the signal sampling circuit 10 further comprises a parameter module; a parameter module configured to receive the offset detection signal, generate a first adjustment code based on the offset detection signal; wherein the offset detection signal indicates a timing offset (tDQS 2 DQ) between the sampling clock signal and the intermediate data signal;
the cascade amplification module 12 is further configured to receive a first adjustment code, and control the working state of each stage of amplification unit based on the first adjustment code; the working state comprises an opening state and a closing state; if the amplifying unit is in an on state, the amplifying unit amplifies and delays the input signal to generate an output signal; if the amplifying unit is in the off state, the amplifying unit directly transmits the input signal to generate an output signal.
Taking the cascade amplification module 12 shown in fig. 4 to 7 as an example, each stage of amplification unit will generate a delay of 0.2 nanoseconds (ns) when in the on state, and the data signal DQ needs a delay of 0.4ns in total through testing, the 1 st stage amplification unit and the 2 nd stage amplification unit can be turned on, and the 3 rd stage amplification unit can be turned off. In particular, when the amplifying unit is turned off, the amplifying unit is not in an off state, and still performs a signal transmission function, but the delay between the input signal and the output signal is extremely small (negligible).
In a second possible implementation, the delay time generated by each amplifying unit is a variable range, and the cascade amplifying module 12 can adjust the delay parameter of each amplifying unit, so as to adjust the overall delay time of the data signal. Of course, the delay times of amplifying units belonging to the same stage must be uniform.
Correspondingly, the signal sampling circuit 10 further comprises a parameter module; a parameter module configured to receive the offset detection signal, generate a second adjustment code based on the offset detection signal; wherein the second adjust code indicates a timing offset (tDQS 2 DQ) between the sample clock signal and the intermediate data signal;
the cascade amplification module 12 is further configured to receive a second adjustment code, and control the delay parameter of each stage of amplification unit based on the second adjustment code; the amplifying unit amplifies and delays the input signal based on the second adjustment code to generate an output signal, and the delay time between the input signal and the output signal is controlled by the second adjustment code.
For example, taking the cascade amplification module 12 shown in fig. 4 to 7 as an example, each stage of amplifying unit can generate a delay of 0.1ns to 0.3ns, and according to the test, the delay of the data signal needs 0.4ns in total, the delay of the stage 1 amplifying unit can be controlled to be 0.2ns, the delay of the stage 2 amplifying unit is controlled to be 0.1ns, and the delay of the stage 3 amplifying unit is controlled to be 0.1ns.
With the mechanism of "delay parameters of the cascade amplification module 12 are configured to be adjusted by the first adjustment code", the following control principles of 2 kinds of amplifiers are provided for the amplifier shown in fig. 9.
In the first embodiment, as shown in fig. 11, the third switching tube 33 and the fourth switching tube 34 are both fixedly turned on, and the resistance values of the first resistor 35, the second resistor 36 and the third resistor 38 are adjustable; the working principle is as follows: (1) In the case where the current stage amplifying unit is instructed to be in the on state, the first resistor 35 is in the maximum resistance state (R max ) The second resistor 36 is in the maximum resistance state (R max ) Thereby delaying the signal amplification process, which is equivalent to the amplification unit performing delay transmission processing on the input signal; while the third resistor 38 is in a larger resistance state to avoid premature signal equalization. (2) In the case where the current stage amplifying unit is instructed to be in the off state, the first resistor 35 is in the minimum resistance state (R min ) The second resistor 36 is in a minimum resistance state (R min ) Thereby accelerating the signal amplification process, which is equivalent to the amplification unit performing direct transmission processing on the input signal; while the third resistor 38 is in a smaller resistance state.
In the second embodiment, as shown in fig. 12, the resistance values of the first resistor 35, the second resistor 36, and the third resistor 38 are all fixed; the amplifier further comprises a fifth switching tube 37 and a sixth switching tube 38; the working principle is as follows: (1) In the case where the current stage amplifying unit is instructed to be in the on state, both the third switching tube 33 and the fourth switching tube 34 are turned on, and the fifth switching tube 37 and the sixth switching tube 38 are turned off, which corresponds to the amplifying unit performing delay transmission processing on the input signal; while the third resistor 38 is in a larger resistance state; (2) In the case where the amplifying unit is instructed to be in the off state, the third switching tube 33 and the fourth switching tube 34 are both turned off, and the fifth switching tube 37 and the sixth switching tube 38 are turned on, which corresponds to the amplifying unit performing direct transmission processing on the input signal.
The following example provides a control principle of an amplifier under a mechanism that the delay parameter of the cascade amplification module 12 is configured to be adjusted by the second adjustment code.
As shown in fig. 13, the third switching tube 33 and the fourth switching tube 34 are both fixedly turned on, the resistances of the first resistor 35 and the second resistor 36 are adjustable, and the resistances can be within a larger range (e.g., R 1 、R 2 、R 3 、R 4 … …, etc.) are controllably adjusted. At this time, according to the delay parameter indicated by the current stage amplifying unit, the resistance gear of the first resistor 35/the second resistor 36 is flexibly adjusted, so that the output signal generates a preset delay time relative to the input signal, and meanwhile, the resistance of the third resistor 38 is correspondingly adjusted. That is, in fig. 11, there are only 2 shift positions (R max /R min ) The method comprises the steps of carrying out a first treatment on the surface of the In fig. 13, each resistor has more shift positions (R 1 /R 2 /R 3 /R 4 … …) to achieve more flexible resistance control.
As can be seen from the above, in the case that the signal sampling circuit 10 includes the parameter module, the control terminal of the third switching tube receives the first adjustment sub-signal, and the control terminal of the fourth switching tube receives the second adjustment sub-signal; the first resistor 35, the second resistor 36 and the third resistor 38 are all adjustable resistors, the first resistor 35 receives the third adjustment sub-signal, the second resistor 36 receives the fourth adjustment sub-signal, and the third resistor 38 receives the fifth adjustment sub-signal; the first adjustment sub-signal, the second adjustment sub-signal, the third adjustment sub-signal, the fourth adjustment sub-signal and the fifth adjustment sub-signal are all from the first adjustment code; or the first adjustment sub-signal, the second adjustment sub-signal, the third adjustment sub-signal, the fourth adjustment sub-signal and the fifth adjustment sub-signal are all from the second adjustment code.
In some embodiments, as shown in fig. 2, the interface group 11 includes a data interface 111, a first clock Zhong Jiekou 112, and a second clock interface 113; a data interface 111 configured to receive a data signal DQ from the outside; a first clock Zhong Jiekou configured to externally receive a first strobe clock signal dqs_t; a second clock interface 113 configured to externally receive a second strobe clock signal dqs_b; the first strobe clock signal DQS_T and the second strobe clock signal DQS_B have the same clock period, phases of the first strobe clock signal DQS_T and the second strobe clock signal DQS_B are opposite, and the first strobe clock signal DQS_T and the second strobe clock signal DQS_B form the strobe clock signal DQS.
In the memory, the data signals received each time are actually a set of signals DQ0, DQ1, … … DQn, and the number of the data interface 111, the cascode amplifier module 12, and the sampling module 14 is also (n+1).
In some embodiments, as shown in fig. 2, the clock processing module 13 includes a comparator 131, a frequency dividing module 132, and a clock tree module 133;
a comparator 131 configured to receive the first strobe clock signal dqs_t and the second strobe clock signal dqs_b, compare the first strobe clock signal dqs_t and the second strobe clock signal dqs_b, and output a first clock signal; wherein a portion of the rising edge of the first clock signal is aligned with the rising edge of the first strobe clock signal DQS_T and another portion of the rising edge of the first clock signal is aligned with the rising edge of the second strobe clock signal DQS_B;
the frequency dividing module 132 is connected with the comparator 131 and is configured to receive the first clock signal, perform frequency division processing on the first clock signal and output N second clock signals;
the clock tree module 133 is connected to the frequency dividing module 132, and is configured to receive the N second clock signals, delay the N second clock signals, and output N sampling clock signals.
It should be noted that the clock tree module 133 includes a plurality of clock trees, and each clock tree delays transmission of 1 second clock signal.
In some embodiments, referring to fig. 14, the signal sampling circuit 10 further includes a replica analog module 152 and a detection module 155. Specifically, the replication analog module 152 is configured to receive the second clock signal, perform analog delay processing on the second clock signal, and generate an analog delay signal; and a detection module 155, coupled to the replica analog module, configured to perform phase deviation detection on the analog delay signal and the second clock signal, and generate an offset detection signal.
It should be noted that the replica analog module 152 has the same structure as the clock tree module 133 described above, and the delay parameter of the replica analog module 152 is the same as the delay parameter of the clock tree module 133, and the analog delay signal is used to simulate the waveform of the sampling clock signal.
Referring to fig. 14, in one possible embodiment, the signal sampling circuit 10 further includes a timer 151, a counter 153, and a latch 154. During operation of the timer 151, the timer 151 receives the clock signal CK0 from the frequency dividing module 132 and outputs it as the clock signal CK1, and the clock signal CK0 may be any one of the second clock signals; the clock signal CK2 output by the replica analog block 152 can simulate the waveform of the corresponding sampling clock signal. Here, MPC start and MPC stop are used to control the output signal of the timer 151 to start/end oscillation, and MR45 is used to enable the relevant module.
Here, since the timing offset (tDQS 2 DQ) is mainly generated due to the transmission of the clock tree to the clock signal, that is, the clock signal CK1 and the data signal DQ at the corresponding timing may be considered to be aligned, the phase difference between the clock signal CK1 and the analog delay signal CK2 may be considered to be tDQS2DQ. In addition, the counter 153 may count the number of oscillations of the clock signal per unit time, which are latched by the latch 154 and stored in the register 46 (MR 46) and the register 47 (MR 47) to determine whether the oscillation frequency of the analog delay signal CK2 is deviated.
In summary, the embodiment of the disclosure provides a signal sampling circuit, which increases the delay of the data signal DQ by using a cascaded amplifier after the receiver of the data signal DQ, so as to reduce tDQS2DQ, better meet the requirements of industry standard documents, and have larger margin for DRAM; meanwhile, through cascading the amplifiers, the load of each amplifier can be reduced, and the high-frequency gain of the signal can be improved more conveniently. Taking a cascade amplification module formed by three stages of amplifiers as an example, the amplifiers can adopt a design scheme of 1:2:4, so that the load of each stage of amplifiers is lightened, and the whole data receiving circuit has better high-frequency gain.
In yet another embodiment of the present disclosure, reference is made to fig. 15, which illustrates a schematic diagram of the composition and structure of a memory 30 provided by an embodiment of the present disclosure. As shown in fig. 15, the memory 30 includes at least the aforementioned signal sampling circuit 10.
The foregoing is merely a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. It should be noted that in this disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment. The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments. The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it should be covered in the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (16)

1. A signal sampling circuit, the signal sampling circuit comprising:
an interface group configured to receive a data signal and a strobe clock signal from the outside;
the cascade amplification module is connected with the interface group and is configured to amplify and delay the data signals to generate and output intermediate data signals;
the clock processing module is connected with the interface group and is configured to carry out frequency division and time delay processing on the gating clock signal, and a plurality of sampling clock signals are generated and output;
and the sampling module is connected with the cascade amplification module and the clock processing module and is configured to sample the intermediate data signals by using a plurality of sampling clock signals and output a plurality of target data signals.
2. The signal sampling circuit of claim 1, wherein the cascode amplification module comprises M cascaded amplification units;
the input end of the 1 st stage amplifying unit receives the data signal, the input end of the (i+1) th stage amplifying unit is connected with the output end of the (i) th stage amplifying unit, and the output end of the (M) th stage amplifying unit outputs the intermediate data signal; wherein i and M are both positive integers, and i is less than M.
3. The signal sampling circuit of claim 2, wherein the number of sampling clock signals, the intermediate data signals, and the target data signals are all N; the phases of the N sampling clock signals are different from each other, and the clock periods of the N sampling clock signals are the same; the level states of the N intermediate data signals are the same;
the sampling module comprises N sampling units; the jth sampling unit is configured to receive the jth sampling clock signal and the jth intermediate data signal, sample the jth intermediate data signal by using the jth sampling clock signal, and output the jth target data signal; wherein j and N are positive integers, and j is less than or equal to N.
4. A signal sampling circuit according to claim 3, wherein each stage of the amplifying unit comprises at least 1 amplifier; the number of the amplifiers of the amplifying units in the (i+1) th stage is not smaller than that of the amplifiers of the amplifying units in the (i) th stage.
5. The signal sampling circuit of claim 4, wherein in the case of n=4, m=3, the total number of amplifiers is 7;
the 1 st amplifier forms the 1 st stage of the amplifying unit, the 2 nd amplifier and the 3 rd amplifier are connected in parallel to form the 2 nd stage of the amplifying unit, and the 4 th amplifier, the 5 th amplifier, the 6 th amplifier and the 7 th amplifier are connected in parallel to form the 3 rd stage of the amplifying unit.
6. The signal sampling circuit of claim 5, wherein the signal sampling circuit comprises a logic circuit,
the first input end of the 1 st amplifier receives the data signal, and the second input end of the 1 st amplifier receives a preset reference signal;
the first input end of the 2 nd amplifier and the first input end of the 3 rd amplifier are connected with the first output end of the 1 st amplifier, and the second input end of the 2 nd amplifier and the second input end of the 3 rd amplifier are connected with the second output end of the 1 st amplifier;
the first input end of the 4 th amplifier and the first input end of the 5 th amplifier are connected with the first output end of the 2 nd amplifier, and the second input end of the 4 th amplifier and the second input end of the 5 th amplifier are connected with the second output end of the 2 nd amplifier; the first input end of the 6 th amplifier, the first input end of the 7 th amplifier are connected with the first output end of the 3 rd amplifier, the second input end of the 6 th amplifier and the second input end of the 7 th amplifier are connected with the second output end of the 3 rd amplifier;
the first output end and/or the second output end of the 4 th amplifier are used for outputting the 1 st intermediate data signal, the first output end and/or the second output end of the 5 th amplifier are used for outputting the 2 nd intermediate data signal, the first output end and/or the second output end of the 6 th amplifier are used for outputting the 3 rd intermediate data signal, and the first output end and/or the second output end of the 7 th amplifier are used for outputting the 4 th intermediate data signal.
7. The signal sampling circuit of claim 6, further comprising a parameter module;
the parameter module is configured to receive an offset detection signal and generate a first adjustment code based on the offset detection signal; wherein the offset detection signal indicates a timing offset between the sampling clock signal and the intermediate data signal;
the cascade amplifying module is further configured to receive the first adjusting code and control the working state of the amplifying unit of each stage based on the first adjusting code;
wherein the working state comprises an opening state and a closing state; if the amplifying unit is in an on state, the amplifying unit amplifies and delays an input signal to generate an output signal; if the amplifying unit is in a closed state, the amplifying unit directly transmits the input signal to generate an output signal.
8. The signal sampling circuit of claim 6, further comprising a parameter module;
the parameter module is configured to receive an offset detection signal and generate a second adjustment code based on the offset detection signal; wherein the second adjustment code indicates a timing offset between the sampling clock signal and the intermediate data signal;
The cascade amplification module is further configured to receive the second adjustment code, and control delay parameters of the amplification units of each stage based on the second adjustment code;
the amplifying unit amplifies and delays an input signal based on the second adjustment code to generate an output signal, and the delay time between the input signal and the output signal is controlled by the second adjustment code.
9. The signal sampling circuit according to any one of claims 4 to 8, wherein the amplifier comprises a first resistor, a second resistor, a first switching tube, a second switching tube, a third switching tube, a fourth switching tube;
the control end of the first switching tube forms a first input end of the amplifier, and the control end of the second switching tube forms a second input end of the amplifier; the first end of the first switching tube forms a first output end of the amplifier, and the first end of the second switching tube forms a second output end of the amplifier;
the first end of the first resistor receives a first power supply signal, the second end of the first resistor is connected with the first end of the first switching tube, the second end of the first switching tube is connected with the first end of the third switching tube, and the second end of the third switching tube is connected with the grounding end; the first end of the second resistor receives a second power signal, the second end of the second resistor is connected with the first end of the second switching tube, the second end of the second switching tube is connected with the first end of the fourth switching tube, and the second end of the fourth switching tube is connected with the grounding end.
10. The signal sampling circuit of claim 9, wherein the amplifier further comprises a third resistor and capacitor;
the first end of the third resistor is connected with the second end of the first switching tube, and the second end of the third resistor is connected with the second end of the second switching tube; the first end of the capacitor is connected with the second end of the first switch tube, and the second end of the capacitor is connected with the second end of the second switch tube.
11. The signal sampling circuit of claim 9, wherein the signal sampling circuit comprises a logic circuit,
the control end of the third switching tube receives a first clock control signal, and the control end of the fourth switching tube receives a second clock control signal.
12. The signal sampling circuit of claim 7 or 8, wherein the set of interfaces includes a data interface, a first clock Zhong Jiekou, and a second clock interface;
the data interface is configured to receive the data signal from the outside;
the first clock Zhong Jiekou configured to receive a first strobe clock signal from the outside;
the second clock interface is configured to receive a second gating clock signal from outside;
the first gating clock signal and the second gating clock signal have the same clock period, the phases of the first gating clock signal and the second gating clock signal are opposite, and the first gating clock signal and the second gating clock signal form the gating clock signal.
13. The signal sampling circuit of claim 12, wherein the clock processing module comprises a comparator, a frequency dividing module, and a clock tree module;
the comparator is configured to receive the first gating clock signal and the second gating clock signal and output a first clock signal; wherein a portion of the rising edge of the first clock signal is aligned with the rising edge of the first strobe clock signal and another portion of the rising edge of the first clock signal is aligned with the rising edge of the second strobe clock signal;
the frequency dividing module is connected with the comparator and is configured to receive the first clock signal, perform frequency dividing processing on the first clock signal and output N second clock signals;
the clock tree module is connected with the frequency division module and is configured to receive N second clock signals, delay and transmit the N second clock signals and output N sampling clock signals.
14. The signal sampling circuit of claim 13, further comprising a replica analog module and a detection module;
the replication simulation module is configured to receive the second clock signal, perform simulation delay processing on the second clock signal and generate a simulation delay signal;
The detection module is connected with the replication simulation module and is configured to detect phase deviation of the simulation delay signal and the second clock signal and generate the deviation detection signal;
the replication simulation module has the same structure as the clock tree module, the delay parameter of the replication simulation module is the same as the delay parameter of the clock tree module, and the simulation delay signal is used for simulating the waveform of the sampling clock signal.
15. The signal sampling circuit of claim 3, wherein the signal sampling circuit comprises,
the j-th sampling unit comprises a j-th sampler; the input end of the jth sampler receives the jth intermediate data signal, the clock end of the jth sampler receives the jth sampling clock signal, and the output end of the jth sampler outputs the jth target data signal;
alternatively, the jth sampling unit includes a jth adder and a jth sampler; a first input end of a j-th adder receives a j-th intermediate data signal, and a second input end of the j-th adder is connected with an output end of at least one sampler; the input end of the jth sampler is connected with the output end of the jth adder, the clock end of the jth sampler receives the jth sampling clock signal, and the output end of the jth sampler outputs the jth target data signal; the adder is used for reducing the influence of the first A intermediate data signals on the voltage value of the current intermediate data signals; a is a positive integer.
16. A memory comprising the signal sampling circuit of any one of claims 1-15.
CN202310210367.5A 2023-03-07 2023-03-07 Signal sampling circuit and memory Active CN116072165B (en)

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