CN116070584B - Circuit simulation method, circuit simulation device, electronic equipment and computer readable storage medium - Google Patents
Circuit simulation method, circuit simulation device, electronic equipment and computer readable storage medium Download PDFInfo
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Abstract
The application provides a circuit simulation method, a circuit simulation device, electronic equipment and a computer readable storage medium, wherein the circuit simulation method comprises the following steps: dividing the netlist circuit into a plurality of sub-circuits according to hypergraph division rules and initial information of the netlist circuit; modeling a plurality of the sub-circuits in parallel to obtain a BBD matrix; obtaining a comprehensive calculation result of the netlist circuit by solving the block diagonal matrix of the BBD matrix in parallel so as to complete the netlist circuit simulation; wherein, the BBD matrix is a single-layer BBD structure. According to the method, the netlist circuit is divided into the plurality of sub-circuits, so that the plurality of sub-circuits are analyzed and solved in parallel, and finally, the calculation results of the sub-circuits are integrated to obtain the final simulation result, so that the overall calculation time of the netlist circuit is saved, and the circuit simulation efficiency is improved.
Description
Technical Field
The present application relates to the field of automation, and in particular, to a circuit simulation method, apparatus, electronic device, and computer readable storage medium.
Background
In the circuit design stage of VLSI (VERY LARGE SCALE Integration Circuit, chinese name: very large scale integrated circuit), the designed circuit needs to be simulated using EDA (Electronic Design Automation, chinese name: electronic design automation) tools to verify the circuit function and to be able to further optimize the design. Along with the improvement of the process, the scale of the integrated circuit is larger, the simulation time of the integrated circuit is longer, and the simulation speed is slow.
Disclosure of Invention
Accordingly, an object of an embodiment of the present application is to provide a circuit simulation method, apparatus, electronic device, and computer readable storage medium, which can accelerate the circuit simulation.
In a first aspect, an embodiment of the present application provides a circuit simulation method, including: dividing the netlist circuit into a plurality of sub-circuits according to hypergraph division rules and initial information of the netlist circuit; modeling a plurality of the sub-circuits in parallel to obtain a BBD matrix; obtaining a comprehensive calculation result of the netlist circuit by solving the block diagonal matrix of the BBD matrix in parallel so as to complete the netlist circuit simulation; wherein, the BBD matrix is a single-layer BBD structure.
In the implementation process, the netlist circuit is divided into a plurality of sub-circuits, and the plurality of sub-circuits are analyzed and solved in parallel, so that the plurality of sub-circuits are analyzed and processed at the same time, the time for overall analysis and processing of the netlist circuit is shortened, and the circuit simulation speed is improved. In addition, the BBD matrix is set to be a single layer, so that the difficulty of BBD matrix calculation is simplified, and the calculation difficulty of circuit simulation is simplified.
In one embodiment, the solving the block diagonal matrix of the BBD matrix in parallel to obtain the synthesized calculation result of the netlist circuit, so as to complete the netlist circuit simulation, includes: processing the BBD matrix by a block Gaussian elimination method to obtain a processed BBD matrix; carrying out parallel solving on a first target block diagonal matrix of the processed BBD matrix to obtain a subcircuit calculation result; solving a linear equation of a diagonal matrix of a second target block of the processed BBD matrix to obtain a root circuit calculation result; determining the comprehensive calculation result according to the sub-circuit calculation result and the root circuit calculation result to complete the netlist circuit simulation; wherein the first target block diagonal matrix and the second target block diagonal matrix are each part of the BBD matrix.
In the implementation process, different characteristics of the block diagonal matrix in different areas of the BBD matrix are calculated according to the characteristics of different block diagonal matrices in the BBD matrix, corresponding calculation modes can be matched according to the characteristics of different block diagonal matrices, calculation of the BBD matrix is simplified, and calculation efficiency is improved.
In one embodiment, the performing parallel solution on the first target block diagonal matrix of the processed BBD matrix to obtain a sub-circuit calculation result includes: and carrying out parallel pre-solving on the diagonal matrix of the first target block by a sparse matrix direct method to obtain a subcircuit calculation result.
In the implementation process, the sparse matrix direct method is adopted for solving the diagonal matrix of the first target block with strong reusability in the BBD matrix, and the solving speed and the calculating accuracy of the diagonal matrix of the first target block can be integrally improved based on the advantages of good universality, high solving result accuracy, stable performance and the like of the sparse matrix direct method.
In one embodiment, the solving the linear equation of the second target block diagonal matrix of the processed BBD matrix to obtain the root circuit calculation result includes: and solving a linear equation of the diagonal matrix of the second target block by an iteration method to obtain a root circuit calculation result.
In the implementation process, the relatively complex diagonal matrix of the second target block in the BBD matrix is solved by adopting an iteration method, and the solving speed of the diagonal matrix of the second target block can be improved based on the advantage of high solving speed of the iteration method. In addition, the parallel effect of low data volume transmission is achieved by limiting the transmission information volume between the sub-calculation unit and the root calculation unit and combining the analysis and solving algorithm, and the parallel efficiency is greatly improved.
In one embodiment, the solving the linear equation of the second target block diagonal matrix of the processed BBD matrix to obtain the root circuit calculation result further includes: and constructing a precondition according to the BBD matrix, and solving the linear equation through the precondition and matrix vector multiplication to obtain a root circuit calculation result.
In the implementation process, when the complex matrix of the diagonal matrix of the second target block is calculated, the precondition is created first, so that the dense matrix with extremely high complexity can be avoided from being decomposed and the complex matrix can be calculated explicitly, the calculation of the complex matrix is simplified, and the calculation efficiency is improved. Meanwhile, dense matrixes can be prevented from being transmitted between the sub-computing units and the root computing units, so that huge traffic is prevented from being generated, and the parallel efficiency is greatly improved.
In one embodiment, before the partitioning of the netlist circuit into the plurality of sub-circuits according to the hypergraph partitioning rules and the initial information of the netlist circuit, the method further comprises: analyzing original information of a netlist circuit in netlist information, and constructing a hypergraph corresponding to the netlist circuit according to the original information; the partitioning of the netlist circuit into a plurality of sub-circuits according to hypergraph partitioning rules and initial information of the netlist circuit comprises: and processing the hypergraph through the hypergraph dividing rule to obtain a plurality of sub-circuits.
In the implementation process, the netlist information of the netlist circuit is processed and decomposed, and the connection relation among devices is marked and classified, so that the array is output together when the hypergraph relation is output, the hypergraph division is convenient to follow-up, and the data processing efficiency is improved.
In one embodiment, the parsing the original information of the netlist circuit in the netlist information and constructing a hypergraph corresponding to the netlist circuit according to the original information includes: analyzing original information of a netlist circuit in netlist information to describe device connection relations in the netlist circuit through a plurality of vectors; and constructing a hypergraph corresponding to the netlist circuit according to the device connection relations in the netlist circuit described by the vectors.
In the implementation process, the connection relation of devices in the netlist circuit is described through vectors, and the information of the netlist circuit is transmitted in the form of vectors through the connection relation of the devices in the netlist circuit described through vectors. The size of the transmission quantity of the data is controlled, the data transmission efficiency is improved, and the simulation speed is further improved.
In one embodiment, the initial information includes devices and nodes of the netlist circuit, and the processing of the hypergraph by the hypergraph partitioning rule to obtain a plurality of sub-circuits includes: matching and clustering the device and the node to obtain a coarsened hypergraph; and carrying out multi-layer hypergraph division on the coarsened hypergraph to obtain a plurality of sub-circuits.
In the implementation process, when hypergraph division is performed, rough division is performed on the hypergraph, then multi-layer division is further performed, and the hypergraph is divided for a plurality of times, so that the accuracy of hypergraph division is improved.
In one embodiment, said matching and clustering said device and said node to obtain a coarsened hypergraph comprises: and matching and clustering the device and the nodes according to preset partition information to obtain a coarsened hypergraph.
In the implementation process, by dividing part of hypergraphs in advance, only part of hypergraphs need to be matched and clustered when hypergraphs are divided, and the hypergraph dividing speed and the hypergraph dividing reliability can be effectively improved.
In a second aspect, an embodiment of the present application further provides a circuit simulation apparatus, including: the partitioning module is used for partitioning the netlist circuit into a plurality of sub-circuits according to hypergraph partitioning rules and initial information of the netlist circuit; a matrix creation module for modeling a plurality of the sub-circuits in parallel to obtain a BBD matrix; the solving module is used for parallelly solving the block diagonal matrix of the BBD matrix to obtain a comprehensive calculation result of the netlist circuit so as to complete the netlist circuit simulation; wherein, the BBD matrix is a single-layer BBD structure.
In a third aspect, an embodiment of the present application further provides an electronic device, including: a processor, a memory storing machine-readable instructions executable by the processor, which when executed by the processor, perform the steps of the method of the first aspect, or any of the possible implementations of the first aspect.
In a fourth aspect, embodiments of the present application also provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the circuit emulation method of the first aspect, or any possible implementation of the first aspect.
In order to make the above objects, features and advantages of the present application more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a circuit simulation method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a parallel computing system according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a functional module of a circuit simulation device according to an embodiment of the present application;
Fig. 4 is a block schematic diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
MPI parallel computation is an important means for solving the simulation bottleneck of an EDA tool, and is also a key technology for deploying a cloud platform by the EDA tool. The basic idea of MPI parallel computing is to divide a problem that requires very much computational power to solve into many small parts, then distribute these parts to multiple cores/computers/servers for processing, and finally integrate the results of the computations to get the final result. Therefore, the overall calculation time can be saved, and the calculation efficiency is greatly improved.
The current common circuit simulation MPI parallel computation mainly focuses on the parallel of a linear equation system solving method used in simulation. However, this degree of parallelism does not significantly accelerate the speed of the simulation.
In view of this, the present inventors have generally studied for a long time and proposed a circuit simulation method. The circuit is divided into a plurality of sub-circuits, the sub-circuits are solved and calculated in parallel, and after the calculation results are integrated, circuit simulation is carried out, so that the time for circuit analysis and calculation can be greatly reduced, and the circuit simulation efficiency is improved.
Please refer to fig. 1, which is a flowchart of a circuit simulation method according to an embodiment of the present application. The specific flow shown in fig. 1 will be described in detail.
Step 201, dividing the netlist circuit into a plurality of sub-circuits according to hypergraph division rules and initial information of the netlist circuit.
The hypergraph division rule may be a division rule set by a person, a rule formed by clustering, or the like. The hypergraph division rule may be stored in advance in the memory device or may be input to the processing device together with the netlist circuit. It can be appreciated that if the hypergraph partitioning rule is an unsupervised learning clustering rule, the hypergraph partitioning rule may be updated after each circuit simulation, or periodically updated, so as to improve the accuracy of the hypergraph partitioning rule.
The initial information of the netlist circuit may include the cells of the netlist circuit, the electrical characteristics of the components, pins, ports, loads, etc.
Step 202, modeling a plurality of sub-circuits in parallel to obtain a BBD matrix.
Wherein, the BBD matrix is a single-layer BBD structure.
And 203, solving the block diagonal matrix of the BBD matrix in parallel to obtain a comprehensive calculation result of the netlist circuit so as to complete the netlist circuit simulation.
It can be understood that after the block diagonal matrix of the BBD matrix is solved in parallel to obtain the comprehensive calculation result of the netlist circuit, a corresponding waveform can be output according to the comprehensive calculation result, so as to complete the netlist circuit simulation through the waveform.
As shown in fig. 2, the parallel computing system for performing steps 202 and 203 described above may include a plurality of sub-computing units, sub-memories, a root computing unit, and a root memory. The root computing unit controls the root memory, each sub-computing unit controls the corresponding sub-memory, and two-way communication exists between the root computing unit and the sub-computing unit. The sub-calculation unit is used for processing the sub-circuits, and one sub-calculation unit corresponds to one sub-circuit. When multiple subcircuits need to be analyzed and solved, the multiple subcircuit calculation units simultaneously perform parallel calculation on the corresponding subcircuits. After determining the sub-circuit calculation result calculated by the sub-calculation unit, the root calculation unit is used for processing the coupling circuit and outputting the final result.
The parallel computing system can be arranged in a core, a processor, a server, a cloud end and other devices for use. In the parallel computing system, each sub-computing unit is connected in series, and the sub-computing unit is connected in series with the root computing unit.
In some embodiments, each sub-computing unit may include an analyzer and a solver, the analyzer to model the plurality of sub-circuits in parallel after analysis to obtain the BBD matrix. The solver is used for carrying out parallel solving on the block diagonal matrix of the BBD matrix.
In the implementation process, the netlist circuit is divided into a plurality of sub-circuits, and the plurality of sub-circuits are analyzed and solved in parallel, so that the plurality of sub-circuits are analyzed and processed at the same time, the time for overall analysis and processing of the netlist circuit is shortened, and the circuit simulation speed is improved. In addition, the BBD matrix is set to be a single layer, so that the difficulty of BBD matrix calculation is simplified, and the calculation difficulty of circuit simulation is simplified.
In one possible implementation, step 203 includes: processing the BBD matrix by a block Gaussian elimination method to obtain a processed BBD matrix; carrying out parallel solving on a first target block diagonal matrix of the processed BBD matrix to obtain a sub-circuit calculation result; solving a linear equation of a second target block diagonal matrix of the processed BBD matrix to obtain a root circuit calculation result; and determining the comprehensive calculation result according to the sub-circuit calculation result and the root circuit calculation result to complete the netlist circuit simulation.
Wherein the first target block diagonal matrix and the second target block diagonal matrix are each part of a BBD matrix.
Illustratively, the BBD matrix can be of the form:
;
Wherein, 、、、、、D is the block matrix built up for each sub-circuit.
After the BBD matrix is subjected to Gaussian processing, the processed BBD matrix can be in the following form:
；
s matrix sum of the processed BBD matrix The matrix can be represented by the following linear equation:
；
；
The first target block diagonal matrix here may be the first K block diagonal matrices of the processed BBD matrix. The second target block diagonal matrix may be the block diagonal matrix S of the BBD matrix after the processing described above.
From the BBD matrix structure, the above-、-、-Is a reusable block diagonal matrix and can therefore be solved by employing a sparse matrix direct method. For the block diagonal matrix S, the block diagonal matrix S is a dense matrix, and thus can be solved by using an iterative method.
It will be appreciated that the above-described solution of the first and second target diagonal matrices is a corresponding preferred calculation method based on the feature selection of the respective block diagonal matrices in the BBD matrix. Of course, the calculation method of the first target diagonal matrix and the second target diagonal matrix is not limited to the calculation method described above. For example, the first target diagonal matrix and the second target diagonal matrix may be both solved by a direct method or may be both solved by an iterative method. The solution manner of the first target diagonal matrix and the second target diagonal matrix can be adjusted according to the actual situation, and the application is not particularly limited.
Alternatively, the solution of the first target block diagonal matrix may be performed in series with the solution of the second target block diagonal matrix, or may be performed in parallel. The implementation manner of the solution of the diagonal matrix of the one target block and the solution of the diagonal matrix of the second target block can be adjusted according to actual conditions, and the application is not particularly limited.
The combined calculation result may be a calculation result obtained by coupling the sub-circuit calculation result and the root circuit calculation result.
In the implementation process, different characteristics of the block diagonal matrix in different areas of the BBD matrix are calculated according to the characteristics of different block diagonal matrices in the BBD matrix, corresponding calculation modes can be matched according to the characteristics of different block diagonal matrices, calculation of the BBD matrix is simplified, and calculation efficiency is improved.
In one possible implementation manner, the parallel solving of the first target block diagonal matrix of the block diagonal matrix to obtain the sub-circuit calculation result includes: and carrying out parallel pre-solving on the diagonal matrix of the first target block by a sparse matrix direct method to obtain a subcircuit calculation result.
The sparse matrix direct method here may be sparse LU decomposition, LDLT decomposition, cholesky decomposition, or the like.
Common methods of solving sparse matrices include direct and iterative methods. The direct method refers to an accurate solution of a system of equations by operations involving finite steps such as matrix decomposition and solution of a system of trigonometric equations without considering calculation of rounding errors, and is therefore also called an accurate method. The iterative method refers to that an initial solution vector is given, a vector column is constructed through a certain calculation (a series of approximate solutions approximating accurate values are generally obtained through successive iteration), and the limit of the vector column is the theoretical accurate solution of the equation set. Compared with the iterative method, the direct method has the advantages of good universality, high accuracy of solving results and stable performance. The advantages of the direct method are particularly apparent when the matrix decomposition result can be reused by multiple subsequent computations and multiple right-hand terms. Therefore, for the first K diagonal block matrixes in the BBD matrix, due to strong reusability, the calculation time of the first K diagonal block matrixes is reduced by adopting the sparse matrix direct method to solve the problem, and the calculation efficiency is improved.
Illustratively, the above-mentioned processed BBD matrix is decomposed by adopting sparse LU decomposition, and then the diagonal matrix of first K blocks of the processed BBD matrix is undergone the process of LU decomposition and pre-decomposition so as to obtain the invented BBD matrixSystem calculation after LU decomposition is reused。
In the implementation process, the sparse matrix direct method is adopted for solving the diagonal matrix of the first target block with strong reusability in the BBD matrix, and the solving speed and the calculating accuracy of the diagonal matrix of the first target block can be integrally improved based on the advantages of good universality, high solving result accuracy, stable performance and the like of the sparse matrix direct method.
In one possible implementation, solving the linear equation of the second target block diagonal matrix of the block diagonal matrix to obtain the root circuit calculation result includes: and solving a linear equation of a second target block diagonal matrix of the block diagonal matrix by an iteration method to obtain a root circuit calculation result.
The iterative method herein may include a conjugate gradient method, a minimum residual method, and the like.
The root circuit computation described above may be a root node computation or a coupled circuit computation on a processor.
The iterative method is a method of gradually approaching the accurate solution of the linear equation set by using a certain limit process. When faced with more complex problems, the solution cannot be achieved by direct methods, where iterative methods are typically used. Compared with a direct method, the method has the advantages that the solving speed is high, the specific value of the coupling circuit matrix is not needed, and only the matrix vector multiplication can be calculated. The solving method can be well combined with a parallel system, a dense matrix is not required to be transmitted between computing units, and only a vector is required to be transmitted. Therefore, for the complex matrix in the diagonal matrix of the second target block, the calculation speed of the diagonal matrix of the second target block can be improved by solving the complex matrix through the iterative method, and the transmission between the sub-calculation unit and the root calculation unit only needs to be carried out through vectors, so that the size of the transmission variable is strictly controlled. The dense matrix and the larger-scale coefficient matrix are not allowed to be transmitted between the computing units, so that the cost of the parallel system in the transmission process information is ensured to be small.
It will be appreciated that the second target block diagonal matrix in the BBD matrix is the S matrix, and that when solving the second target block diagonal matrix, it is essentially a system of linear equations that solve the S matrix. The linear equation system for solving the S matrix can be solved by adopting a precondition conjugate gradient method or a precondition generalized minimum residual method and the like.
In the implementation process, the relatively complex diagonal matrix of the second target block in the BBD matrix is solved by adopting an iteration method, and the solving speed of the diagonal matrix of the second target block can be improved based on the advantage of high solving speed of the iteration method. In addition, the parallel effect of low data volume transmission is achieved by limiting the transmission information volume between the sub-calculation unit and the root calculation unit and combining the analysis and solving algorithm, and the parallel efficiency is greatly improved.
In one possible implementation manner, solving the linear equation of the second target block diagonal matrix of the block diagonal matrix to obtain the root circuit calculation result further includes: and constructing a precondition according to the BBD matrix, and solving the linear equation through the precondition and matrix vector multiplication to obtain a root circuit calculation result.
The building of the preconditions from the BBD matrix here can be achieved by:
first, LU decomposition is performed on the D matrix ；
Then constructing a precondition matrix:；
Wherein, The precondition matrix of S, D is a second target block diagonal matrix of the original BBD matrix, L and U respectively correspond to a lower triangle and an upper triangle obtained by decomposing the matrix LU of D, and the matrix LU is divided into a lower triangle and an upper triangle,Correspondence matrixIs used for the maximum m feature vectors of (a),Correspondence matrixM is 10-20.
And finally, solving the precondition matrix.
The precondition solving can be realized by the following method: the method can use the symmetrical first and then Lanczos method to calculate the maximum eigenvalue and eigenvector, the process only needs to calculate the matrix vector multiplicationAnd (3) obtaining the product. And forSolving this precondition equation, we knowLU decomposition of (C)Can be regarded as a low-rank correction, so that a Sherman-Morrison formula can be introduced for rapid calculation. Thus, the precondition matrix is calculated.
Further, after the precondition matrix is determined, calculating an S matrix by a matrix vector multiplication method:
；
Wherein S is Schur complement matrix, D is right lower corner diagonal block matrix, For the lower edge block matrix,Is a diagonal block matrix of the upper left corner,Is a right side block matrix.
As can be found from the above calculation formula, we can calculate on the root calculation unitCalculating/>, in each sub-calculation unitThe calculation can be completed by solving only one linear equation set, so that the calculated amount is greatly reduced.
In the implementation process, when the complex matrix of the diagonal matrix of the second target block is calculated, the precondition is created first, so that the dense matrix with extremely high complexity can be avoided from being decomposed and the complex matrix can be calculated explicitly, the calculation of the complex matrix is simplified, and the calculation efficiency is improved. Meanwhile, dense matrixes can be prevented from being transmitted between the sub-computing units and the root computing units, so that huge traffic is prevented from being generated, and the parallel efficiency is greatly improved.
In one possible implementation, before step 201, it includes: and analyzing the original information of the netlist circuit in the netlist information, and constructing a hypergraph corresponding to the netlist circuit according to the original information. Step 201, comprising: and processing the hypergraph through a hypergraph dividing rule to obtain a plurality of sub-circuits.
The netlist information here may include various types of information. For example, for general information in netlist files, such as analysis information, model information, etc., syntactic semantic analysis is used and stored in the corresponding circuit class. For a statement that represents a device connection relationship, it can be extracted as a connection relationship among hypergraphs.
Illustratively, for netlist statement rbit 09 01 k, it needs to be represented as superside 9 connected with superside 0 with vertex rbit0. After all devices are scanned, output is performed in a compressed format of hypergraph.
In some embodiments, the sub-circuit portions of the netlist information require special processing.
Illustratively:
.SUBCKT NAND 1 2 3 4
* noeuds: entrees(2) sortie vcc
q1 9 5 1 qmod
d1clamp 0 1 dmod
q2 9 5 2 qmod
d2clamp 0 2 dmod
rb 4 5 4k
r1 4 6 1.6k
q3 6 9 8 qmod
r2 8 0 1k
rc 4 7 130
q4 7 6 10 qmod
dvbedrop 10 3 dmod
q5 3 8 0 qmod
.ends NAND
In some embodiments, all devices in the sub-circuit may also be manually marked when reading the connection between their devices, and the devices may be framed to be partitioned into the same partition in a later hypergraph partition. All devices in the sub-circuit may also be marked down by a classification model and framed to partition into the same partition in a later hypergraph partition, etc. The device fixed division relation represented by the sub-circuit is output in an array form at the same time of outputting the hypergraph representation, so that the final hypergraph representation is obtained.
In the implementation process, the netlist information of the netlist circuit is processed and decomposed, and the connection relation among devices is marked and classified, so that the array is output together when the hypergraph relation is output, the hypergraph division is convenient to follow-up, and the data processing efficiency is improved.
In one possible implementation, resolving original information of a netlist circuit in netlist information, and constructing a hypergraph corresponding to the netlist circuit according to the original information, including: analyzing original information of the netlist circuit in the netlist information to describe device connection relations in the netlist circuit through a plurality of vectors; and constructing a hypergraph corresponding to the netlist circuit according to the device connection relations in the netlist circuit described by the vectors.
In the implementation process, the connection relation of devices in the netlist circuit is described through vectors, and the information of the netlist circuit is transmitted in the form of vectors through the connection relation of the devices in the netlist circuit described through vectors. The size of the transmission quantity of the data is controlled, the data transmission efficiency is improved, and the simulation speed is further improved.
In one possible implementation, the initial information includes devices and nodes of the netlist circuit, and the hypergraph is processed by a hypergraph partitioning rule to obtain a plurality of sub-circuits, including: matching and clustering the devices and the nodes to obtain a coarsened hypergraph; and carrying out multi-layer hypergraph division on the coarsened hypergraph to obtain a plurality of sub-circuits.
After hypergraph representation is performed according to initial information (including but not limited to initial information of a sub-circuit and initial information of a sub-module of circuit design), devices and nodes are pre-aggregated according to a hypergraph dividing rule to obtain a thicker hypergraph, and then nodes of the hypergraph are matched pairwise and clustered according to a connection relation of the hypergraph. After the clustering is completed, the coarsest hypergraph can be obtained, and for the coarsest hypergraph, the coarsest hypergraph after the division of the coarsest hypergraph is obtained by dividing the coarsest hypergraph by using a spectrum method. And performing multi-level hypergraph division of aggregation-division-refinement on the coarsened hypergraph to obtain a plurality of sub-circuits.
The above clustering can be regarded as a problem of unsupervised learning, and can be performed by using kmeans method.
In some embodiments, the aggregation-division-refinement of the coarsened hypergraph multi-level hypergraph division to obtain multiple sub-circuits may be achieved by: and carrying out refinement correction based on a boundary Fiduccia-MATTHEYSES method, and recovering the aggregated vertexes into the hypergraph to obtain final hypergraph division so as to obtain a plurality of sub-circuits.
In the implementation process, when hypergraph division is performed, rough division is performed on the hypergraph, then multi-layer division is further performed, and the hypergraph is divided for a plurality of times, so that the accuracy of hypergraph division is improved.
In one possible implementation, matching and clustering the devices and nodes to obtain a coarsened hypergraph includes: and matching and clustering the device and the nodes according to preset partition information to obtain a coarsened hypergraph.
The preset division information here is a priori information in the circuit information. The pre-partition information may be artificial partition or deep learning network partition. The pre-dividing information can be understood as a hypergraph which is divided in advance, namely the pre-dividing information can be matched and clustered without matching and clustering when the hypergraph is divided, and only the non-pre-dividing information is matched and clustered, so that the hypergraph dividing speed and the hypergraph dividing reliability can be effectively improved.
In the implementation process, by dividing part of hypergraphs in advance, only part of hypergraphs need to be matched and clustered when hypergraphs are divided, and the hypergraph dividing speed and the hypergraph dividing reliability can be effectively improved.
Based on the same application conception, the embodiment of the application also provides a circuit simulation device corresponding to the circuit simulation method, and because the principle of solving the problem of the device in the embodiment of the application is similar to that of the embodiment of the circuit simulation method, the implementation of the device in the embodiment of the application can be referred to the description in the embodiment of the method, and the repetition is omitted.
Fig. 3 is a schematic functional block diagram of a circuit simulation device according to an embodiment of the application. The respective modules in the circuit simulation apparatus in the present embodiment are configured to execute the respective steps in the above-described method embodiment. The circuit simulation device comprises a dividing module 301, a matrix creation module 302 and a solving module 303; wherein,
The partitioning module 301 is configured to partition the netlist circuit into a plurality of sub-circuits according to a hypergraph partitioning rule and initial information of the netlist circuit.
The matrix creation module 302 is configured to model a plurality of the sub-circuits in parallel to obtain a BBD matrix.
The solving module 303 is configured to solve the block diagonal matrix of the BBD matrix in parallel to obtain a comprehensive calculation result of the netlist circuit, so as to complete the netlist circuit simulation; wherein, the BBD matrix is a single-layer BBD structure.
In a possible implementation, the solving module 303 is further configured to: processing the BBD matrix by a block Gaussian elimination method to obtain a processed BBD matrix; carrying out parallel solving on a first target block diagonal matrix of the processed BBD matrix to obtain a subcircuit calculation result; solving a linear equation of a diagonal matrix of a second target block of the processed BBD matrix to obtain a root circuit calculation result; determining the comprehensive calculation result according to the sub-circuit calculation result and the root circuit calculation result to complete the netlist circuit simulation; wherein the first target block diagonal matrix and the second target block diagonal matrix are each part of the BBD matrix.
In a possible implementation, the solving module 303 is specifically configured to: and carrying out parallel pre-solving on the diagonal matrix of the first target block by a sparse matrix direct method to obtain a subcircuit calculation result.
In a possible implementation, the solving module 303 is specifically configured to: and solving a linear equation of the diagonal matrix of the second target block by an iteration method to obtain a root circuit calculation result.
In a possible implementation, the solving module 303 is specifically configured to: and constructing a precondition according to the BBD matrix, and solving the linear equation through the precondition and matrix vector multiplication to obtain a root circuit calculation result.
In a possible implementation manner, the circuit simulation device further comprises a parsing module, configured to: and analyzing the original information of the netlist circuit in the netlist information, and constructing a hypergraph corresponding to the netlist circuit according to the original information.
In a possible implementation manner, the dividing module 301 is specifically configured to: and processing the hypergraph through the hypergraph dividing rule to obtain a plurality of sub-circuits.
In a possible implementation manner, the parsing module is specifically configured to: analyzing original information of a netlist circuit in netlist information to describe device connection relations in the netlist circuit through a plurality of vectors; and constructing a hypergraph corresponding to the netlist circuit according to the device connection relations in the netlist circuit described by the vectors.
In a possible implementation manner, the dividing module 301 is specifically configured to: matching and clustering the device and the node to obtain a coarsened hypergraph; and carrying out multi-layer hypergraph division on the coarsened hypergraph to obtain a plurality of sub-circuits.
In a possible implementation manner, the dividing module 301 is specifically configured to: and matching and clustering the device and the nodes according to preset partition information to obtain a coarsened hypergraph.
For the convenience of understanding the present embodiment, first, an electronic device for executing the circuit simulation method disclosed in the embodiment of the present application will be described in detail.
As shown in fig. 4, a block schematic diagram of the electronic device is shown. The electronic device 100 may include a memory 111, a processor 113. It will be appreciated by those of ordinary skill in the art that the configuration shown in fig. 4 is merely illustrative and is not limiting of the configuration of the electronic device 100. For example, electronic device 100 may also include more or fewer components than shown in FIG. 4, or have a different configuration than shown in FIG. 4.
The memory 111 and the processor 113 are directly or indirectly electrically connected to each other to realize data transmission or interaction. For example, the components may be electrically connected to each other via one or more communication buses or signal lines. The processor 113 is used to execute executable modules stored in the memory.
The Memory 111 may be, but is not limited to, a random access Memory (Random Access Memory, RAM), a Read Only Memory (ROM), a programmable Read Only Memory (Programmable Read-Only Memory, PROM), an erasable Read Only Memory (Erasable Programmable Read-Only Memory, EPROM), an electrically erasable Read Only Memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc. The memory 111 is configured to store a program, and the processor 113 executes the program after receiving an execution instruction, and a method executed by the electronic device 100 defined by the process disclosed in any embodiment of the present application may be applied to the processor 113 or implemented by the processor 113.
The processor 113 may be an integrated circuit chip having signal processing capabilities. The processor 113 may be a general-purpose processor, including a central processing unit (Central Processing Unit, abbreviated as CPU), a network processor (Network Processor, abbreviated as NP), and the like; but may also be a digital signal processor (DIGITAL SIGNAL processor, DSP for short), application SPECIFIC INTEGRATED Circuit (ASIC for short), field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The electronic device 100 in this embodiment may be used to perform each step in each method provided in the embodiment of the present application.
Furthermore, the embodiment of the present application also provides a computer readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the steps of the circuit simulation method described in the above method embodiment are executed.
The computer program product of the circuit simulation method provided by the embodiment of the present application includes a computer readable storage medium storing a program code, where the program code includes instructions for executing the steps of the circuit simulation method described in the above method embodiment, and the details of the method embodiment may be referred to above, and will not be described herein.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The apparatus embodiments described above are merely illustrative, for example, of the flowcharts and block diagrams in the figures that illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes. It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (10)
1. A circuit simulation method, comprising:
Dividing the netlist circuit into a plurality of sub-circuits according to hypergraph division rules and initial information of the netlist circuit;
Modeling a plurality of the sub-circuits in parallel to obtain a BBD matrix;
The block diagonal matrix of the BBD matrix is solved in parallel to obtain a comprehensive calculation result of the netlist circuit, so that netlist circuit simulation is completed;
wherein, the BBD matrix is a single-layer BBD structure;
The method for obtaining the comprehensive calculation result of the netlist circuit by solving the block diagonal matrix of the BBD matrix in parallel to complete the netlist circuit simulation comprises the following steps:
processing the BBD matrix by a block Gaussian elimination method to obtain a processed BBD matrix;
carrying out parallel solving on a first target block diagonal matrix of the processed BBD matrix to obtain a subcircuit calculation result;
solving a linear equation of a diagonal matrix of a second target block of the processed BBD matrix to obtain a root circuit calculation result;
determining the comprehensive calculation result according to the sub-circuit calculation result and the root circuit calculation result to complete the netlist circuit simulation;
wherein the first target block diagonal matrix and the second target block diagonal matrix are each part of the BBD matrix;
Constructing a precondition according to the BBD matrix, and solving the linear equation through the precondition and matrix vector multiplication to obtain a root circuit calculation result;
said constructing preconditions according to said BBD matrix, comprising:
Performing LU decomposition on the second target block diagonal matrix, and constructing a precondition matrix based on the second target block diagonal matrix after LU decomposition;
calculating a maximum eigenvalue and eigenvector by using a first symmetrization and Lanczos method;
Solving the precondition matrix through a Sherman-Morrison formula;
Wherein, the constructing precondition according to the BBD matrix specifically comprises:
Performing LU decomposition on the D matrix, i.e., d=lu;
constructing a precondition matrix:
Wherein, The precondition matrix of S is that D is a diagonal matrix of a second target block of the original BBD matrix, L and U respectively correspond to a lower triangle and an upper triangle obtained by decomposing the matrix LU of D, and X corresponds to matrixIs a maximum m eigenvectors of Λ corresponding to matrixM is between 10 and 20, R i is the lower side block matrix, B i is the diagonal block matrix of the upper left corner, and C i is the right side block matrix.
2. The method of claim 1, wherein the parallel solving of the first target block diagonal matrix of the processed BBD matrix results in a sub-circuit calculation result, comprising:
and carrying out parallel pre-solving on the diagonal matrix of the first target block by a sparse matrix direct method to obtain a subcircuit calculation result.
3. The method of claim 1, wherein solving the linear equation of the second target block diagonal matrix of the processed BBD matrix results in a root circuit calculation result, comprising:
and solving a linear equation of the diagonal matrix of the second target block by an iteration method to obtain a root circuit calculation result.
4. The method of claim 1, wherein prior to dividing the netlist circuit into a plurality of sub-circuits according to hypergraph division rules and initial information of the netlist circuit, the method further comprises:
Analyzing original information of a netlist circuit in netlist information, and constructing a hypergraph corresponding to the netlist circuit according to the original information;
the partitioning of the netlist circuit into a plurality of sub-circuits according to hypergraph partitioning rules and initial information of the netlist circuit comprises:
And processing the hypergraph through the hypergraph dividing rule to obtain a plurality of sub-circuits.
5. The method of claim 4, wherein parsing the original information of the netlist circuit in the netlist information and constructing a hypergraph corresponding to the netlist circuit according to the original information comprises:
analyzing original information of a netlist circuit in netlist information to describe device connection relations in the netlist circuit through a plurality of vectors;
and constructing a hypergraph corresponding to the netlist circuit according to the device connection relations in the netlist circuit described by the vectors.
6. The method of claim 4, wherein the initial information includes devices and nodes of the netlist circuit, the processing the hypergraph according to a hypergraph partitioning rule to obtain a plurality of sub-circuits, comprising:
matching and clustering the device and the node to obtain a coarsened hypergraph;
And carrying out multi-layer hypergraph division on the coarsened hypergraph to obtain a plurality of sub-circuits.
7. The method of claim 6, wherein said matching and clustering the device and the node to obtain a coarsened hypergraph comprises:
And matching and clustering the device and the nodes according to preset partition information to obtain a coarsened hypergraph.
8. A circuit emulation device, comprising:
the partitioning module is used for partitioning the netlist circuit into a plurality of sub-circuits according to hypergraph partitioning rules and initial information of the netlist circuit;
a matrix creation module for modeling a plurality of the sub-circuits in parallel to obtain a BBD matrix;
The solving module is used for solving the block diagonal matrix of the BBD matrix in parallel to obtain a comprehensive calculation result of the netlist circuit so as to complete netlist circuit simulation;
wherein, the BBD matrix is a single-layer BBD structure;
The solving module is further configured to: processing the BBD matrix by a block Gaussian elimination method to obtain a processed BBD matrix; carrying out parallel solving on a first target block diagonal matrix of the processed BBD matrix to obtain a subcircuit calculation result; solving a linear equation of a diagonal matrix of a second target block of the processed BBD matrix to obtain a root circuit calculation result; determining the comprehensive calculation result according to the sub-circuit calculation result and the root circuit calculation result to complete the netlist circuit simulation; wherein the first target block diagonal matrix and the second target block diagonal matrix are each part of the BBD matrix;
The solving module is specifically configured to: constructing a precondition according to the BBD matrix, and solving the linear equation through the precondition and matrix vector multiplication to obtain a root circuit calculation result;
The solving module is specifically further configured to: performing LU decomposition on the second target block diagonal matrix, and constructing a precondition matrix based on the second target block diagonal matrix after LU decomposition; calculating a maximum eigenvalue and eigenvector by using a first symmetrization and Lanczos method; solving the precondition matrix through a Sherman-Morrison formula;
The solving module is specifically further configured to: performing LU decomposition on the D matrix, i.e., d=lu; constructing a precondition matrix:
Wherein, The precondition matrix of S is that D is a diagonal matrix of a second target block of the original BBD matrix, L and U respectively correspond to a lower triangle and an upper triangle obtained by decomposing the matrix LU of D, and X corresponds to matrixIs a maximum m eigenvectors of Λ corresponding to matrixM is between 10 and 20, R i is the lower side block matrix, B i is the diagonal block matrix of the upper left corner, and C i is the right side block matrix.
9. An electronic device, comprising: a processor, a memory storing machine-readable instructions executable by the processor, which when executed by the processor perform the steps of the method of any of claims 1-7 when the electronic device is run.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a computer program which, when run by a processor, performs the steps of the method according to any of claims 1-7.
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