CN116070573A

CN116070573A - Soft error layout optimization method considering pulse narrowing

Info

Publication number: CN116070573A
Application number: CN202310208293.1A
Authority: CN
Inventors: 贺旭; 刘畅; 李暾; 屈婉霞; 吴强; 张吉良
Original assignee: Hunan University; National University of Defense Technology
Current assignee: Hunan University; National University of Defense Technology
Priority date: 2023-03-07
Filing date: 2023-03-07
Publication date: 2023-05-05
Anticipated expiration: 2043-03-07
Also published as: CN116070573B

Abstract

The embodiment of the invention provides a soft error layout optimization method considering pulse narrowing, which belongs to the technical field of data processing and specifically comprises the following steps: step 1, carrying out logic synthesis on a preset RTL design and generating an input layout by adopting a layout tool; step 2, globally finding all possible unit pairs in the input layout by using a KM algorithm to obtain a unit pairing result; step 3, generating a combined unit according to the unit pairing result, and calculating the initial position and the size of the combined unit according to the original unit information; step 4, calculating the repositioning of the units considering the displacement based on the initial positions of all the units, and obtaining a quenching unit pair meeting the quenching effect; and 5, further optimizing the line length by using a preset operation under the condition of considering the quenching unit pairs, wherein the preset operation comprises a unit exchange operation and a unit insertion operation, and finally generating an optimized layout result. By the scheme, the optimization efficiency and the quenching effect enhancement performance are improved.

Description

Soft error layout optimization method considering pulse narrowing

Technical Field

The embodiment of the invention relates to the technical field of data processing, in particular to a soft error layout optimization method considering pulse narrowing.

Background

Currently, as feature sizes continue to shrink, modern CMOS devices and Integrated Circuits (ICs) become more susceptible to soft errors due to smaller capacitance and lower operating voltages. Soft errors can be caused by a variety of reasons, such as alpha particles from package decay, secondary particles from cosmic rays, crosstalk, random noise in the circuit, etc., where radiation-induced single event transient pulse (SET) effects are the primary cause of soft errors. SET is a transient pulse caused by a single ionized particle generating "accumulated charge" through a sensitive area in the device. SET is a serious reliability problem for ICs because SET can create faults and soft errors in the circuit and even cause equipment damage.

However, existing layout optimization methods, such as the former work Chang Liu, xu He, bin Liang, and Yang Guo.2018. Detailed placement for pulse quenching enhancement in anti-radiation combinational circuit design. Integration, VLSI 62 (2018), 182-189, have limited pulse narrowing effect enhancement because the process of cell movement is performed in a one-by-one fashion without global view.

It can be seen that there is a need for a soft error layout optimization method that is efficient, has enhanced performance stability due to quenching effects, and allows for pulse narrowing.

Disclosure of Invention

In view of this, the embodiments of the present invention provide a soft error layout optimization method considering pulse narrowing, which at least partially solves the problems of poor optimization efficiency and poor enhancement performance of quenching effect in the prior art.

The embodiment of the invention provides a soft error layout optimization method considering pulse narrowing, which comprises the following steps:

step 1, carrying out logic synthesis on a preset RTL design and generating an input layout by adopting a layout tool;

step 2, globally finding all possible unit pairs in the input layout by using a KM algorithm to obtain a unit pairing result;

step 3, generating a combined unit according to the unit pairing result, and calculating the initial position and the size of the combined unit according to the original unit information;

step 4, calculating the repositioning of the units considering the displacement based on the initial positions of all the units, and obtaining a quenching unit pair meeting the quenching effect;

and 5, further optimizing the line length by using a preset operation under the condition of considering the quenching unit pairs, wherein the preset operation comprises a unit exchange operation and a unit insertion operation, and finally generating an optimized layout result.

According to a specific implementation manner of the embodiment of the present invention, the step 2 specifically includes:

step 2.1, generating a fan-out set corresponding to each unit and calculating the sensitivity of each unit;

and 2.2, pairing each unit with the highest sensitivity in the fan-out set corresponding to the unit by using a KM algorithm to form a unit pairing result.

According to a specific implementation manner of the embodiment of the present invention, the step 2.2 specifically includes:

is provided with

and

Units->

And fan-out unit->

And calculating unit

And fan-out unit->

Pairing weights of (a);

constructing a connection graph

, wherein

Representing a set of fan-in units,/->

Representing a set of fan-out units>

Representing a connection set;

and calling a KM algorithm to perform global unit pairing on the connection diagram to form a unit pairing result.

According to a specific implementation manner of the embodiment of the present invention, the calculation formula of the pairing weight is

wherein ,

indicating sensitivity, & gt>

and

Are positive parameters.

According to a specific implementation manner of the embodiment of the present invention, the step 3 specifically includes:

described as based on existing raw cell information and displacement driving problems

And rewrites the layout problem according to preset conditions;

Inferring initial information of the combined unit, for the integrated unit

The width and initial coordinates are calculated as follows:

wherein ,

and

Respectively represent->

Width and initial lower left corner coordinates of the cell, accordingly, for the subunit +.>

，

and

Respectively indicate->

And the initial lower left corner coordinates.

According to a specific implementation manner of the embodiment of the present invention, the step 4 specifically includes:

step 4.1, repositioning the combined unit and the unpaired unit through formulas corresponding to layout problems, modeling a linear complementation problem, giving unit information and a connection relation netlist of the combined unit and the unpaired unit, and constructing a linear complementation problem data structure;

step 4.2, compressing the linear complementation problem data structure through a two-step scanning strategy to construct a corresponding constraint matrix, and solving the linear complementation problem by using a matrix splitting iteration method based on a mode;

and 4.3, obtaining the repositioned unit coordinates according to the solving result, and carrying out integer processing on the repositioning unit coordinates to obtain legal positions of all units including the combined unit, wherein the original adjacent unit pair in the combined unit after successful layout is taken as a quenching unit pair.

According to a specific implementation manner of the embodiment of the present invention, the expression of the layout problem is

wherein ,

is the horizontal coordinate vector of all units, +.>

Is an identity matrix>

Is each element

Vector of->

Is a constraint matrix of horizontal adjacent relation of left and right units, < >>

Only two non-zero elements-1 and 1 in each row, < >>

The number of rows of (a) is the left and right constraint number of the cell in the horizontal direction,/->

The number of columns of (a) is the number of units, vector +.>

Each element of the matrix>

The width of the left cell in each row of left and right horizontally adjacent constraints.

According to a specific implementation manner of the embodiment of the present invention, the corresponding constraint matrix is constructed by compressing the linear complementary problem data structure through a two-step scanning strategy

The method comprises the following steps:

when scanning cells in a row from left to right, firstly, forming adjacent constraint by odd-numbered cells and right adjacent cells thereof;

after the first scan, a second scan is started, adding the neighbor constraint of the cell and its right neighbor at even locations.

The soft error layout optimization scheme considering pulse narrowing in the embodiment of the invention comprises the following steps: step 1, carrying out logic synthesis on a preset RTL design and generating an input layout by adopting a layout tool; step 2, globally finding all possible unit pairs in the input layout by using a KM algorithm to obtain a unit pairing result; step 3, generating a combined unit according to the unit pairing result, and calculating the initial position and the size of the combined unit according to the original unit information; step 4, calculating the repositioning of the units considering the displacement based on the initial positions of all the units, and obtaining a quenching unit pair meeting the quenching effect; and 5, further optimizing the line length by using a preset operation under the condition of considering the quenching unit pairs, wherein the preset operation comprises a unit exchange operation and a unit insertion operation, and finally generating an optimized layout result.

The embodiment of the invention has the beneficial effects that: according to the scheme of the invention, the quenching effect enhancement is considered to optimize the soft error rate during layout, so that soft error generation in a circuit can be reduced under the condition of not introducing any hardware penalty, the units are dynamically paired during the layout by setting a layout algorithm, then all the units are globally paired once, and in the subsequent unit relocation process, the units are globally relocated, so that the quenching effect between adjacent logic related units is enhanced, and the optimization efficiency and the quenching effect enhancement performance are improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic flow chart of a soft error layout optimization method considering pulse narrowing according to an embodiment of the present invention;

FIG. 2 is a detailed layout frame and an evaluation flow diagram thereof corresponding to a soft error layout optimization method considering pulse narrowing according to an embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating an exemplary quenching effect according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a unit pairing according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a combined unit formed by combining the head and the tail according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a unit relocation process according to an embodiment of the present invention;

fig. 7 is a schematic diagram of a process of merging paired units into a combined unit according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a matrix according to an embodiment of the present invention

Schematic diagrams of two scanning construction methods;

fig. 9 is a schematic diagram of an exemplary layout taking quenching effect into consideration according to an embodiment of the present invention.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present disclosure, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.

It should also be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.

In addition, in the following description, specific details are provided in order to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.

The embodiment of the invention provides a soft error layout optimization method considering pulse narrowing, which can be applied to a layout optimization process of a chip design scene.

Referring to fig. 1, a flow chart of a soft error layout optimization method considering pulse narrowing is provided in an embodiment of the present invention. As shown in fig. 1 and 2, the method mainly comprises the following steps:

the Soft Error Rate (SER) may be optimized at different levels from software to hardware. The method for optimizing SER by layout mainly utilizes pulse narrowing effect, namely Quenching effect (quench) in a SET propagation path to reduce the probability of the SET reaching a final output end. Compared with other soft error rate optimization methods, the pulse narrowing effect is enhanced by using the layout, and the SER is optimized without any chip area cost or flow process adjustment. Unit cell

and

Are all inverters, their output nodes are named +.>

and

. Initially, assume +.>

The input of (1) is high,/->

The PMOS of (c) is OFF,

is LOW, and->

The associated PMOS transistor is ON.

As shown in FIG. 3, wherein (a) indicates that if the ions hit

The PMOS transistor is turned off +.>

The logic low state at will be driven high by charge collection and then at +.>

The set pulse high is generated. The SET pulse will propagate to +.>

Resulting in->

HIGH to LOW transition at +.>

The PMOS state of (c) becomes OFF.

(b) Indicating when

When PMOS is off, it is sensitive to charge collection. If->

and

Is physically close to each other because charge sharing can make SET charge from +.>

Diffusion to->

，

Will be turned back ON, thus will +.>

Is driven to HIGH again. At->

The LOW-to-HIGH transition at this point resets the node voltage to the pre-event state.

(c) Representation of

The pulses at are effectively truncated so that +.>

Only very narrow pulse widths are present, i.e. a quenching effect is produced. The longer pulse can propagate unattenuated deep in the logic>

The narrow pulse at that point is likely to be further attenuated or even filtered out by the logic gate on the subsequent path or not latched due to the longer clock period. Thus, the first and second substrates are bonded together,

and

Pairing can be used to enhance the quenching effect.

It should be noted that the pulse narrowing effect occurs under three conditions, circuit structure connected, layout position adjacent and in a proper level state. In the layout process, the netlist structure is unchanged, namely the connection relation of the units is not changed, the level state of each unit is related to input excitation, and the positions of the units on the layout can be controlled. Accordingly, the focus herein is on the positional relationship of the electrically connected cells. Two units which are connected in the definition circuit and are positioned in the same row and adjacent to each other in the layout are quenching unit pairs, and only the quenching unit pairs can generate pulse narrowing effect.

Since the shrinkage of the SET pulse width is highly dependent on the physical distance between the electrically related cells. If the distance is too large, the pulse narrowing effect disappears. To maximize the pulse narrowing effect, the two units of the same quenching unit pair should be horizontally close to each other. It is worth supplementing that vertical neighbors are not considered in pulse narrowing enhancement, because the well/substrate contact area between layout rows affects charge transfer, significantly impairing the pulse narrowing effect.

Considering that the cells in the quenched cell pairs require horizontally adjacent layouts, the global layout cannot determine the final location of the cells, so our algorithm works in a detailed layout.

The detailed layout problem of pulse narrowing enhancement can be expressed as hypergraph

Layout problems. Standard unit->

And wire mesh->

，

，

. For each unit->

Its coordinates are +.>

Width is->

. In this work, each cell has a uniform height, equal to the height of the layout row. Given width of +.>

Height->

Layout area of HDomain->

Each movable unit->

Coordinates of->

) The following requirements need to be met:

located in legal area

An inner part;

not overlapping with other circuit units;

layout is within a cell row.

Definition 1: in our work, a cell pair

Is defined as a pair of quenching units if and only if +.>

, and

and

Is horizontally adjacent.

Based on the above analysis, the basis for the occurrence of the pulse narrowing effect is the presence of pairs of quenching units, the distance between which determines the intensity of the pulse narrowing effect. The detailed layout is to optimize SER by generating as many quenching cell pairs as possible. Since two cells in each quench cell pair require horizontally adjacent layouts, we also consider layout shifts when moving cells in order to avoid unduly affecting circuit performance. Thus, the objective of our detailed layout is to maximize the number of quench cell pairs while minimizing cell displacement.

In specific implementation, three unit types of INV, NAND and NOR in a 65nm unit library can be used for circuit construction. To obtain an input layout, a given register transfer level (Register Transfer Level, RTL) design is first logically integrated by the Synopsys Design Compiler tool and then the layout is generated by the cancer Innovus tool.

further, the step 2 specifically includes:

Further, the step 2.2 specifically includes:

is provided with

and

Units->

And fan-out unit->

And calculating unit

And fan-out unit->

Pairing weights of (a);

constructing a connection graph

, wherein

Representing a set of fan-in units,/->

Indicating fanOut of the set of units, +.>

Representing a connection set;

Further, the calculation formula of the pairing weight is as follows

wherein ,

indicating sensitivity, & gt>

and

Are positive parameters.

In practice, for each cell

，

Representing its fan-out set. We need to select the best unit +.>

And will->

and

Put together to finally generate a cell pair. At the time of selecting candidates

When, two factors will be considered:

cell sensitivity: sensitivity of the cell to SET after impact by a single ion. The higher the sensitivity, the higher the unit priority that needs to mask the SET.

Distance: the original distance between the two units. In order to reduce the displacement when combining the paired units, their original distance should be within a certain range threshold.

The sensitivity concept can be employed to evaluate the radiation resistance of each cell. For units

Sensitivity of->

Calculated by equation (1).

（1）

wherein

Representation unit->

The probability of the output value of (2) being LOW. As described above, the PMOS transistor of the cell in the OFF state is particularly sensitive to node charge collection. Thus, if->

The value of (2) is larger, then +.>

Easy generation of SET->

Is->

Probability of the SET pulse propagating to the circuit terminal. If it is

Very high, say->

Transient pulses are easily generated and may lead to soft errors. Thus (S) >

In the next cell repositioning process, the paired cells will move horizontally closer to each other, eventually forming a quenched cell pair. Our method pairs all cells simultaneously so that as much potential pulse narrowing effect as possible is produced.

Fig. 4 shows an example of unit pairing, in which (a) represents a unit connection relationship and (b) represents a unit pairing process. Unit cell

Only one fan-out->

，

Also only one fan in->

We can directly let +.>

and

Mate and horizontally approach each other during subsequent cell repositioning. In the case of multiple fan-out or fan-in units, the fan-out or fan-in with the highest SET sensitivity is selected for pairing. For example, in FIG. 4, unit +.>

There are two fan-in units, i.e. +.>

and

But only one fan-in can be associated with +.>

Pairing is in principle to select the cell where the probability of the SET pulse propagating to the terminal is high.

Since the two cells of a pairing need to be laid out together during cell repositioning, we should also consider cell distance when pairing cells. Otherwise, it will cause excessive displacement in subsequent cell relocations, affecting circuit performance, such as line length.

Here we describe weight calculation at cell pairing. Is provided with

and

Respectively->

and

Is used for the input coordinates of (a). We use +.>

To calculate +.>

Fan out from it->

Is a pairing weight of (a). As shown in formula (2), has high sensitivity and distance +.>

Fan-out of smaller distance>

Will preferably be +.>

Pairing. +.>

and

All positive parameters, < > in our experiments>

Set to the number of input vectors at simulation, +.>

；

（2）

The global pairing of units can be performed using the (Kuhn-Munkres) KM algorithm. First, we construct a connection graph

, wherein

Representing a set of fan-in units,/->

Representing a set of fan-out units. Given unit->

Each->

There is an edge +>

. Edge->

The weight on is equal to->

. FIG. 4 (b) shows a connection diagram corresponding to the netlist shown in FIG. 4 (a)>

And pairing results. Fanin unit set

Fan-out Unit set->

. Connection set->

. When a connection diagram is established->

And when the KM algorithm is used, the problem of unit pairing is solved. FIG. 4 (b) shows the pairing result, i.e

and

。/>

The calculation complexity of the KM pairing algorithm is as follows

, wherein

And->

. To reduce the run time we restrict +.>

I.e. +.>

. If the number of units exceeds +.>

The KM will be recalled until the unit pairing is complete.

In KM pairing result, each unit

May be paired up to two times, e.g. as a drive unit in a pairing or as a fan-out unit in a pairing. As shown in fig. 5, ->

Is paired twice, once as +.>

Is +.>

Is driven by a driver of (a). In our pairing method, if a unit is paired twice, once as a drive and once as a fan-out, the two pairs can be combined into one combination. FIG. 5 shows an example of pairing result +.>

，

Can be combined into a combination +.>

Meanwhile, when one unit is paired twice, a distance threshold may be set, and then a more appropriate unit may be selected for pairing according to the threshold between units.

on the basis of the above embodiment, the step 3 specifically includes:

And rewrites the layout problem according to preset conditions;

inferring initial information of the combined unit, for the integrated unit

The width and initial coordinates are calculated as follows:

wherein ,

and

Respectively represent->

Width and initial lower left corner coordinates of the cell, accordingly, for the subunit +. >

，

and

Respectively indicate->

And the initial lower left corner coordinates.

In specific implementation, based on the unit pairing result, we perform unit repositioning to finally generate quenching pairs, so as to realize pulse narrowing effect enhancement. The cell relocation flow is shown in fig. 6. In order to reduce the performance impact of the mobile unit on the cell relocation process, the target of the cell relocation process is set to minimize displacement. Given chip layout area and standard cell set

Wherein each cell has a width +.>

And unifying the heights, the cell repositioning problem can be expressed by formula (3); />

（3）

wherein ,

and

Units->

And the repositioned lower left corner coordinates. Each unit->

Go->

Alignment, i.e.)>

，

Is->

Bottom of row->

Coordinates. The cells in a row are according to their +.>

Ordering of coordinates, i.e. if units +.>

Is positioned at->

Right side of (2)>

. All cells have to be laid out in the chip area, i.e. for row +.>

Units of (a) which are->

Coordinates cannot exceed +.>

I.e. go->

Right boundary of (c).

In an implementation, it is assumed that each cell is directly aligned with its original row, i.e

，

. If the constraint on the cell beyond the right boundary of the row where it is located is further temporarily relaxed, equation (3) can be rewritten as equation (4);

(4)

wherein ,

is the horizontal coordinate vector of all units, +.>

Is an identity matrix>

Is each element

Vector of->

Only two non-zero elements-1 and 1 in each row, < >>

The number of columns of (a) is the number of cells.

In order to produce the pulse narrowing effect, the paired logically related cells must be laid out horizontally, close to each other. During a cell repositioning, the cells within one or more quenched cell pairs form a combined cell to ensure that after repositioning, the cells in the same pair or group are close to each other. Fig. 7 gives an example of a combination unit. Given two paired unit pairs

，

They can be combined into an integrated unit +.>

. To produce the pulse narrowing effect, the integrated cell width and initial coordinates are calculated from their internal cell initial coordinates.

For combined units

Wherein the subunit->

The width and initial coordinates of (2) are +.>

and ,

Then->

The width and initial coordinates of (a) are set according to equation (5); />

(5)

Wherein the width is

Is a combined unit->

The sum of the widths of all sub-units in (1)/(1)>

Coordinates->

Set to->

Median ∈of internal subunits >

Coordinates. But initially +.>

Coordinates->

Is more complex, and specific computational reasoning is given below.

For the case of t=2, i.e

. After cell relocation we get

and

. According to the purpose of formula (3), the combination unit +.>

Is +.>

Can be derived from equation (6);

(6)

for a plurality of units, forming a combined unit, i.e. t>In the case of 2, the number of the elements,

, wherein

We have->

_t And

,

,

. Similarly, the combination unit->

Initial coordinates of (a)

Can be derived by equation (7);

(7)

further, the step 4 specifically includes:

Further, the layout problem is expressed as

wherein ,

is the horizontal coordinate vector of all units, +.>

Is an identity matrix>

Is each element

Vector of->

Only two non-zero elements-1 and 1 in each row, < >>

The number of columns of (a) is the number of units, vector +.>

Each element of the matrix>

Further, the linear complementary problem data structure is compressed through a two-step scanning strategy to construct a corresponding constraint matrix

The method comprises the following steps:

In practice, after initialization of the integrated unit, the integrated unit and unpaired unit will undergo a unit relocation by solving the layout problem described in equation (4). To reduce circuit performance degradation after cell repositioning, the displacement between the cell and the initial coordinates is taken into account during cell repositioning. The displacement driven cell movement problem is modeled as a Linear Complementary Problem (LCP). Given that all cells include integrated cell and unpaired cell information, and the connection relationship netlist between them, an LCP data structure can be constructed. After data construction, a modulo-based matrix split iterative method (MMSIM) may be applied to solve the LCP problem. Finally, we obtain the repositioned cell coordinates based on the MMSIM result.

The objective function in equation (4) can be modeled as LCP and solved by MMSIM. The MMSIM iterative process is shown in equation (8), in which the horizontal coordinates of the cell are stored in a vector

Is a kind of medium. Vector->

Can pass vector->

And (5) calculating. For each iteration->

Based on vector->

Vectors +.>

. The MMSIM process is iterated a plurality of times until

Finishing the process; />

(8)

wherein ,

is the number of iterations, vector->

、

Sum matrix->

、

and

The calculation of (2) is given by equation (9). Wherein (1)>

、

and

Appears in equation (4), matrix +.>

Split into +.>

，

Is a matrix->

Schur complement->

Is a tri-diagonal approximation of (c).

and

Are all normal numbers, set to 0.5 in our implementation. The former work gives the data construction and proving process of MMSIM;

(9)

after solving for LCP, we need to align the cell with the nearest legal position because the calculated coordinates are of the continuous floating point type. The sub-units within the integrated unit also need to be restored and laid out in horizontally adjacent positions. Since in equation (4) the right boundary constraint of the line is relaxed, if in the MMSIM result, cell overlap occurs or the unit position exceeds the right boundary of the line, the position of these cells is illegal. Since in practice the number of illegal units is very small, we can directly find the nearest legal location to lay out it.

Each iteration in solving LCP by using MMSIM, as shown in equation (8)

All need to be utilized

Is determined by the inverse matrix of +.>

. According to formula (9) because +.>

Is a sparse matrix, wherein: (1) Matrix->

Is a diagonal matrix, (2) matrix->

Only two non-zero elements per row, namely-1 and 1, (3) matrix +.>

Is a tri-diagonal matrix, so M can be determined to be a sparse matrix. Likewise, a +>

Is also a sparse matrix, ">

The gaussian elimination calculation may be used,but->

It may not be a sparse matrix, and the number of non-zero elements may be large. If->

Rather than a sparse matrix, it will greatly impact the scalability of storage and computation.

FIG. 8 shows an example, six cells in a row

Obtaining a vector according to the initial coordinates of the cell>

. The adjacent relation is as follows:

. Corresponding vectors according to the adjacent relation order

FIG. 8 (a) shows the corresponding matrix +.>

, and

. Based on matrix->

and

We can obtain a matrix

And calculates its inverse matrix +.>

. However, matrix +.>

Not sparse momentAn array. />

The present embodiment gives a construction matrix

Can ensure +.>

Becoming a sparse matrix. The method mainly examines matrix- >

Sub-matrix->

And (5) constructing. In order to make a tri-diagonal matrix

Becomes a diagonal matrix, matrix->

The construction method should be modified.

Due to

Only two non-zero elements, namely 1 and-1, and +.>

Let->

Is->

Is>

Lines, we have ∈ ->

，

. In order to make->

Is a diagonal matrix>

and

Should be 0. Wherein for->

If go->

The position and row of non-zero elements in (1)>

If the positions in (a) are different, we get +.>

. Similarly, if line->

Locations and rows of non-zero elements in (3)

If the positions in (a) are different, we get +.>

. If->

，

Three diagonal moments->

Will degrade into a diagonal matrix. Therefore, in constructing matrix B, we need to ensure each +.>

and

、

Has different positions.

FIG. 8 shows an example to illustrate

Is a construction process of (1). As shown in fig. 8 (a), we give the adjacent cell constraint in order:

. In order to make->

For sparse matrix, i.e. each +.>

and

、

Should have different positions, we are constructing +.>

The order of adjacent cells is changed:

. Since the adjacency relation is unchanged, the cell adjacency constraint is not changed. Corresponding vectors according to the adjacent relation order

Corresponding matrix- >

Sum matrix->

As shown in fig. 8 (b). It can be seen that the tri-diagonal matrix +.>

Degenerate into diagonal matrices. Thus, compared to FIG. 8 (a), we have +.>

Is a sparse matrix. To distinguish from the sequential scanning strategy in fig. 8 (a), we refer to the matrix construction method in fig. 8 (b) as a two-step scanning strategy.

The two unit scan strategies are summarized as follows:

sequential scanning: hypothesis unit

In units->

Left side of (2)>

Is the right adjacent unit, i.e.)>

. In general, we can scan the rows of cells from left to right by default and individually as a matrix +.>

Every pair of adjacent units->

Constraints are added.

Two-step scanning: when scanning cells in a row from left to right, we first combine the odd-positioned cells with their right neighbors into an adjacency constraint. After the first scan, we begin the second scan, adding the neighbor constraint of the cell with its right neighbor at even locations.

Through a two-step scanning strategy, the method can effectively reduce

From the complexity of (a)And the algorithm expandability is improved. Under our two-step scanning strategy, the number of non-zero elements per row is 3; while the number of non-zero elements per row is proportional to the number of cells per row RowCC under the sequential scanning strategy. Therefore, the matrix compression ratio CompRatio under the two-step scanning strategy is shown in equation (10). The larger the circuit scale, the more cells are laid out per row, and the higher the compression ratio. Experiments show that the maximum difference of the results of the two scanning strategies is smaller than +. >

. Since the layout coordinates need to be rounded to integers, the difference between these two scanning strategies is negligible, meaning that our two-step scanning strategy can provide lossless data compression during cell repositioning;

(10)

resolution of LCP using MMSIM, each iteration

Is +.>

. This is because all matrices in equations (8) and (9), i.e. +.>

、

、

、

and

Are all provided with->

Sparse moment of each non-zero elementAll complexity of the matrix, matrix vector multiplication, matrix addition/subtraction and vector operations is +.>

. Furthermore, under a two-step scanning strategy, +.>

The computational complexity is also +.>

. Finally, experiments show that the MMSIM iteration times of all test cases are about 1000-2000 times.

Step 5, under the condition of considering the quenching unit pairs, further optimizing the line length by using preset operations, wherein the preset operations comprise unit exchange operations and unit insertion operations, and finally generating an optimized layout result;

in practice, after cell repositioning, cell swapping, insertion, etc. may be used to further optimize the line length HPWL while ensuring that the pair of quench cells that have been created do not separate, thereby yielding initial layout results. After the initial layout result is obtained, whether the line length in the initial layout result is converged or not can be judged, if so, an optimized layout result is generated, and if not, the step 4 is returned to perform optimization again.

According to the soft error layout optimization method considering pulse narrowing, the soft error rate is optimized by considering quenching effect enhancement during layout, soft error generation in a circuit can be lightened under the condition that no hardware penalty is introduced, the layout algorithm is set to dynamically pair units during layout, all units are globally paired at one time, and in the subsequent unit relocation process, the units are globally relocated, so that quenching effect among adjacent logic related units is enhanced, and optimization efficiency and quenching effect enhancement performance are improved.

The present solution will be described in connection with an embodiment in which the detailed layout method can be implemented using c++, the compilation tool is g++4.4.7, and the program runs on a Linux workstation using 2.20GHz Intel Xeon CPU and 32GB RAM, using a single CPU core. We used ISCAS-85 test cases for layout performance evaluation. The RTL code of ISCAS-85 test case is input, based on 65nm cell library, synopsys Design Compiler is adopted for logic synthesis, wherein the cell library only uses three cell types of INV, NAND and NOR. The synthesized netlist is then used to generate an initial layout using a cancer Innovus tool. We employ a Mixed Mode Analysis Tool (MMAT) for evaluating SER performance. Table 1 gives ISCAS-85 test case information;

The SER is evaluated using an MMAT tool. The tool adopts a device in a 65nm double-well process unit library, a grid-based 3D TCAD simulation method is used for obtaining the SET pulse width of ion impact, and a 3D TCAD model is finally calibrated to match an SPICEI-V curve;

table 2 lists the simulated configurations. For each test case we simulated 10000 random excitation vectors. For each random stimulus vector, the behavior of the netlist is simulated using a Verilog simulator, injecting transient pulses into the logic gates. The propagation of the pulse is then simulated by the MMAT. Finally, the transient pulse width and its distribution are captured at each output of the circuit. The output of the MMAT includes SER and transient pulse width distribution.

To quantitatively measure soft error sensitivity in a combined circuit, we have used soft error sensitivity factor (SEVF) for research. For each unit

It->

The calculation is shown in formula (11);

(11)/>

wherein

Is the number of analog input vectors, +.>

Is when->

When the drain region of (2) is hit +.>

At the input vector

Probability of generating SET pulse down, +.>

Is the SET pulse at the input vector +.>

Probability of propagating down to the circuit output.

Entire circuit

Can be achieved by applying to all +.>

The sum is obtained as shown in formula (12);

(12)

Table 3 compares the input layout and the optimized performance of our working our in pulse narrowing effect and SER. The circumamsevf column shows the soft error estimate of the circuit, the quench cell number column shows the number of cells in the quench cell pair, the pulse narrowing event number column shows the number of occurrences of the pulse narrowing effect during simulation using 10000 random excitation vectors, and CPU(s) is run time in seconds. It can be seen that the circutsevf average of our method was reduced by 29.66% with a greater optimization of both quench unit count and pulse narrowing event count. The runtime of the our is less than 0.2 seconds for all test cases. Wherein the runtime overhead comes primarily from the LCP solution process.

Table 4 lists the line length HPWL and the average displacement after layout optimization taking into account pulse narrowing by the our method. To further investigate the cause of the increase in HPWL during layout optimization considering pulse narrowing, we show the average Manhattan distance between the cells and their fan-outs in the initial average connection distance column. As shown in Table 4, the initial average connection distance for all test cases is generally large, with an average value of 33.50. Therefore, when the mobile unit is required to generate the quenched unit pairs, a larger unit displacement is brought about.

Taking the maximum scale circuit C7552 in ISCAS85 as an example, fig. 9 shows an example of a cell layout that takes into account the effect of pulse narrowing. It can be found that in the input initial layout result of fig. 9 (a), only a few random quench unit pairs are distributed, and fig. 9 (b) is the result of the our method, and the number of quench unit pairs is significantly increased after optimization by the pulse narrowing effect. It should be noted that, since the quenching unit pairs need to be horizontally adjacent, the more the number of quenching unit pairs is compared with the input layout, the more the layout distribution will be compact;

to further investigate the impact of pulse narrowing enhancement methods on the design, we performed a routing process on the layout results and then reported the circuit timing and power information via PrimeTime (PT). Experiments have found that the layout of the Ours is free of wiring congestion. In addition, from the PT report, we observe that the timing impact of all test cases is less than 1ps, the power impact is 0 μW, in other words, the timing and power loss after pulse narrowing enhancement are negligible in all test cases. The main reason we analyze this result is that the timing variation is small due to the relatively small chip size of the design, such as the maximum test case C7552 of 68.30 x 68.75 μm, and the generally short wire length. In a more general case, because cell displacement is considered in our LCP method, it is guaranteed that the timing path variation is within a reasonably small range.

Table 5 lists the corresponding soft error numbers for the four pulse width ranges, namely pulse widths [ 0-100 ps ], [100 ps-200 ps ], [2000 ps-300 ps ], and [300 ps-400 ps ]. On average, our method can reduce the number of soft errors by about 19.63% -54.17% over these pulse width ranges;

finally, because of the small ISCAS85 size, we used the largest four test circuits from the EPFL combinational logic circuit, with a maximum of hyptense, with over 2.7×e5 cells and nets for scalability analysis. The selected EPFL test case information is shown in table 6;

no commercial tool can directly consider the pulse narrowing effect to analyze SER at present, and since the analysis scale of the existing MMAT tool is very limited, we mainly consider the number of quenching units in order to evaluate the pulse narrowing effect optimization result of our detailed layout method on EPFL circuit. From the foregoing Table 3, it can be observed that the greater the number of quenching units, the more beneficial the pulse narrowing effect can be to help reduce the SER. Therefore, for EPFL circuits, we measure the effect of pulse narrowing primarily in terms of the number of quench cells.

As shown in table 7, our method increases the number of quenching cells by a factor of 0.71 over the input initial layout on all EPFL circuits. The increase ratio of quench units on the EPFL circuit was comparable to the results on the ISCAS85 circuit (as shown in table 3). Furthermore, our average increase in HPWL was only 8.91% with less impact than the ISCAS85 circuit shown in table 4. Referring to Table 3, we have also found that while the EPFL circuit scale is 10-100 times larger than the ISCAS85 circuit scale, the average displacement of the EPFL is generally smaller. In addition, our runtime increases substantially linearly with increasing circuit scale, with approximately 46.60% of the runtime being used to address LCP during cell relocation. Therefore, it can be concluded that our method has better scalability;

By optimizing SER in view of pulse narrowing enhancement at layout time, soft error generation in the circuit can be mitigated without introducing any hardware penalty. To reduce soft errors in a combined circuit using pulse narrowing effect we propose a detailed layout algorithm that can enhance the pulse narrowing effect between adjacent logically related cells. In our approach, the pulse narrowing effect enhancement is globally optimized and cell displacement minimization is considered. Simulation results show that the number of quenching unit pairs can be greatly increased by using the method, and the soft error sensitivity of the circuit is reduced by 25.99 percent on average. In addition, for large-scale test circuits, the pulse narrowing effect of our method enhances performance stability, and the displacement is smaller, and the run time increases linearly with scale, thus proving the scalability of our method.

The units involved in the embodiments of the present invention may be implemented in software or in hardware.

It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.

Claims

1. A soft error layout optimization method that accounts for pulse narrowing, comprising:

2. The method according to claim 1, wherein the step 2 specifically comprises:

3. The method according to claim 2, wherein the step 2.2 specifically comprises:

is provided with

and

Units->

And fan-out unit->

Is used for calculating the input coordinates of the (a) and (b) of the (b)>

And fan-out unit->

Pairing weights of (a);

constructing a connection graph

, wherein

Representing a set of fan-in units,/->

Representing a set of fan-out units>

Representing a connection set;

4. The method of claim 3, wherein the formula for calculating the pairing weight is

，

wherein ,

indicating sensitivity, & gt>

and

Are positive parameters.

5. A method according to claim 3, wherein said step 3 comprises:

And rewrites the layout problem according to preset conditions;

inferring initial information of the combined unit, for the integrated unit

The width and initial coordinates are calculated as follows: />

wherein ,

and

Respectively represent->

，

and

Respectively indicate->

And the initial lower left corner coordinates.

6. The method according to claim 4, wherein the step 4 specifically includes:

7. The method of claim 5, wherein the layout problem is expressed as

wherein ,

is the horizontal coordinate vector of all units, +.>

Is an identity matrix>

Is per element->

Vector of->

Only two non-zero elements-1 and 1 in each row, < >>

The number of columns of (a) is the number of units, vector +. >

Each element of the matrix>

8. The method of claim 6, wherein the compressing the linear complementary problem data structure by a two-step scanning strategy constructs its corresponding constraint matrix

The method comprises the following steps: