CN116070573A - Soft error layout optimization method considering pulse narrowing - Google Patents

Abstract

An embodiment of the present invention provides a soft error layout optimization method considering pulse narrowing, which belongs to the field of data processing technology, and specifically includes: step 1, performing logic synthesis on the preset RTL design and using a layout tool to generate an input layout; step 2. Use the KM algorithm to globally find all possible cell pairs in the input layout, and obtain cell pairing results; step 3, generate combined cells according to the cell pairing results, and calculate the initial position and size of the combined cells according to the original cell information; step 4, Based on the initial positions of all units, calculate the unit relocation considering the displacement, and obtain the quenching unit pair that satisfies the quenching effect; step 5, in the case of considering the quenching unit pair, use the preset operation to further optimize the line length, where the preset The design operation includes cell exchange operation and cell insertion operation, and finally generates an optimized layout result. Through the scheme of the present invention, the optimization efficiency and quenching effect enhancement performance are improved.

Description

Soft Error Layout Optimization Method Considering Pulse Narrowing

Technical Field

The embodiments of the present invention relate to the field of data processing technology, and in particular to a soft error layout optimization method considering pulse narrowing.

Background Art

As feature sizes continue to shrink, modern CMOS devices and integrated circuits (ICs) are becoming more susceptible to soft errors due to smaller capacitance and lower operating voltages. Soft errors can be caused by a variety of reasons, such as alpha particles from package decay, secondary particles from cosmic rays, crosstalk, and random noise in the circuit, among which radiation-induced single event transient pulse (SET) effects are the main cause of soft errors. SET is a transient pulse caused by a single ionized particle passing through a sensitive area in the device to generate "accumulated charge". SET is a serious reliability issue for ICs because it can cause faults and soft errors in the circuit and even cause device damage.

However, in existing layout optimization methods, such as previous work Chang Liu, Xu He, Bin Liang, andYang Guo. 2018. Detailed placement for pulse quenching enhancement in anti-radiation combinational circuit design. Integration, VLSI 62 (2018), 182–189., the pulse narrowing effect enhancement is limited because the unit movement process is performed one by one without a global perspective.

It can be seen that there is an urgent need for an efficient soft error layout optimization method that takes pulse narrowing into consideration and has stable quenching effect enhancement performance.

Summary of the invention

In view of this, an embodiment of the present invention provides a soft error layout optimization method considering pulse narrowing, which at least partially solves the problem of poor optimization efficiency and quenching effect enhancement performance in the prior art.

An embodiment of the present invention provides a soft error layout optimization method considering pulse narrowing, including:

Step 1, perform logic synthesis on the preset RTL design and use layout tools to generate input layout;

Step 2, use the KM algorithm to globally find all possible unit pairs in the input layout and obtain the unit pairing results;

Step 3, generating a combined unit according to the unit pairing result, and calculating the initial position and size of the combined unit according to the original unit information;

Step 4, based on the initial positions of all units, calculate the unit relocation considering the displacement to obtain the quenching unit pair that satisfies the quenching effect;

Step 5, taking into account the quenching unit pair, further optimize the line length using preset operations, wherein the preset operations include a unit exchange operation and a unit insertion operation, and finally generate an optimized layout result.

According to a specific implementation of the embodiment of the present invention, step 2 specifically includes:

Step 2.1, generate the fan-out set corresponding to each unit and calculate the sensitivity of each unit;

In step 2.2, the KM algorithm is used to pair each unit with the unit with the highest sensitivity in its corresponding fan-out set to form a unit pairing result.

According to a specific implementation of the embodiment of the present invention, step 2.2 specifically includes:

和

分别为单元

和其扇出单元

的输入坐标，并计算单元

和其扇出单元

的配对权值；set up

and

Unit

and its fan-out unit

The input coordinates and calculate the unit

and its fan-out unit

The pairing weight of

，其中

表示扇入单元的集合，

表示扇出单元的集合，

表示连接集；Building a connection graph

,in

represents the set of fan-in units,

represents the set of fan-out units,

Represents a connection set;

The KM algorithm is called to perform global unit pairing on the connection graph to form a unit pairing result.

According to a specific implementation of the embodiment of the present invention, the calculation formula of the pairing weight is:

表示敏感度，

和

均为正参数。in,

Indicates sensitivity,

and

are all positive parameters.

According to a specific implementation of the embodiment of the present invention, step 3 specifically includes:

Based on the existing original unit information and displacement driven problem, it can be described as

and rewrite it as a layout problem based on the preset conditions;

，其宽度和初始坐标计算如下：The initial information of the reasoning combination unit, for the integrated unit

, whose width and initial coordinates are calculated as follows:

其中，

和

,分别表示

单元的宽度和初始左下角坐标，相应地，对于子单元

，

和

分别表示

的宽度和初始左下角坐标。

in,

and

, respectively

The width and initial lower left corner coordinate of the cell, and accordingly, for the child cells

,

and

Respectively

The width and initial lower left corner coordinates.

According to a specific implementation of the embodiment of the present invention, step 4 specifically includes:

Step 4.1, relocate the combined cells and the unpaired cells by using the formula corresponding to the layout problem, model the linear complementarity problem, and construct the linear complementarity problem data structure by giving the cell information and connection relationship netlist of the combined cells and the unpaired cells;

Step 4.2, compressing the linear complementarity problem data structure through a two-step scanning strategy to construct its corresponding constraint matrix, and applying the module-based matrix splitting iteration method to solve the linear complementarity problem;

Step 4.3, according to the solution result, the relocated unit coordinates are obtained, and they are integerized to obtain the legal positions of all units including the combined unit, and the original adjacent unit pairs in the successfully laid out combined unit are used as quenched unit pairs.

According to a specific implementation of an embodiment of the present invention, the expression of the layout problem is:

是所有单元水平方向坐标向量，

是单位矩阵，

是每个元素

的向量，

是单元左右水平相邻关系的约束矩阵，

中每行中只有两个非零元素-1和1，

的行数是单元水平方向的左右约束数目，

的列数是单元数，向量

中每个元素对应矩阵

每行左右水平相邻约束中左边单元的宽度。in,

is the horizontal coordinate vector of all units,

is the identity matrix,

Each element

The vector of

is the constraint matrix of the horizontal adjacent relationship of the unit.

There are only two non-zero elements in each row of

The number of rows is the number of left and right constraints in the horizontal direction of the cell.

The number of columns is the number of cells, and the vector

Each element in the matrix

The width of the left cell in the horizontal adjacent constraints on each row.

的步骤包括：According to a specific implementation of an embodiment of the present invention, the linear complementarity problem data structure is compressed by a two-step scanning strategy to construct its corresponding constraint matrix.

The steps include:

When scanning cells in a row from left to right, first form neighbor constraints between cells in odd positions and their right adjacent cells;

After the first scan, the second scan begins, adding neighbor constraints between the cell and its right neighbor at even positions.

The soft error layout optimization scheme considering pulse narrowing in the embodiment of the present invention includes: step 1, performing logic synthesis on a preset RTL design and using a layout tool to generate an input layout; step 2, using a KM algorithm to globally find all possible cell pairs in the input layout to obtain a cell pairing result; step 3, generating a combination cell according to the cell pairing result, and calculating the initial position and size of the combination cell according to the original cell information; step 4, based on the initial positions of all cells, calculating the cell relocation considering the displacement to obtain a quenching cell pair that satisfies the quenching effect; step 5, taking the quenching cell pair into consideration, further optimizing the line length using a preset operation, wherein the preset operation includes a cell exchange operation and a cell insertion operation, and finally generating an optimized layout result.

The beneficial effects of the embodiments of the present invention are as follows: through the scheme of the present invention, the quenching effect enhancement is considered during layout to optimize the soft error rate, and the soft error generation in the circuit can be reduced without introducing any hardware penalty. By setting the layout algorithm to dynamically pair cells during layout, all cells are then globally paired at one time, and in the subsequent cell relocation process, they are globally relocated, thereby enhancing the quenching effect between adjacent logically related cells, and improving the optimization efficiency and the quenching effect enhancement performance.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

FIG1 is a schematic flow chart of a method for optimizing soft error placement taking pulse narrowing into consideration provided by an embodiment of the present invention;

FIG2 is a schematic diagram of a detailed layout framework and an evaluation flow chart corresponding to a soft error layout optimization method considering pulse narrowing provided by an embodiment of the present invention;

FIG3 is a schematic diagram showing an example of a quenching effect provided by an embodiment of the present invention;

FIG4 is a schematic diagram of an example of unit pairing provided by an embodiment of the present invention;

FIG5 is a schematic diagram of a combination unit provided by an embodiment of the present invention that is combined end to end;

FIG6 is a schematic diagram of a unit relocation process provided by an embodiment of the present invention;

FIG7 is a schematic diagram of a process of merging paired units into a combined unit provided by an embodiment of the present invention;

的两种扫描构建方法示意图；FIG. 8 is a matrix provided by an embodiment of the present invention.

Schematic diagram of two scanning construction methods;

FIG. 9 is a schematic diagram of a layout example taking into account the quenching effect provided by an embodiment of the present invention.

DETAILED DESCRIPTION

The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work belong to the scope of protection of the present invention.

It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and/or function described herein is merely illustrative. Based on the present invention, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and/or practice the method. In addition, other structures and/or functionalities other than one or more of the aspects described herein can be used to implement this device and/or practice this method.

It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention. The drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, one skilled in the art will appreciate that the aspects described may be practiced without these specific details.

An embodiment of the present invention provides a soft error layout optimization method considering pulse narrowing, and the method can be applied to a layout optimization process in a chip design scenario.

Referring to FIG1 , a flow chart of a method for optimizing soft error placement considering pulse narrowing is provided in an embodiment of the present invention. As shown in FIG1 and FIG2 , the method mainly includes the following steps:

Step 1, perform logic synthesis on the preset RTL design and use the layout tool to generate input layout;

和

都是反相器，它们的输出节点分别命名为

和

。最初，假设

的输入为高，

的PMOS为OFF，

为LOW，与

相关联的PMOS晶体管为ON。The soft error rate (SER) can be optimized at different levels from software to hardware. Among them, the layout optimization method of SER is mainly to reduce the probability of SET reaching the final output end by using the pulse narrowing effect, that is, the quenching effect, in the SET propagation path. Compared with other soft error rate optimization methods, by using layout to enhance the pulse narrowing effect, while optimizing SER, no chip area cost or wafer process adjustment is required.

and

are all inverters, and their output nodes are named

and

Initially, it is assumed that

The input is high,

The PMOS is OFF,

is LOW, and

The associated PMOS transistor is ON.

的截止PMOS晶体管，则

处的逻辑低状态将被电荷收集驱动为高，然后在

处产生置位脉冲高。该SET脉冲将传播到

，导致

处的HIGH到LOW转变，

的PMOS状态变为OFF。As shown in Figure 3, (a) indicates that if the ion hits

The PMOS transistor is turned off, then

The logic low state at

The SET pulse will propagate to

,lead to

HIGH to LOW transition at

The PMOS state becomes OFF.

的PMOS关闭时，它对电荷收集敏感。如果

和

在物理上彼此接近，因为电荷共享可以使SET电荷从

扩散到

，

的PMOS将返回ON，从而将

的状态再次驱动到HIGH。在

处的LOW-to-HIGH转变将节点电压重置为事件前状态。(b) indicates when

When the PMOS is turned off, it is sensitive to charge collection.

and

Being physically close to each other, charge sharing can enable the SET charge to

Spread to

,

The PMOS will turn ON, thus

is driven HIGH again.

The LOW-to-HIGH transition at resets the node voltage to its pre-event state.

处的脉冲被有效地截短，使得

处只具有非常窄的脉冲宽度，即产生了淬灭效应。相比长脉冲可以不衰减地传播到逻辑深处，

处的窄脉冲很可能通过后续路径上被逻辑门被进一步衰减甚至过滤掉，或者由于时钟周期更长而不被锁存。因此，

和

可以配对来增强淬灭效应。(c) indicates

The pulse at is effectively truncated, making

The pulse width is very narrow, which results in a quenching effect. Compared with the long pulse, which can propagate deep into the logic without attenuation,

The narrow pulse at is likely to be further attenuated or even filtered out by the logic gates in the subsequent path, or not latched due to the longer clock cycle.

and

Can be paired to enhance the quenching effect.

It should be pointed out that there are three conditions for the pulse narrowing effect to occur: the circuit structure is connected, the layout position is adjacent, and it is in a suitable level state. During the layout process, the netlist structure remains unchanged, that is, the unit connection relationship does not change. The level state of each unit is related to the input stimulus, and what can be controlled is the position of the unit on the layout. Therefore, the focus of this article is on the position relationship of the electrically connected units. Two units that are connected in the circuit and located in the same row and adjacent in the layout are defined as quenching unit pairs. Only quenching unit pairs can produce pulse narrowing effects.

Since the shrinkage of SET pulse width is highly dependent on the physical distance between electrically related units. If the distance is too large, the pulse narrowing effect disappears. In order to maximize the pulse narrowing effect, the two units of the same quenching unit pair should be horizontally close to each other. It is worth adding that the vertical adjacent situation is not considered in the pulse narrowing enhancement, because the well/substrate contact area between the layout rows affects the charge transfer, which will significantly weaken the pulse narrowing effect.

Considering that the cells in the quenching cell pair need to be laid out horizontally adjacent to each other, the global layout cannot determine the final position of the cells, so our algorithm works on the detailed layout.

布局问题。设标准单元

和线网

，

，

。对于每个单元

，其坐标为

，宽度为

。在本工作中，每个单元具有统一的高度，等于布局行的高度。给定宽度为

、高度

H的布局区域

，每个可移动单元

的坐标

)需要满足如下要求：The detailed layout problem of pulse narrowing enhancement can be expressed as a hypergraph

Layout problem. Set standard unit

And line network

,

,

For each unit

, whose coordinates are

, the width is

In this work, each cell has a uniform height, equal to the height of the layout row. Given a width of

,high

H layout area

, each movable unit

Coordinates

) must meet the following requirements:

内；Located in a legal area

Inside;

No overlap with other circuit units;

Layout is within a cell row.

被定义为淬灭单元对，当且仅当

，并且

和

是水平相邻的。Definition 1: In our work, the unit pair

is defined as a quenching unit pair if and only if

,and

and

are horizontally adjacent.

According to the above analysis, the basis for the pulse narrowing effect is the existence of quenching unit pairs, and the distance between the quenching unit pairs determines the strength of the pulse narrowing effect. The detailed layout optimizes the SER by generating as many quenching unit pairs as possible. Since the two units in each quenching unit pair need to be arranged horizontally adjacent to each other, in order to avoid affecting the circuit performance too much, we also consider the layout displacement when moving the unit. Therefore, the purpose of our detailed layout is to maximize the number of quenching unit pairs while minimizing the unit displacement.

In specific implementation, the three cell types of INV, NAND and NOR in the 65nm cell library can be used to build the circuit. In order to obtain the input layout, given the Register Transfer Level (RTL) design, the Synopsys Design Compiler tool is first used for logic synthesis, and then the Cadance Innovus tool generates the layout.

Step 2, use the KM algorithm to globally find all possible unit pairs in the input layout and obtain the unit pairing results;

Furthermore, the step 2 specifically includes:

Step 2.1, generate the fan-out set corresponding to each unit and calculate the sensitivity of each unit;

In step 2.2, the KM algorithm is used to pair each unit with the unit with the highest sensitivity in its corresponding fan-out set to form a unit pairing result.

Furthermore, the step 2.2 specifically includes:

和

分别为单元

和其扇出单元

的输入坐标，并计算单元

和其扇出单元

的配对权值；set up

and

Unit

and its fan-out unit

The input coordinates and calculate the unit

and its fan-out unit

The pairing weight of

，其中

表示扇入单元的集合，

表示扇出单元的集合，

表示连接集；Building a connection graph

,in

represents the set of fan-in units,

represents the set of fan-out units,

Represents a connection set;

The KM algorithm is called to perform global unit pairing on the connection graph to form a unit pairing result.

Furthermore, the calculation formula of the pairing weight is:

表示敏感度，

和

均为正参数。in,

Indicates sensitivity,

and

are all positive parameters.

，

表示其扇出集合。我们需要选择最佳单元

，并将

和

放在一起以最终生成单元对。在选择候选

时，将考虑两个因素：In specific implementation, for each unit

,

represents its fan-out set. We need to select the best unit

, and

and

Put together to finally generate a unit pair.

Two factors will be considered:

Cell sensitivity: The sensitivity of a cell to SET after being hit by a single ion. The higher the sensitivity, the higher the priority of the cell that needs to be shielded from SET.

Distance: The original distance between two units. To reduce displacement when combining pairs of units, their original distance should be within a certain range threshold.

，其敏感度

由公式(1)计算。

（1）The sensitivity concept can be used to evaluate the radiation resistance performance of each unit.

, its sensitivity

Calculated by formula (1).

(1)

表示单元

的输出值为LOW的概率。如上文所述，处于OFF状态的单元的PMOS晶体管对节点电荷收集特别敏感。因此，如果

的值较大，则

容易产生SET

是

处的SET脉冲传播到电路终端的概率。如果

很高，则说明

很容易产生瞬态脉冲，并可能导致软错误。因此，

接下来的单元重定位过程中，配对单元将水平移动使其彼此靠近，最终形成淬灭单元对。我们方法会同时对所有单元进行配对，使得尽可能多地产生潜在的脉冲窄化效应。in

Representation unit

The probability that the output value is LOW. As mentioned above, the PMOS transistor of the cell in the OFF state is particularly sensitive to node charge collection. Therefore, if

If the value of is large,

Easy to generate SET

yes

The probability that a SET pulse at t will propagate to the circuit terminals.

Very high, it means

Transient pulses are easily generated and may cause soft errors.

In the subsequent unit repositioning process, the paired units will move horizontally to make them close to each other, eventually forming a quenched unit pair. Our method pairs all units simultaneously to maximize the potential pulse narrowing effect.

只有一个扇出

，

也只有一个扇入

，我们可以直接将

和

配对，并在后续单元重定位过程中，将它们彼此水平靠近。当具有多个扇出或扇入单元的情况下，选择具有最高SET敏感度的扇出或扇入进行配对。例如，在图4中，单元

有两个扇入单元，即

和

，但只有一个扇入可以与

配对，原则上是选择SET脉冲传播到终端概率较高的单元。Figure 4 shows an example of unit pairing, where (a) represents the unit connection relationship and (b) represents the unit pairing process.

Only one fan-out

,

There is only one fan-in

, we can directly

and

Pair them and move them horizontally closer to each other during subsequent cell relocation. When there are multiple fan-out or fan-in cells, the fan-out or fan-in with the highest SET sensitivity is selected for pairing. For example, in Figure 4, the cell

There are two fan-in units, namely

and

, but only one fan-in can be

Pairing, in principle, is to select cells with a higher probability of SET pulses propagating to the terminal.

Since the two paired cells need to be laid out together during the cell relocation process, we should also consider the cell distance when pairing the cells. Otherwise, it will cause excessive displacement during the subsequent cell relocation, affecting circuit performance such as line length.

和

分别为

和

的输入坐标。我们使用

来计算

与其扇出

的配对权值。如公式(2)所示，具有高敏感度和距

较小距离的扇出

，会优选与

配对。公式(2)中的

和

均为正参数，在我们的实验中，

设置为仿真时输入向量的数目，

；Here, we describe the weight calculation when pairing units.

and

They are

and

We use

To calculate

Instead of fanning out

As shown in formula (2), it has high sensitivity and distance

Fan-out at smaller distances

, will prefer

Pairing. In formula (2)

and

are all positive parameters. In our experiments,

Set to the number of input vectors during simulation,

;

（2）

(2)

，其中

表示扇入单元的集合，

表示扇出单元的集合。给定单元

，每个

都存在一条边

。边

上的权重等于

。图4(b)给出了与图4(a)所示网表对应的连接图

的示例及配对结果。扇入单元集合

，扇出单元集合

。连接集

。当建立连接图

时，将调用KM算法来解决单元配对问题。图4(b)显示了配对结果，即

和

。The (Kuhn-Munkres) KM algorithm can be used for global pairing of units. First, we construct the connection graph

,in

represents the set of fan-in units,

Represents a collection of fan-out cells. Given a cell

, each

There is an edge

.side

The weight on is equal to

Figure 4(b) shows the connection diagram corresponding to the netlist shown in Figure 4(a)

Examples and matching results of Fan-In Unit Collection

, fan-out unit set

. Connection Set

When establishing a connection diagram

When , the KM algorithm will be called to solve the unit pairing problem. Figure 4(b) shows the pairing result, i.e.

and

.

，其中

，而

。为了减少运行时间，我们限制

，即

。如果单元数超过

，KM将被再次调用，直到单元配对全部完成。The computational complexity of the KM pairing algorithm is

,in

,and

To reduce the running time, we limit

,Right now

If the number of units exceeds

, KM will be called again until all unit pairings are completed.

可最多会被配对两次，如作为配对中的驱动单元，或作为配对中的扇出单元。如图5所示，

被配对两次，一次作为

的扇出，一次为

的驱动。在我们的配对方法中，如果一个单元被配对两次，即一次作为驱动，一次作为扇出，则这两对可以合并为一个组合。图5给出了一个示例，配对结果

，

可以合并为一个组合

，同时，在一个单元被配对两次时，可以设定距离阈值，然后根据单元间的阈值选择更合适的单元进行配对。In the KM pairing results, each unit

It can be paired up to twice, such as as a driver unit in a pair, or as a fan-out unit in a pair. As shown in Figure 5,

Paired twice, once as

The fan-out is

In our pairing method, if a cell is paired twice, once as a driver and once as a fan-out, the two pairs can be merged into one combination. Figure 5 shows an example of the pairing result.

,

Can be combined into a combination

,At the same time, when a unit is paired twice, a distance threshold can be set, and then a more appropriate unit can be selected for pairing based on the threshold between units.

Step 3, generating a combined unit according to the unit pairing result, and calculating the initial position and size of the combined unit according to the original unit information;

Based on the above embodiment, step 3 specifically includes:

Based on the existing original unit information and displacement driven problem, it can be described as

and rewrite it as a layout problem based on the preset conditions;

，其宽度和初始坐标计算如下：The initial information of the reasoning combination unit, for the integrated unit

, whose width and initial coordinates are calculated as follows:

其中，

和

,分别表示

单元的宽度和初始左下角坐标，相应地，对于子单元

，

和

分别表示

的宽度和初始左下角坐标。

in,

and

, respectively

The width and initial lower left corner coordinate of the cell, and accordingly, for the child cells

,

and

Respectively

The width and initial lower left corner coordinates.

，其中每个单元具有宽度

和统一高度，单元重定位问题可以用公式(3)表示；In the specific implementation, based on the cell pairing results, we reposition the cells to finally generate quenching pairs to achieve enhanced pulse narrowing effect. The cell repositioning process is shown in Figure 6. In order to reduce the performance impact caused by moving cell pairs, the goal of the cell repositioning process is set to minimize displacement. Given a chip layout area and a standard cell set

, where each cell has width

and uniform height, the unit relocation problem can be expressed by formula (3);

（3）

(3)

和

分别是单元

的原始左下角坐标和重定位后左下角坐标。每个单元

与行

对齐，即

，

是第

行的底部

坐标。行中的单元按其

坐标排序，即如果单元

位于

的右侧，则

。所有单元必须布局在芯片区域内，即，对于行

中的单元，其

坐标不能超过

，即行

的右边界。in,

and

The units are

The original lower left corner coordinates and the lower left corner coordinates after relocation. Each unit

With line

Alignment, i.e.

,

It is

Bottom of the row

Coordinates. The cells in a row are grouped by their

Coordinate sorting, that is, if the unit

lie in

On the right side,

All cells must be placed within the chip area, i.e., for rows

The unit in

Coordinates cannot exceed

, that is

right border of .

，

。如果进一步暂时放宽对单元超出其所在行右边界的约束，则公式(3)可以重写为公式(4)；In the implementation, it is assumed that each cell is directly aligned with its original row, i.e.

,

If we further temporarily relax the constraint that the cell exceeds the right boundary of its row, then formula (3) can be rewritten as formula (4);

(4)

(4)

是所有单元水平方向坐标向量，

是单位矩阵，

是每个元素

的向量，

是单元左右水平相邻关系的约束矩阵，

中每行中只有两个非零元素-1和1，

的行数是单元水平方向的左右约束数目，

的列数是单元数。in,

is the horizontal coordinate vector of all units,

is the identity matrix,

Each element

The vector of

is the constraint matrix of the horizontal adjacent relationship of the unit.

There are only two non-zero elements in each row of

The number of rows is the number of left and right constraints in the horizontal direction of the cell.

The number of columns is the number of cells.

，

，它们可以合并为集成单元

。为了产生脉冲窄化效应，集成单元宽度和初始坐标是根据其内部单元初始坐标计算的。In order to produce the pulse narrowing effect, paired logically related cells must be laid out horizontally and close to each other. During the cell relocation process, cells within one or more pairs of quenching cells are combined to ensure that after relocation, cells in the same pair or group are close to each other. Figure 7 shows an example of a combined cell. Given two paired cell pairs

,

, they can be combined into integrated units

To generate the pulse narrowing effect, the integrated cell width and initial coordinates are calculated based on their internal cell initial coordinates.

，其中子单元

的宽度和初始坐标分别为

和,

则

的宽度和初始坐标根据公式(5)设置；For combined units

, where the subunit

The width and initial coordinates are

and,

but

The width and initial coordinates of are set according to formula (5);

(5)

(5)

是组合单元

中所有子单元的宽度之和，初始

坐标

设置为

内部子单元的中值

坐标。但初始

坐标

的计算更复杂，以下给出具体计算推理。Among them, the width

It is a combined unit

The sum of the widths of all subunits in the initial

coordinate

Set to

The median value of the internal subunit

coordinates. But the initial

coordinate

The calculation of is more complicated, and the specific calculation reasoning is given below.

。在单元重定位后，我们得到

和

。根据公式(3)的目的，组合单元

的初始坐标

可以由公式(6)导出；For the case of t=2, that is,

After cell relocation, we get

and

According to the purpose of formula (3), the combined unit

The initial coordinates of

It can be derived from formula (6);

(6)

(6)

，其中

，我们有

_t和

,

,

。类似地，组合单元

的初始坐标

可以通过公式(7)导出；For multiple units forming a combined unit, that is, when t > 2,

,in

, we have

_t and

,

,

Similarly, the combined unit

The initial coordinates of

It can be derived by formula (7);

(7)

(7)

Step 4, based on the initial positions of all units, calculate the unit relocation considering the displacement to obtain the quenching unit pair that satisfies the quenching effect;

Furthermore, the step 4 specifically includes:

Step 4.1, relocate the combined cells and the unpaired cells by using the formula corresponding to the layout problem, model the linear complementarity problem, and construct the linear complementarity problem data structure by giving the cell information and connection relationship netlist of the combined cells and the unpaired cells;

Step 4.2, compressing the linear complementarity problem data structure through a two-step scanning strategy to construct its corresponding constraint matrix, and applying the module-based matrix splitting iteration method to solve the linear complementarity problem;

Step 4.3, according to the solution result, the relocated unit coordinates are obtained, and they are integerized to obtain the legal positions of all units including the combined unit, and the original adjacent unit pairs in the successfully laid out combined unit are used as quenched unit pairs.

Furthermore, the expression of the layout problem is:

是所有单元水平方向坐标向量，

是单位矩阵，

是每个元素

的向量，

是单元左右水平相邻关系的约束矩阵，

中每行中只有两个非零元素-1和1，

的行数是单元水平方向的左右约束数目，

的列数是单元数，向量

中每个元素对应矩阵

每行左右水平相邻约束中左边单元的宽度。in,

is the horizontal coordinate vector of all units,

is the identity matrix,

Each element

The vector of

is the constraint matrix of the horizontal adjacent relationship of the unit.

There are only two non-zero elements in each row of

The number of rows is the number of left and right constraints in the horizontal direction of the cell.

The number of columns is the number of cells, and the vector

Each element in the matrix

The width of the left cell in the horizontal adjacent constraints on each row.

的步骤包括：Furthermore, the two-step scanning strategy is used to compress the linear complementarity problem data structure to construct its corresponding constraint matrix

The steps include:

When scanning cells in a row from left to right, first form neighbor constraints between cells in odd positions and their right adjacent cells;

After the first scan, the second scan begins, adding neighbor constraints between the cell and its right neighbor at even positions.

In specific implementation, after the integrated cell is initialized, the integrated cell and the unpaired cell will be relocated by solving the layout problem described in formula (4). In order to reduce the circuit performance degradation after the cell relocation, the displacement between the cell and the initial coordinates is considered during the cell relocation. The displacement-driven cell movement problem is modeled as a linear complementary problem (LCP). Given the information of all cells including integrated cells and unpaired cells, as well as the connection relationship netlist between them, the LCP data structure can be constructed. After the data is constructed, the modular matrix splitting iteration method (MMSIM) can be applied to solve the LCP problem. Finally, we get the coordinates of the relocated cells based on the MMSIM results.

中。向量

可以通过向量

计算。对于每次迭代

，基于向量

，可以获得向量

。MMSIM过程经过多次迭代直到

时完成；The objective function in formula (4) can be modeled as LCP and solved by MMSIM. The iterative process of MMSIM is shown in formula (8), where the horizontal coordinates of the unit are stored in the vector

In. Vector

Through the vector

Calculate. For each iteration

, based on vector

, we can get the vector

The MMSIM process goes through multiple iterations until

Completed when

(8)

(8)

是迭代次数，向量

、

和矩阵

、

和

的计算由公式(9)给出。其中，

、

和

出现在公式(4)中，矩阵

在MMSIM中被拆分为

，

是矩阵

的Schur补码

的三对角近似。

和

都是正常数，在我们的实现中设置都为0.5。前人工作给出了MMSIM的数据构造和证明过程；in,

is the number of iterations, the vector

,

and matrix

,

and

The calculation of is given by formula (9). Where,

,

and

Appearing in formula (4), the matrix

In MMSIM, it is divided into

,

is a matrix

Schur complement

The tridiagonal approximation of .

and

They are all positive numbers, and are set to 0.5 in our implementation. Previous work has given the data construction and proof process of MMSIM;

(9)

(9)

After solving the LCP, since the calculated coordinates are continuous floating point types, we need to align the cells with the nearest legal position. The sub-cells inside the integrated cell also need to be restored and laid out in horizontally adjacent positions. Since the right boundary constraint of the row is relaxed in formula (4), if there is cell overlap or the unit position exceeds the right boundary of the row in the MMSIM result, the position of these cells is illegal. Since in practice, the number of illegal cells is very small, we can directly find the nearest legal position and lay it out.

都需要利用

的逆矩阵求出

。根据公式(9)所示，因为

的每个部分都是稀疏矩阵，其中：(1)矩阵

为对角矩阵，(2)矩阵

每行只有两个非零元素，即-1和1，(3)矩阵

为三对角矩阵，所以可以判断M是稀疏矩阵。同样地，

也是稀疏矩阵，

可以使用高斯消元法计算，但是

可能不是稀疏矩阵，其非零元素的个数可能很大。如果

不是稀疏矩阵，它将极大地影响存储和计算的可扩展性。As shown in formula (8), in the process of solving LCP using MMSIM, each iteration

Need to use

Find the inverse matrix of

According to formula (9), because

Each part of is a sparse matrix, where: (1) the matrix

is a diagonal matrix, (2) the matrix

Each row has only two non-zero elements, namely -1 and 1. (3) The matrix

is a tridiagonal matrix, so we can judge that M is a sparse matrix. Similarly,

is also a sparse matrix,

It can be calculated using Gaussian elimination, but

may not be a sparse matrix and the number of its nonzero elements may be large.

Not a sparse matrix, which will greatly affect the scalability of storage and computation.

，根据单元初始坐标得到向量

。其相邻的关系为：

。根据相邻关系顺序，对应的向量

，图8 (a)给出了对应的矩阵

，和

。基于矩阵

和

，我们可以获得矩阵

，并计算其逆矩阵

。然而，矩阵

不是稀疏矩阵。Figure 8 shows an example where there are six cells in a row.

, according to the initial coordinates of the unit, we get the vector

. The adjacent relationship is:

According to the order of adjacent relations, the corresponding vector

, Figure 8 (a) shows the corresponding matrix

,and

. Based on the matrix

and

, we can obtain the matrix

, and calculate its inverse matrix

However, the matrix

is not a sparse matrix.

的有效方法，可以确保

成为稀疏矩阵。该方法主要考察矩阵

中的子矩阵

构造。为了使三对角矩阵

成为对角矩阵，矩阵

应该修改构建方法。This embodiment provides a construction matrix

An effective method to ensure

Become a sparse matrix. This method mainly examines the matrix

The submatrix in

In order to make the tridiagonal matrix

becomes a diagonal matrix, the matrix

The build method should be modified.

的每一行中只有两个非零元素，即1和-1，并且

，假设

是

的第

行，我们分别有

，

。为了使得

是对角矩阵，

和

都应为0。其中，对于

，如果行

中非零元素的位置与行

中的位置不同，则我们得到

。类似地，如果行

中的非零元素的位置与行

中的位置不同，则我们得到

。如果

，

，三对角矩

将退化为对角矩阵。因此，在构建矩阵B时，我们需要确保每个个

和

、

的非零元素具有不同的位置。because

There are only two non-zero elements in each row of

, assuming

yes

No.

OK, we have

,

In order to make

is a diagonal matrix,

and

should all be 0.

, if the line

The positions and rows of non-zero elements in

If the positions in are different, we get

. Similarly, if the line

The positions of the non-zero elements in the row

If the positions in are different, we get

.if

,

, three diagonal moments

will degenerate into a diagonal matrix. Therefore, when constructing the matrix B, we need to ensure that each

and

,

The non-zero elements of have different positions.

的构建过程。如图8(a)所示，我们按顺序给出相邻单元约束：

。为了使

为稀疏矩阵，即每个

和

、

的非零元素应该具有不同的位置，我们在构建

时改变了相邻单元的顺序：

。由于相邻关系不变，因此不会改变单元相邻约束条件。根据相邻关系顺序，对应的向量

，相应的矩阵

和矩阵

如图8 (b)所示。可以看出，三对角矩阵

退化为对角矩阵。因此，与图8(a)相比，我们得到的

是稀疏矩阵。为了区别于图8(a)中的顺序扫描策略，我们将图8(b)中的矩阵构建方法称为两步扫描策略。Figure 8 shows an example to illustrate

As shown in Figure 8(a), we give the adjacent unit constraints in sequence:

In order to make

is a sparse matrix, that is, each

and

,

The non-zero elements of should have different positions.

, which changes the order of adjacent cells:

Since the adjacent relationship remains unchanged, the cell adjacent constraint will not be changed. According to the order of adjacent relationship, the corresponding vector

, the corresponding matrix

and matrix

As shown in Figure 8 (b), it can be seen that the tridiagonal matrix

degenerates into a diagonal matrix. Therefore, compared with Figure 8(a), we get

is a sparse matrix. To distinguish it from the sequential scanning strategy in Figure 8(a), we call the matrix construction method in Figure 8(b) a two-step scanning strategy.

The two unit scanning strategies are summarized as follows:

在单元

的左侧，

为右相邻单元，即

。通常，我们可以默认从左向右扫描单元行，并逐个为矩阵

中的每对相邻单元

添加约束。Sequential Scan: Assumption Unit

In the unit

On the left side,

is the right adjacent unit, that is

. Usually, we can default to scanning the cell rows from left to right and one by one for the matrix

Each pair of adjacent cells in

Add constraints.

Two-step scan: When scanning cells in a row from left to right, we first form neighbor constraints between cells in odd positions and their right neighbors. After the first scan, we start the second scan, adding neighbor constraints between cells in even positions and their right neighbors.

的复杂性，从而提高算法可扩展性。在我们的两步扫描策略下，每行的非零元素数为3；而在顺序扫描策略下每行的非零元素数量与每行单元数目RowCC成正比。因此，两步扫描策略下的矩阵压缩比CompRatio如公式(10)所示。当电路规模越大，每行布局的单元越多，压缩比越高。实验表明两种扫描策略的结果最大差异小于

。由于布局坐标需要四舍五入为整数，这两种扫描策略之间的差异可以忽略不计，这意味着我们的两步扫描策略可以在单元重定位过程中提供无损数据压缩；Through the two-step scanning strategy, it can effectively reduce

The complexity of the algorithm is reduced, thereby improving the scalability of the algorithm. Under our two-step scanning strategy, the number of non-zero elements in each row is 3; while under the sequential scanning strategy, the number of non-zero elements in each row is proportional to the number of cells in each row RowCC. Therefore, the matrix compression ratio CompRatio under the two-step scanning strategy is shown in formula (10). When the circuit scale is larger, the more cells are laid out in each row, and the higher the compression ratio. Experiments show that the maximum difference in the results of the two scanning strategies is less than

Since the layout coordinates need to be rounded to integers, the difference between the two scanning strategies is negligible, which means that our two-step scanning strategy can provide lossless data compression during cell relocation;

(10)

(10)

的计算复杂度为

。这是因为公式(8)和(9)中的所有矩阵，即

、

、

、

和

，都是具有

个非零元素的稀疏矩阵，矩阵向量乘法、矩阵加法/减法和向量运算的所有复杂度都是

。此外，在两步扫描策略下，

计算的复杂度也是

。最后，实验表明所有测试用例的MMSIM迭代次数约为1000-2000次。Using MMSIM to solve the LCP, each iteration

The computational complexity is

This is because all matrices in formulas (8) and (9), namely

,

,

,

and

, all have

For a sparse matrix with non-zero elements, all complexities of matrix-vector multiplication, matrix addition/subtraction, and vector operations are

In addition, under the two-step scanning strategy,

The computational complexity is also

Finally, experiments show that the number of MMSIM iterations for all test cases is about 1000-2000.

Step 5, taking into account the quenching unit pair, further optimizing the line length by using the preset operation, wherein the preset operation includes a unit exchange operation and a unit insertion operation, and finally generating an optimized layout result;

In specific implementation, after the cell is relocated, operations such as cell exchange and insertion can be used to further optimize the line length HPWL, while ensuring that the quenching cell pairs that have been generated will not be separated, thereby obtaining the initial layout result. After obtaining the initial layout result, it can be determined whether the line length in the initial layout result converges. If so, an optimized layout result is generated. If not, return to step 4 for optimization again.

The soft error layout optimization method considering pulse narrowing provided in this embodiment optimizes the soft error rate by considering the quenching effect enhancement during layout, and can reduce the soft error generation in the circuit without introducing any hardware penalty. By setting the layout algorithm to dynamically pair cells during layout, all cells are then globally paired at one time, and they are globally relocated during subsequent cell relocation processes, the quenching effect between adjacent logically related cells is enhanced, thereby improving the optimization efficiency and the quenching effect enhancement performance.

The following will illustrate this solution with reference to an embodiment. In the experiment, C++ can be used to implement the detailed layout method. The compilation tool is g++4.4.7. The program runs on a Linux workstation that uses a 2.20GHz IntelXeon CPU and 32GB RAM, using a single CPU core. We use the ISCAS-85 test case to evaluate the layout performance. The RTL code of the ISCAS-85 test case is input, and the logic synthesis is performed using Synopsys Design Compiler based on the 65nm cell library, in which the cell library only uses three cell types: INV, NAND, and NOR. Then, the synthesized netlist uses the Cadance Innovus tool to generate the initial layout. We use the mixed mode analysis tool (MMAT) to evaluate the SER performance. Table 1 gives the ISCAS-85 test case information;

The MMAT tool is used to evaluate the SER. The tool uses devices from the 65nm dual-well process cell library and uses a grid-based 3D TCAD simulation method to obtain the SET pulse width of the ion impact. The 3D TCAD model will eventually be calibrated to match the SPICEI-V curve;

Table 2 lists the simulation configuration. For each test case, we simulated 10,000 random stimulus vectors. For each random stimulus vector, the behavior of the netlist was simulated using a Verilog simulator to inject transient pulses into the logic gates. Then, the propagation of the pulses was simulated by MMAT. Finally, the transient pulse width and its distribution were captured at each output of the circuit. The output of MMAT includes SER and transient pulse width distribution.

，其

，计算如公式(11)所示；In order to quantitatively measure the soft error sensitivity in combinational circuits, we use the soft error sensitivity factor (SEVF) for investigation.

,That

, calculated as shown in formula (11);

(11)

(11)

是模拟输入向量的数目，

是当

的漏极区域被击中时，

在输入向量

下产生SET脉冲的概率，

是SET脉冲在输入向量

下传播到电路输出端的概率。in

is the number of simulated input vectors,

When

The drain region is hit when

In the input vector

The probability of generating a SET pulse under

is the SET pulse in the input vector

The probability of propagating to the output of the circuit.

的SEVF可以通过对所有

求和来获得，如公式(12)所示；The whole circuit

The SEVF can be

The sum is obtained as shown in formula (12);

(12)

(12)

Table 3 compares the optimization performance of the input layout and our work Ours in terms of pulse narrowing effect and SER. The CircuitSEVF column shows the soft error evaluation value of the circuit, the Quenching Unit Number column shows the number of units in the quenching unit pair, the Pulse Narrowing Event Number column shows the number of pulse narrowing effects during the simulation using 10,000 random excitation vectors, and CPU(s) is the running time in seconds. It can be seen that the CircuitSEVF of our method is reduced by an average of 29.66%, and the number of quenching units and the number of pulse narrowing events are greatly optimized. For all test cases, the running time of Ours is less than 0.2 seconds. The running time overhead mainly comes from the LCP solution process.

Table 4 lists the line length HPWL and average displacement after the layout optimization considering pulse narrowing by Ours method. To further investigate the reason for the increase in HPWL during the layout optimization considering pulse narrowing, we show the average Manhattan distance between the cell and its fan-out in the column of initial average connection distance. As shown in Table 4, the initial average connection distance of all test cases is generally large, with an average value of 33.50. Therefore, when it is necessary to move cells to generate quenching cell pairs, it will cause large cell displacement.

Taking the largest circuit C7552 in ISCAS85 as an example, Figure 9 shows an example of unit layout considering the pulse narrowing effect. It can be found that in the initial layout result of the input in Figure 9(a), only a few random quenching unit pairs are distributed. Figure 9(b) is the result of Ours method. After the optimization of the pulse narrowing effect, the number of quenching unit pairs increases significantly. It should be mentioned that since the quenching unit pairs need to be horizontally adjacent, compared with the input layout, the more quenching unit pairs there are, the tighter the layout distribution will be.

To further investigate the impact of pulse narrowing enhancement on the design, we routed the layout results and then reported the circuit timing and power information through PrimeTime (PT). Ours’s layout results showed no routing congestion. In addition, from the PT report, we observed that the timing impact of all test cases was less than 1ps and the power impact was 0μW. In other words, the timing and power loss after pulse narrowing enhancement were negligible in all test cases. The main reason for our analysis of this result is that the timing changes are small due to the relatively small chip size of the design, such as the largest test case C7552 is 68.30×68.75μm, and the generally short connection length. In more general cases, because our LCP method considers cell displacement, the timing path changes are guaranteed to be within a reasonably small range.

Table 5 lists the number of soft errors corresponding to four pulse width ranges, namely pulse widths [0~100ps), [100ps~200ps), [2000ps~300ps) and [300ps~400ps]. On average, our method can reduce the number of soft errors by about 19.63%~54.17% in these pulse width ranges;

Finally, due to the small size of ISCAS85, in order to perform scalability analysis, we used the four largest test circuits from EPFL combinational logic circuits, the largest of which is Hypotense, with more than 2.7×E5 cells and wire nets. The selected EPFL test case information is shown in Table 6;

Currently, there is no commercial tool that can directly consider the pulse narrowing effect to analyze the SER, and since the analysis scale of existing MMAT tools is very limited, in order to evaluate the optimization results of our detailed layout method for the pulse narrowing effect of the EPFL circuit, we mainly consider the number of quenching units. It can be observed from Table 3 above that the more quenching units there are, the more helpful it is to produce the pulse narrowing effect and help reduce the SER. Therefore, for the EPFL circuit, we mainly measure the effect of pulse narrowing by the number of quenching units.

As shown in Table 7, on all EPFL circuits, our method increases the number of quenching cells by 0.71 times compared to the input initial layout. The increase ratio of quenching cells on the EPFL circuit is comparable to the results on the ISCAS85 circuit (as shown in Table 3). In addition, our HPWL increases by only 8.91% on average, which is less impactful than the ISCAS85 circuit shown in Table 4. Referring to Table 3, we also found that although the scale of EPFL circuits is 10-100 times larger than that of ISCAS85 circuits, the average displacement of EPFL is generally smaller. In addition, our running time increases basically linearly with the increase of circuit scale, of which about 46.60% of the running time is used to solve LCP during the cell relocation process. Therefore, it can be concluded that our method has good scalability;

By optimizing SER by considering pulse narrowing enhancement during layout, soft error generation in the circuit can be mitigated without introducing any hardware penalty. In order to reduce soft errors in combinational circuits by utilizing the pulse narrowing effect, we propose a detailed layout algorithm that can enhance the pulse narrowing effect between adjacent logically related cells. In our method, the pulse narrowing effect enhancement is globally optimized and considers the minimization of cell displacement. Simulation results show that our method can significantly increase the number of quenching cell pairs, and the soft error sensitivity of the circuit is reduced by an average of 25.99%. In addition, for large-scale test circuits, the pulse narrowing effect enhancement performance of our method is stable, with smaller displacement, and the running time increases linearly with the scale, which proves the scalability of our method.

The units involved in the embodiments of the present invention may be implemented in software or hardware.

It should be understood that various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof.

The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (8)

1. A soft error layout optimization method considering pulse narrowing, characterized by comprising: Step 1, perform logic synthesis on the preset RTL design and use layout tools to generate input layout; Step 2, use the KM algorithm to globally find all possible unit pairs in the input layout and obtain the unit pairing results; Step 3, generating a combined unit according to the unit pairing result, and calculating the initial position and size of the combined unit according to the original unit information; Step 4, based on the initial positions of all units, calculate the unit relocation considering the displacement to obtain the quenching unit pair that satisfies the quenching effect; Step 5, taking into account the quenching unit pair, further optimize the line length using preset operations, wherein the preset operations include a unit exchange operation and a unit insertion operation, and finally generate an optimized layout result. 2. The method according to claim 1, characterized in that the step 2 specifically comprises: Step 2.1, generate the fan-out set corresponding to each unit and calculate the sensitivity of each unit; In step 2.2, the KM algorithm is used to pair each unit with the unit with the highest sensitivity in its corresponding fan-out set to form a unit pairing result. 3. The method according to claim 2, characterized in that the step 2.2 specifically comprises: set up

and

Unit

and its fan-out unit

The input coordinates and calculate the unit

and its fan-out unit

The pairing weight of Building a connection graph

,in

represents the set of fan-in units,

represents the set of fan-out units,

Represents a connection set; The KM algorithm is called to perform global unit pairing on the connection graph to form a unit pairing result. 4. The method according to claim 3, characterized in that the calculation formula of the pairing weight is:

,

in,

Indicates sensitivity,

and

are all positive parameters. 5. The method according to claim 3, characterized in that said step 3 specifically comprises: Based on the existing original unit information and displacement driven problem, it can be described as

and rewrite it as a layout problem based on the preset conditions; The initial information of the reasoning combination unit, for the integrated unit

, whose width and initial coordinates are calculated as follows:

in,

and

, respectively

The width and initial lower left corner coordinate of the cell, and accordingly, for the child cells

,

and

Respectively

The width and initial lower left corner coordinates. 6. The method according to claim 4, characterized in that said step 4 specifically comprises: Step 4.1, relocate the combined cells and the unpaired cells by using the formula corresponding to the layout problem, model the linear complementarity problem, and construct the linear complementarity problem data structure by giving the cell information and connection relationship netlist of the combined cells and the unpaired cells; Step 4.2, compressing the linear complementarity problem data structure through a two-step scanning strategy to construct its corresponding constraint matrix, and applying the module-based matrix splitting iteration method to solve the linear complementarity problem; Step 4.3, according to the solution result, the relocated unit coordinates are obtained, and they are integerized to obtain the legal positions of all units including the combined unit, and the original adjacent unit pairs in the successfully laid out combined unit are used as quenched unit pairs. 7. The method according to claim 5, characterized in that the expression of the layout problem is

in,

is the horizontal coordinate vector of all units,

is the identity matrix,

Each element

The vector of

is the constraint matrix of the horizontal adjacent relationship of the unit.

There are only two non-zero elements in each row of

The number of rows is the number of left and right constraints in the horizontal direction of the cell.

The number of columns is the number of cells, and the vector

Each element in the matrix

The width of the left cell in the horizontal adjacent constraints on each row. 8. The method according to claim 6, characterized in that the linear complementarity problem data structure is compressed by a two-step scanning strategy to construct its corresponding constraint matrix

The steps include: When scanning cells in a row from left to right, first form neighbor constraints between cells in odd positions and their right adjacent cells; After the first scan, the second scan begins, adding neighbor constraints between the cell and its right neighbor at even positions.

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