CN116069718A

CN116069718A - Chip configuration method, device, equipment and medium

Info

Publication number: CN116069718A
Application number: CN202310100982.0A
Authority: CN
Inventors: 周开林
Original assignee: Zhuanxin Semiconductor Nanjing Co ltd
Current assignee: Zhuanxin Semiconductor Nanjing Co ltd
Priority date: 2023-02-10
Filing date: 2023-02-10
Publication date: 2023-05-05

Abstract

The invention relates to the technical field of integrated chips, and discloses a chip configuration method, a device, equipment and a medium, wherein the method comprises the following steps: dividing a module to be configured into at least two serial configuration structures; determining configuration data of a module to be configured in the serial configuration structure, and writing the configuration data into a configuration cache module; the configuration buffer module sends configuration data to the module to be configured through the broadcast bus matrix, and the module to be configured is configured; the broadcast bus matrix returns a write response to the configuration buffer module so that the configuration buffer module can continue to send configuration data to the module to be configured. The efficiency of chip configuration is improved.

Description

Chip configuration method, device, equipment and medium

Technical Field

The present invention relates to the field of chip integration technologies, and in particular, to a method, an apparatus, a device, and a medium for configuring a chip.

Background

With the development of integrated circuit technology, the performance and functionality of chips have increased with the increase in circuit integration capability. Before the chip is put into use, the chip needs to be subjected to integrated work such as function configuration.

As it is now more distant. For example, large-scale switching integrated circuits are increasingly large, with more and more modules being integrated on one chip, with more and more physical distances from each other than from the chip, with very few hundred million-gate sizes, and with tens or even hundreds of physically separated modules being integrated. The whole chip needs to be initialized and configured before the chip works, and the initialized and configured values are different in different working scenes, so that a large number of addresses need to be written. In the chip operation process, if some modules have error conditions, it may need to re-initialize a certain batch of modules, and also need to write a large number of addresses.

The configuration mode is that the CPU writes the internal register or the memory of each module.

One method is that the on-chip CPU or the upper computer directly writes each address, because the physical distance of most modules is far, delay in terms of CPU fetch and the like is not considered, if 20 clocks are required for averagely sending each address from the CPU to write completion, a total of 100 modules need to be configured, and 1000 registers need to be configured for each module, and a total of at least 20x100x 1000=2_000_000 clocks are required for configuration completion. Considering only the configuration of registers, there are actually many modules on the switch that need to initialize the memory, which is several orders of magnitude larger than the registers, thus making it much longer to configure a round.

Therefore, how to configure a chip to reduce complexity and difficulty of chip configuration is one of the technical problems to be considered.

Disclosure of Invention

The invention provides a chip configuration method, a chip configuration device, computer equipment and a medium.

In a first aspect, a chip configuration method is provided, including:

dividing a module to be configured into at least two serial configuration structures;

determining configuration data of a module to be configured in the serial configuration structure, and writing the configuration data into a configuration cache module;

the configuration buffer module sends the configuration data to the module to be configured through a broadcast bus matrix, and configures the module to be configured;

and the broadcast bus matrix returns a write response to the configuration buffer module so that the configuration buffer module can continuously send configuration data to the module to be configured.

In some embodiments, the dividing the module to be configured into at least two serial configuration structures includes:

displaying a configuration interface of the serial configuration structure to a user;

dividing the modules to be configured selected by the user into a group, wherein the modules belong to the same type;

and dividing the modules to be configured belonging to the same group into at least two serial configuration structures according to the grouping restriction rule.

In some embodiments, the dividing the modules to be configured selected by the user into a group, which belong to the same type, includes:

and dividing the modules to be configured with the same type and configuration data coincidence rate larger than a first preset threshold value into the same group according to a preset classification rule.

In some embodiments, the packet limiting rule comprises:

the serial configuration structures divided by the modules to be configured in the same group contain the same number of the modules to be configured.

In some embodiments, the packet limiting rule comprises:

the at least two serial configuration structures can form an association relationship, wherein the first serial configuration structure and the second serial configuration structure are the association relationship, so that at least one module to be configured in the first serial configuration structure and the module to be configured in the second serial configuration structure are the association relationship, the ordering positions of the modules to be configured in the association relationship in the respective serial configuration structures are the same, and the configuration data superposition rate is larger than a second preset threshold.

In some embodiments, the determining the configuration data of the module to be configured in the serial configuration structure, writing the configuration data into a configuration buffer module, includes:

acquiring first configuration data of a module to be configured in a serial configuration structure, and writing the first configuration data into the configuration cache module;

copying the first configuration data, and writing the first configuration data into the configuration buffer module to obtain configuration data of a serial configuration structure which has an association relation with the serial configuration structure.

In some embodiments, the configuration buffer module sends the configuration data to the module to be configured through a broadcast bus matrix, including:

and the configuration buffer module sends the configuration data to the module to be configured in a preset write command period through a broadcast bus matrix.

In a second aspect, there is provided a chip configuration apparatus, comprising:

the grouping unit is used for dividing the module to be configured into at least two serial configuration structures;

the generating unit is used for determining configuration data of the module to be configured in the serial configuration structure and writing the configuration data into the configuration cache module;

the configuration unit is used for the configuration cache module to send the configuration data to the module to be configured through a broadcast bus matrix and configure the module to be configured;

and the response unit is used for returning a write response to the configuration buffer module by the broadcast bus matrix so that the configuration buffer module can continuously send configuration data to the module to be configured.

In a third aspect, a computer device is provided, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the steps of the above-described chip configuration method when executing the computer program.

In a fourth aspect, a computer readable storage medium is provided, the computer readable storage medium storing a computer program which, when executed by a processor, implements the steps of the above-described chip configuration method.

In the scheme realized by the chip configuration method, the device, the computer equipment and the storage medium, the module to be configured can be divided into at least two serial configuration structures; determining configuration data of a module to be configured in the serial configuration structure, and writing the configuration data into a configuration cache module; the configuration buffer module sends configuration data to the module to be configured through the broadcast bus matrix, and the module to be configured is configured; the broadcast bus matrix returns a write response to the configuration buffer module so that the configuration buffer module can continue to send configuration data to the module to be configured. In the present invention, an additional mode, a broadcast mode, is added, in which the cross-linking and arbitration of multiple slaves (internal RAM, APB, external BUS, etc.) is performed in response to the BUS Matrix being the multi-master (Core, DMA, etc.) that issued BUS Matrix at the command [ ARM ]. The purpose is to improve the bandwidth under the condition that different hosts access different peripheral devices, and the other is to simplify the protocol design of the Bus Master. The configuration flow is greatly accelerated by the BUS Matrix which is generated and returned to the DMA channel.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of an application environment of a chip configuration method according to an embodiment of the invention;

FIG. 2 is a flow chart of a chip configuration method according to an embodiment of the invention;

FIG. 3 is a flow chart illustrating a method of configuring a chip according to an embodiment of the invention;

FIG. 4 is a flow chart of a chip configuration method according to an embodiment of the invention;

FIG. 5 is a schematic diagram of a chip configuration apparatus according to an embodiment of the invention;

FIG. 6 is a schematic diagram of a computer device according to an embodiment of the invention;

FIG. 7 is a schematic diagram of another embodiment of a computer device according to the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The chip configuration method provided by the embodiment of the invention can be applied to an application environment as shown in fig. 1, wherein a client communicates with a server through a network. The server side can obtain configuration files corresponding to all groups according to grouping information of a serial configuration structure of a module to be configured by a user and the grouping information, wherein the configuration files comprise a transmission port calling file, a pin multiplexing file, a port pin connection file and a register file; generating configuration data of the module to be configured according to the configuration file; the configuration bus sends configuration data to the module to be configured, and the module to be configured is configured; and when the configuration of the module to be configured is completed, the module to be configured returns a configuration response to the configuration bus. In the invention, the efficiency of chip configuration is improved. The clients may be, but are not limited to, various personal computers, notebook computers, smart phones, tablet computers, and portable wearable devices. The server may be implemented by a stand-alone server or a server cluster formed by a plurality of servers. The present invention will be described in detail with reference to specific examples.

Referring to fig. 2, fig. 2 is a schematic flow chart of a chip configuration method according to an embodiment of the invention, including the following steps:

s10, dividing a module to be configured into at least two serial configuration structures;

the chip to be configured may be a chip that needs to be designed and configured, for example, configuration of the chip includes configuration such as IO (input and output) instantiation and pin multiplexing. In the configuration process of IO instantiation and pin multiplexing of the chip, a plurality of configuration files are required to be generated, corresponding relations among hardware function modules corresponding to the configuration files respectively are determined, and relevant files for configuring the chip to be configured are obtained.

In some embodiments, the step S10 may include:

s101, displaying a configuration interface of a serial configuration structure to a user;

s102, dividing the modules to be configured selected by a user into a group, wherein the modules belong to the same type;

it will be appreciated that the chip may include multiple types (such as port configuration and cache configuration), each type may be the same physical module, or may be a functional module, on the basis of which, when the modules are configured, they are classified by type, and the selected serial channels generally need to belong to the same type, that is, serial channels in one type are selected first, and then the modules to be configured, which are connected in series with the channels, are configured in sequence.

S103, dividing the modules to be configured belonging to the same group into at least two serial configuration structures according to the grouping restriction rule.

In some embodiments, the dividing the modules to be configured selected by the user into a group in the S102 may include:

It will be appreciated that the switch is often divided into multiple PIPEs, and the hardware and modules of each PIPE are substantially the same, so that the configuration is also substantially the same, and one PIPE can be put into one ring, and the PIPEs are put into one group, so that when one ring is configured, the configuration is also duplicated and sent to other PIPEs, and the configuration efficiency is improved by several times.

In some embodiments, the packet limiting rule includes:

In an application scenario, as shown in fig. 3 and 4, the packet adopts a structure shown in fig. 3, and the configuration data may be located in an upper computer) [ cpu or pcie ], or may be located in an on-chip Main memory (Main Mem in the figure), where each module (BLK) to be configured is connected in series in a ring form, and is divided into multiple rings (ring 0-ring n in the figure) so as to be configured in parallel. If the two DMA (direct memory access) channels are not the same Ring then the Ring to be configured can be configured in parallel, e.g. DMA CH0 configuration Ring0, DMACH1 configuration Ring 1.

Meanwhile, when a loop is built, similar configured modules are symmetrically placed on the same group of loops, so that configuration data on one loop is simultaneously copied to other loops of the same group when the configuration data is sent out, the configuration of one loop at a time can be completed, and the configuration speed is further increased.

For example, the number of rings 0-3 on the hardware is a group, the hardware of different rings is basically equivalent, for example, the first ring has 4 BLKs, the number of 2-3 rings is also 4 BLKs, the configuration of the 1 st BLK of the first ring is similar to that of the 1 st BLK of the 2-3 rings, the following steps are basically similar, and the special configuration with difference can be independently configured through the common configuration.

The configuration DB 0-n is the configuration address (to be allocated to that BLM in DB) and the configuration size of the configuration module 0-n and is written to the Main Mem, the configuration configured_data0-n is the data to be Configured of the configuration module 0-n and is written to the Main Mem, the DMA CH0 is set to process these DB and configuration data, after completion, the DMA CH0 will go to the Main Mem to fetch DB, then the configuration data is fetched according to DB content, and then the configuration data is copied and issued to Ring0-3, the issued command has a broadcast flag, all the Configured modules receive such commands without responses, the responses are generated at Bus Marix (Bus matrix) and can be quickly returned to the corresponding DMA CH0, so that the commands are continuously sent to all the modules on Ring0-3 to configure them, as shown in fig. 4.

It can be seen that the write command can be issued substantially continuously, dividing 100 modules over 4 rings according to the previous calculation scenario, requiring only one clock per configuration, requiring a total of 1x25x1000 = 25_000 clocks, since it is ideally 80 times faster.

In some embodiments, the grouping constraint includes that the number of modules to be configured of the grouping having the association is the same, and the ordering positions of the modules to be configured having the same configuration data in the serial configuration structure are the same.

In some embodiments, the configuration buffer module sends configuration data to the module to be configured through the broadcast bus matrix, including:

the configuration buffer module sends configuration data to the module to be configured in a preset write command period through the broadcast bus matrix.

It can be understood that if the configured module cannot process the configuration data quickly, the configured module can also set a broadcast gap, and commands can be continuously sent out when the configured module is not configured, and every time the configured broadcast command starts to time when the command is sent, the next command can only be sent when the time reaches the set value of the broadcast gap, so that the situation that the module cannot respond quickly can be dealt with.

In some embodiments, S1031 may include: the grouping constraint condition comprises that the number of the grouping modules to be configured with the association relation is the same, and the ordering positions of the grouping modules to be configured with the same configuration data in the serial configuration structure are the same.

S20, determining configuration data of a module to be configured in the serial configuration structure, and writing the configuration data into a configuration cache module;

s30, the configuration buffer module sends configuration data to the module to be configured through the broadcast bus matrix, and the module to be configured is configured;

in some embodiments, the step S30 may include: the configuration bus sends configuration data to the module to be configured in a preset configuration period.

And S40, the broadcast bus matrix returns a write response to the configuration buffer module so that the configuration buffer module can continuously send configuration data to the module to be configured.

It will be appreciated that, typically, each time a write is completed, the configured module needs to return a response to indicate that the write is completed, although the host may support outlining (outlining refers to the ability of the host to initiate multiple read-write transactions when no response is received), when a command corresponding to outlining depth is sent, the next command needs to be sent after waiting for a response to return, and when configuration is initialized, a large number of write commands are generated and a large number of write responses are generated, and these write responses need to be sent back to the corresponding channels of the DMA around the loop, which significantly slows the speed of configuration. An extra mode, broadcast mode, is added in which the cross-linking and arbitration of multiple slaves (internal RAM, APB, external BUS, etc.) is performed in response to the BUS Matrix being sent out at command (BUS, DMA, etc.). The purpose is to improve the bandwidth under the condition that different hosts access different peripheral devices, and the other is to simplify the protocol design of the Bus Master. The configuration flow is greatly accelerated by the BUS Matrix which is generated and returned to the DMA channel.

In some embodiments, the above method further comprises: the configuration data is converted into a code file.

It can be seen that in the above scheme an extra mode is added, broadcast mode, in which the BUS Matrix in response to the command send out BUS Matrix [ ARM is multi-master (Core, DMA etc.), cross-linking and arbitration of multi-slaves (internal RAM, APB, external BUS etc.). The purpose is to improve the bandwidth under the condition that different hosts access different peripheral devices, and the other is to simplify the protocol design of the Bus Master. The configuration flow is greatly accelerated by the BUS Matrix which is generated and returned to the DMA channel.

It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present invention.

In an embodiment, a chip configuration apparatus is provided, where the chip configuration apparatus corresponds to the chip configuration method in the above embodiment one by one. As shown in fig. 5, the chip configuration apparatus includes a grouping unit 101, a generating unit 102, a configuration unit 103, and a response unit 104. The functional modules are described in detail as follows:

For specific limitations of the chip configuration apparatus, reference may be made to the above limitations of the chip configuration method, and no further description is given here. The respective modules in the above-described chip configuration apparatus may be implemented in whole or in part by software, hardware, and combinations thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.

In one embodiment, a computer device is provided, which may be a server, and the internal structure of which may be as shown in fig. 6. The computer device includes a processor, a memory, a network interface, and a database connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes non-volatile and/or volatile storage media and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface of the computer device is for communicating with an external client via a network connection. The computer program is executed by a processor to perform functions or steps of a chip configuration method server side.

In one embodiment, a computer device is provided, which may be a client, the internal structure of which may be as shown in FIG. 7. The computer device includes a processor, a memory, a network interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface of the computer device is for communicating with an external server via a network connection. The computer program, when executed by a processor, performs a chip configuration method client-side function or step

In one embodiment, a computer device is provided comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the steps of when executing the computer program:

according to grouping information of a serial configuration structure of a module to be configured by a user, acquiring configuration files corresponding to all the groups according to the grouping information, wherein the configuration files comprise a transmission port calling file, a pin multiplexing file, a port pin connection file and a register file;

generating configuration data of the module to be configured according to the configuration file;

the configuration bus sends the configuration data to the module to be configured, and the module to be configured is configured;

and when the configuration of the module to be configured is completed, the module to be configured returns a configuration response to the configuration bus.

In one embodiment, a computer readable storage medium is provided having a computer program stored thereon, which when executed by a processor, performs the steps of:

It should be noted that, the functions or steps implemented by the computer readable storage medium or the computer device may correspond to the relevant descriptions of the server side and the client side in the foregoing method embodiments, and are not described herein for avoiding repetition.

Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the various embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions.

The above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention.

Claims

1. A chip configuration method, comprising:

2. The chip configuration method according to claim 1, wherein the dividing the module to be configured into at least two serial configuration structures includes:

3. The chip configuration method according to claim 2, wherein the dividing the modules to be configured selected by the user into a group belonging to the same type includes:

4. The chip configuration method of claim 2, wherein the packet restriction rule comprises:

5. The chip configuration method of claim 2, wherein the packet restriction rule comprises:

6. The chip configuration method according to claim 5, wherein determining configuration data of a module to be configured in the serial configuration structure, writing the configuration data into a configuration buffer module, comprises:

7. The chip configuration method according to claim 1, wherein the configuration buffer module transmits the configuration data to the module to be configured through a broadcast bus matrix, comprising:

8. A chip configuration apparatus, comprising:

9. Computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of the chip configuration method according to any of claims 1 to 7 when the computer program is executed.

10. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the steps of the chip configuration method according to any one of claims 1 to 7.