CN116055422A

CN116055422A - Device and method for controlling data packet sending sequence

Info

Publication number: CN116055422A
Application number: CN202210761010.1A
Authority: CN
Inventors: 付豪
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2022-06-29
Filing date: 2022-06-29
Publication date: 2023-05-02

Abstract

The embodiment of the application provides a device and a method for controlling a data packet sending sequence, wherein the device comprises: a data packet storage unit configured to store a plurality of types of data packets to be transmitted, and trigger transmission of the data packets to be transmitted through a read enable signal, wherein the plurality of types of data packets to be transmitted include data packets to be transmitted belonging to a first priority and data packets to be transmitted belonging to a second priority, and the transmission priority of the data packets to be transmitted belonging to the first priority is higher than that of the data packets to be transmitted belonging to the second priority; an address storage unit configured to store a storage address of the data packet to be transmitted belonging to the first priority on the data packet storage unit; a packet type storage unit configured to store a packet type of each of the data packets to be transmitted belonging to the second priority; and a counter configured to count the number of the overrunable transmit data packets.

Description

Device and method for controlling data packet sending sequence

Technical Field

The present invention relates to the field of packet processing, and in particular, embodiments of the present application relate to a method and a device for controlling a transmission sequence of a packet.

Background

Because of the sharing of the on-chip partial resources, how to coordinate the sending sequence of the data packets of the objects needing to share the shared resources is a technical problem that needs attention. For example, PCI-Express is a high-speed serial computer expansion bus standard, which has the main advantage of high data transmission rate, and can still meet the requirements of low-speed devices, and has great development potential. Conventional PCIe transaction Ordering (i.e., implementing bandwidth optimization) methods include Strong Ordering (Strong Ordering), weak Ordering (Weak Ordering) and loose Ordering (repeated Ordering), however, the prior art does not provide a technical solution for implementing such Ordering.

It is to be understood that only the efficient control of the transmission sequence of the data packets can improve the utilization of the shared resources while ensuring that the transaction is not affected.

Disclosure of Invention

An object of the embodiments of the present application is to provide an apparatus and a method for controlling a data packet transmission sequence, where the embodiments of the present application implement data packet transmission control with multiple different priorities through fewer processing units.

In a first aspect, some embodiments of the present application provide an apparatus for controlling a transmission sequence of a data packet, the apparatus including: a packet storage unit configured to store a plurality of types of packets to be transmitted, and trigger transmission of the packets to be transmitted through a read enable signal, wherein the plurality of types of packets to be transmitted include packets to be transmitted belonging to a first priority and packets to be transmitted belonging to a second priority, the transmission priority of the packets to be transmitted belonging to the first priority is higher than that of the packets to be transmitted belonging to the second priority, the packets to be transmitted belonging to the second priority include non-transcendental packets and transcendental packets, and the transmission sequence of the transcendental packets can be transcendental by the non-transcendental packets; an address storage unit configured to store a storage address of the data packet to be transmitted belonging to the first priority on the data packet storage unit; a packet type storage unit configured to store a packet type of each of the data packets to be transmitted belonging to the second priority; and a counter configured to count the number of the overrunable transmission data packets, wherein transmission order adjustment of the non-overrunable transmission data packets and the overrunable transmission data packets is achieved by controlling whether or not a next packet type is read from the packet type storage unit.

Embodiments of the present application control the transmission of multiple data packets with different transmission priorities by fewer processing units (i.e., packet type storage unit, counter, data packet storage unit, and address storage unit).

In some embodiments, the device runs a PCIe protocol, the packet types are: the data packets to be sent, which belong to the first priority, are data packets with loose ordering enabled, and the data packets to be sent, which belong to the second priority, are all data packets with loose ordering not enabled; wherein, the data packet storage unit includes: the first data packet storage module is configured to store one or more data packets to be sent, which belong to the type of the Posted packet, and trigger the data packets to be sent, which belong to the type of the Posted packet, to be sent through a first channel by a first read enable signal; the second data packet storage module is configured to store one or more data packets to be sent, which belong to the Non-post packet type, and trigger the sending of one data packet to be sent, which belongs to the Non-post packet type, through a second channel by a second read enable signal; and a third data packet storage module configured to store one or more data packets to be transmitted, which belong to the response packet type, and trigger to transmit one data packet to be transmitted, which belongs to the response packet type, through a third channel via a third read enable signal.

According to some embodiments of the application, an independent data packet storage unit is respectively arranged for one packet type, so that data packets with different priorities are conveniently stored and transmitted separately, and the data processing speed is improved.

In some embodiments, the first enable signal is generated at least when it is confirmed that the packet type read from the packet type storage unit is the casted packet type or the address storage unit stores therein a storage address of a data packet to be transmitted of the casted packet type.

Some embodiments of the present application disclose two conditions for triggering the transmission of the data of the Posted packet type, one is that the storage address of the packet type is stored in the address pool or the packet type read from the packet type storage unit is the Posted packet type, so that it can be ensured that the data packet to be transmitted belonging to the first priority and belonging to the Posted packet type and the data packet belonging to the second priority and belonging to the Posted packet type are normally transmitted.

In some embodiments, the second enable signal is generated at least when it is determined that the packet type read from the packet type storage unit is the Non-Posted packet type or the number of data packets to be transmitted belonging to the Non-Posted packet type recorded by the at least one counter is Non-zero.

Some embodiments of the present application disclose two conditions for triggering the transmission of Non-Posted packet type data, one is that a storage address of the packet type is stored in an address pool or a count value of a data packet for the packet type is Non-zero, so that it can be ensured that a data packet to be transmitted belonging to a first priority and belonging to a Non-Posted packet type and a data packet belonging to a second priority and belonging to a Non-Posted packet type are normally transmitted.

In some embodiments, the third enable signal is generated at least when it is confirmed that the packet type read from the packet type storage unit is the response packet type or the number of data packets to be transmitted of the response packet type recorded correspondingly by the at least one counter is non-zero.

Some embodiments of the present application disclose two conditions for triggering transmission of data of a response packet type, one is that a storage address of the packet type is stored in an address pool or a count value of a data packet of the packet type is non-zero, so that it can be ensured that a data packet to be transmitted belonging to a first priority and belonging to the response packet type and a data packet belonging to a second priority and belonging to the response packet type are normally transmitted.

In some embodiments, the first enable signal, the second enable signal, and the third enable signal are each generated after determining a channel credit.

Some embodiments of the present application all ensure that the data packet to be transmitted is transmitted after the corresponding channel credit is satisfied, so as to avoid blocking from affecting normal data transmission.

In some embodiments, the address storage unit includes: the first address pool storage module is configured to store the storage address of a first type of data packet to be sent on the first data packet storage module, wherein the first type of data packet to be sent is a data packet to be sent which belongs to the first priority and belongs to the class of the Posted packet; the second address pool storage module is configured to store the storage address of a second type of data packet to be sent on the second data packet storage module, wherein the second type of data packet to be sent belongs to the first priority and belongs to the Non-casted packet type data packet to be sent; and the third address pool storage module is configured to store the storage address of a third type of data packet to be transmitted on the third data packet storage module, wherein the third type of data packet to be transmitted belongs to the first priority and belongs to the response packet type data packet to be transmitted.

In some embodiments of the present application, an address storage unit is set for a packet type, so that the speed of acquiring a storage address is increased, and further, the data sending speed is increased.

In some embodiments, the apparatus further comprises: the first enabling signal generating module comprises an OR gate and an AND gate connected with the output end of the OR gate, wherein two input signals of the OR gate are as follows: whether the content of the first address pool storage module is non-empty or whether the packet type read from the packet type storage unit is the Posted packet type, and the input signal of the and gate further includes whether the communication usage of the first channel is sufficient.

In some embodiments of the present application, a logic circuit is provided that generates a first enable signal.

In some embodiments, the counter comprises: a first counter configured to perform an operation of adding 1 to a count value when the packet type read from the packet type storage unit is the Non-Posted packet type, and to perform a subtracting operation after transmitting a data packet to be transmitted belonging to the second priority and belonging to the Non-Posted packet type through the second channel; and a second counter configured to perform an operation of incrementing a count value by 1 when the packet type read from the packet type storage unit is the response packet type, and to perform a decrementing operation after transmitting a data packet to be transmitted belonging to the second priority and belonging to the response packet type through the third channel.

Some embodiments of the present application set a counter for different packet types included in the overrunable transmission data packet, so as to ensure that the overrunable transmission data packet can not be transmitted normally after being transmitted beyond transmission, and the data packet is not lost.

In some embodiments, the apparatus further comprises: the second enabling signal generating module comprises an OR gate and an AND gate connected with the output end of the OR gate, wherein two input signals of the OR gate comprise: whether the count value of the first counter is Non-zero or whether the packet type read from the packet type storage unit is the Non-Posted packet type, and the input signal of the and gate includes whether the communication usage of the second channel is sufficient.

Some embodiments of the present application also provide a logic circuit that generates a second enable signal.

In some embodiments, the apparatus further comprises: the third enabling signal generating module comprises an OR gate and an AND gate connected with the output end of the OR gate, wherein two input signals of the OR gate comprise: whether the count value of the second counter is non-zero or whether the packet type read from the packet type storage unit is the response packet type, and the input signal of the and gate further includes whether the communication usage of the third channel is sufficient.

Some embodiments of the present application provide a logic circuit that generates a third enable signal.

In some embodiments, the data packet to be transmitted of the Posted packet type belongs to the Non-overridable transmission data packet, and the data packet to be transmitted of the Non-Posted packet type and the data packet to be transmitted of the response packet type each belong to an overridable transmission data packet, wherein the packet type storage unit is configured to: if the content read from the packet type storage unit is the Non-processed packet type, detecting whether the packet type storage unit is empty, and if not, reading the next packet type in the next period; if the content read from the packet type storage unit is the response packet type, detecting whether the packet type storage unit is empty or not, and if not, reading the next packet type in the next period; and if the content read from the packet type storage unit is the Posted packet type, firstly sending a data packet to be sent belonging to the Posted packet type, and then reading the next packet type from the packet type storage unit.

According to the method and the device, the instant sending of the data packets which cannot be exceeded is achieved by controlling whether the next packet type is read from the packet type storage unit, the number of all the data packets which can be exceeded is counted, and the data packets to be sent after being exceeded can be sent smoothly.

In some embodiments, each data packet to be transmitted includes: and the packet header and the data are stored in the data packet storage unit separately.

Some embodiments of the present application consider that the header lengths included in different data packets to be transmitted are the same, and the data may be different, so that the two parts are stored separately to facilitate subsequent addressing.

In some embodiments, the apparatus further comprises: an addressing control module configured to: the addressing process for the data packet to be sent, which belongs to the first priority, comprises the steps of obtaining a storage address from the address storage unit; the addressing procedure for the data packet to be sent belonging to the second priority comprises: and skipping if the address of the data packet to be transmitted currently obtained through address accumulation belongs to the storage address in the address storage unit.

Some embodiments of the present application need to skip memory addresses of data packets belonging to a first priority when performing address accumulation for addresses corresponding to data packets in a second priority in order to avoid data reading and transmission errors.

In a second aspect, some embodiments of the present application provide a data packet sending method, which is applied to the apparatus in the first aspect, where the apparatus sets a data packet storage module, an address pool storage module, and a bus channel for each data packet to be sent of a packet type, where, for any bus channel, the data packet sending method includes: reading a storage address from an address storage unit arranged in any bus channel pair, and confirming that an upstream module corresponding to any bus channel can accept a data packet, reading a data packet to be sent from a data packet storage unit through the storage address, and sending the data packet to be sent through any bus channel, and repeating the process until the number of the storage addresses stored in the address storage unit is zero; and if the storage address stored in the address storage unit corresponding to any bus channel is confirmed to be zero, confirming that the packet type read from the packet type storage unit is a data packet to be transmitted which needs to be transmitted through any channel, and executing an addition operation on the count value of a counter corresponding to any channel or transmitting a data packet to be transmitted, which is the same as the packet type of the data packet to be transmitted, when the condition is met.

In a third aspect, some embodiments of the present application provide a method for controlling a transmission sequence of a data packet, the method including: receiving a data packet to be sent; storing the data packet to be sent; if the data packet to be sent belongs to the data packet to be sent with the first priority, independently storing a storage address, and addressing and sending the data packet to be sent according to the storage address when a first condition is met; and if the data packet to be transmitted belongs to the data packet to be transmitted with the second priority, storing the packet type of the data packet to be transmitted, and transmitting the data packet to be transmitted when the second condition is met.

In some embodiments, the addressing and transmitting the data packet to be transmitted according to the storage address when the first condition is satisfied includes: and if the channel capacity corresponding to the packet type of the data packet to be transmitted meets the requirement and the read storage address is the storage address of the data packet to be transmitted, reading the data packet to be transmitted according to the storage address and transmitting the data packet to be transmitted.

In some embodiments, the data packet to be sent belonging to the second priority includes: a non-overrunable transmission data packet and a overrunable transmission data packet, the transmission order of the overrunable transmission data packet being overrunable by the non-overrunable transmission data packet, wherein the transmitting the data packet to be transmitted when the second condition is satisfied includes: if the data packet to be sent is the non-overrunable data packet, detecting whether the credit amount of a target channel for sending the data packet to be sent is sufficient, and if the credit amount of the target channel is sufficient, reading and sending the data packet to be sent; and if the credit amount of the target channel is insufficient, waiting until the credit amount of the target channel is sufficient, and reading and transmitting the data packet to be transmitted, wherein the next packet type is not read in the process of waiting for the credit amount of the target channel to be sufficient.

In some embodiments, the sending the data packet to be sent when the second condition is met includes: if the data packet to be transmitted is the data packet which can be transmitted beyond, counting the data packet to be transmitted, detecting whether the credit amount of a target channel for transmitting the data packet to be transmitted is sufficient, if so, reading and transmitting a data packet to be transmitted, which is the same as the packet type of the data packet to be transmitted, and if not, reading the next packet type.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a diagram of a related art link relationship using PCIe devices in an X86 system;

fig. 2 is one of the block diagrams of the apparatus for controlling the transmission sequence of the data packet according to the embodiment of the present application;

FIG. 3 is a second block diagram of an apparatus for controlling a transmission sequence of a data packet according to an embodiment of the present application;

fig. 4 is a schematic diagram of a storage manner of a data packet storage unit according to an embodiment of the present application;

FIG. 5 is a first enable signal generation circuit according to an embodiment of the present disclosure;

FIG. 6 is a second enable signal generation circuit according to an embodiment of the present disclosure;

fig. 7 is a third enable signal generating circuit according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.

Term interpretation:

PCI-Express (or PCIe for short): peripheral component interconnect express, a high-speed serial computer expansion bus standard.

FIFO: first In First Out, a first-in first-out memory device.

SRAM: static Random-Access Memory, static Random Access Memory.

TLP：Transaction Layer Packet。

The related art often involves implementing memory data read-write operation or IO read-write operation through a bus, and at this time, proper data packet read-write control is required to improve the bus utilization rate on the basis of ensuring that the transaction is executed correctly. Although the related art discloses some priority control policies (for example, taking a bus employing the PCI-Express protocol as an example, which discloses three different priority control policies of Strong Ordering (Strong Ordering), weak Ordering (Weak Ordering) and Relaxed Ordering (Relaxed Ordering), the related art may also control the transmission priority of a packet by setting the value of the TC field, for example, the transmission priority of a packet with TC of 0 is highest, and the transmission priority of a packet with TC of 1-7 is sequentially lowered), the related art does not provide a specific means for implementing these priority controls, resulting in technical difficulties in implementing different priority control policies.

The policies for the various packet transmission sequences are illustratively set forth below in connection with FIG. 1 in terms of a system running the PCIe bus protocol.

Referring to FIG. 1, FIG. 1 is a link relationship of PCIe in an X86 architecture, and PCIe devices are of three types, referred to as RC/Switch/EP, respectively. The PCIe device closest to the central processor 100 is an RC device, also known as a root device 200, under which PCIe Endpoints (EPs) and PCIe switches (switches) may be attached, under which PCIe endpoints may in turn be attached. The links between the devices are all implemented according to the PCIe protocol.

That is, devices for PCIe applications include at least three classes: endpoint devices (e.g., the plurality of PCIe endpoints 210 of fig. 1), switching devices (e.g., the PCIe switch 240 of fig. 1), and root devices (e.g., the root device 200 of fig. 1). In the architecture of FIG. 1, PCIe to PCI bridge 220, PCI/PCI-X device 230, and memory 400 are also included. For example, the endpoint device includes a graphics card, a network card, a sound card, a solid state disk, and the like. The switching device is used to link various PCIe endpoint devices to form a PCIe network, and the root device is equivalent to a PCIe Host bridge.

In PCIe devices in various forms, the relationship of ordered (namely data packet sending sequence) of PCIe needs to be satisfied, the compatibility of the traditional PCI and PCI-X, AGP protocols is achieved, meanwhile, the occurrence of deadlock can be avoided, the transmission efficiency of a PCIe bus is improved, and the completion sequence of transactions is ensured to accord with the intention of a developer. Some embodiments of the present application may provide a PCIe Ordering implementation with which PCIe Ordering rules may be implemented by virtue of fewer logic units and triggers.

PCIe Ordering applies to all PCIe transaction layer packets including Mem operations, IO operations, configuration operations, and Msg operations, among others.

It should be noted that, the means for controlling the sending sequence of the data packet provided in the present application may be any one of an integrated endpoint device, a switching device, or a root device.

As known in the art, the common PCIe transaction Ordering methods include Strong Ordering (Strong Ordering), weak Ordering (Weak Ordering) and loose Ordering (Relaxed Ordering). The specific meaning of each ordering is described one by one below.

The strong ordering means that all the transactions are forcedly sent according to the arrival time, the urgency of the transactions is not distinguished, and special cases are not allowed to appear in the same view. When transactions from multiple devices are aggregated at the switch, one transaction cannot issue a transaction that would affect the sending of all subsequent transactions, resulting in transaction blocking.

The requirements for weak ordering are shown in table 1 below:

TABLE 1 Weak ranking principle Table

Whether or not the column can go beyond the row	Posted request	Non-post request	Compensation request
				Posted request	No	Yes	Yes
Non-post request	No	No	Yes
				Compensation request	No	Yes	a)Yes b)No

Table 1 characterizes whether or not a mutual override can be made between a post (of the post packet type), a Non-post (of the Non-post packet type) and a Completion request (of the response packet type), where Yes indicates that a override can be made and No indicates that a override cannot be made, where the override of a Completion occurs between two different Transaction IDs, and the completions between the same transactions cannot be made to override each other. Weak ordering can avoid meaningless blocking and improve system performance compared to strong ordering.

The third is a relaxed Ordering, i.e., a Relay Ordering, which is attached to the PCIe transaction layer header (i.e., the relaxed Ordering mode is enabled by setting the RO field in the header), and a Relay Ordering set TLP request (corresponding to one packet) may override any other TLP request (corresponding to one packet). It will be appreciated that in some embodiments of the present application, a set RO type of data packet to be sent is defined as a data packet to be sent belonging to a first priority, while all other data packets to be sent that do not set ROs are data packets to be sent belonging to a second priority.

It should be noted that, the apparatus for controlling the packet transmission sequence provided in some embodiments of the present application may be used to implement loose ordering weak ordering, or may be used to implement packet sequential transmission control of different TC levels. The present application does not limit the specific types of the packets to be transmitted belonging to the first priority and the packets to be transmitted belonging to the second priority, nor the specific types of the packets to be transmitted belonging to the second priority, which include the packets to be transmitted that can be transcendentally transmitted and the packets to be transmitted that cannot be transcendentally transmitted. For example, a person skilled in the art may define which packets to be transmitted belong to the packets to be transmitted of the first priority, which packets to be transmitted belong to the packets to be transmitted of the second priority, which packets to be transmitted belong to the transcendental transmission packets and which packets to be transmitted belong to the non-transcendental transmission packets according to the difference of specific application scenarios.

An apparatus for controlling transmission of a data packet according to some embodiments of the present application is described below with reference to fig. 2. For example, the apparatus as described above may be integrated on a PCIe application device.

As shown in fig. 2, an apparatus 300 for controlling data packet transmission according to some embodiments of the present application is provided, where the apparatus 300 includes: a packet storage unit 310, an address storage unit 320, a packet type storage unit 330, and at least one counter 340.

A packet storage unit 310 configured to store a plurality of types of packets to be transmitted, and trigger to transmit the packets to be transmitted through a read enable signal, where the plurality of types of packets to be transmitted include packets to be transmitted belonging to a first priority and packets to be transmitted belonging to a second priority, the packets to be transmitted belonging to the first priority have a higher transmission priority than the packets to be transmitted belonging to the second priority, and the packets to be transmitted belonging to the second priority include non-transcendental packets and transcendental packets, and the transmission order of the transcendental packets may be transcendental by the non-transcendental packets.

For example, in some embodiments of the present application, when a PCIe protocol is run by a device to which a device controlling a transmission order of data packets belongs, a data packet to be transmitted belonging to a first priority is a data packet to be transmitted that is set by RO (i.e., a loosely ordered model is enabled), a data packet to be transmitted belonging to a second priority is a data packet to be transmitted that is not set by RO (i.e., a loosely ordered model is not enabled), a data packet to be transmitted belonging to a Non-overridable transmission data packet that is a posted packet type, and a data packet to be transmitted belonging to a overridable transmission data packet that includes a Non-posted packet type and a response packet type.

For example, in some embodiments of the present application, a device to which a device controlling a transmission sequence of a packet runs a PCIe protocol, and a transmission priority of each packet to be transmitted is characterized by a value of a TC field in a PCIe frame header, a number of stages of setting the transmission priority by TC is generally eight (e.g., a value of TC is from 0 to 7), and if a value of TC is assumed to be 0, a highest transmission priority corresponds to and a transmission priority of the corresponding packet to be transmitted is lower as the value of TC increases, packets to be transmitted belonging to the first priority are all packets to be transmitted having a TC field of 0, and packets to be transmitted belonging to the second priority are all packets to be transmitted having a TC of 1 to 7. It can be understood that, among the packets to be transmitted belonging to the second priority, the packets to be transmitted having TC value 1 are non-overrunable packets, because the remaining packets to be transmitted having TC values 2 to 7 can be all overruned by the packets to be transmitted having TC value 1, and the remaining packets to be transmitted having TC values 2 to 7 can be regarded as overrunable packets.

In some embodiments of the present application, a separate packet storage unit is provided for each packet type of packet to be transmitted. For example, if the PCIe protocol is used by the device for controlling data packet transmission, the packet types are a post packet type, a Non-post packet type, and a response packet type, and in some embodiments of the present application, the data packet storage units include three independent data packet storage units, and each storage unit corresponds to a channel. In some embodiments of the present application, all packet types of data to be transmitted may be stored on one packet storage unit.

It should be noted that, the packet storage unit may be an addressable storage unit such as SRAM or DRAM, and the embodiment of the present application is not limited to a specific storage medium type of the packet storage unit.

An address storage unit 320 configured to store a storage address of the data packet to be transmitted belonging to the first priority on the data packet storage unit.

For example, each data packet to be transmitted is stored on the SRAM memory unit and the memory address of each data packet to be transmitted belonging to the first priority is acquired on the SRAM memory unit, and these memory addresses are stored on the address memory unit 320. It can be appreciated that, in some embodiments of the present application, if the loose ordering model is started, the storage addresses may be directly read from the address storage unit 320 in sequence and the corresponding data packets to be sent may be sent, so that it may be ensured that when the channel capacity is sufficient, the data packets to be sent belonging to the first priority may be sent preferentially.

And a packet type storage unit configured to store the packet type of each of the data packets to be transmitted belonging to the second priority.

For example, in some embodiments of the present application, the device that controls the sending of the data packet employs PCIe protocol, and the packet types of the data packet to be sent include: a Posted packet type, a Non-Posted packet type, and a response packet type.

It may be understood that, in the embodiment of the present application, packet types of the to-be-transmitted data packet belonging to the first priority and the to-be-transmitted data packet belonging to the second priority respectively include: a Posted packet type, a Non-Posted packet type, and a response packet type.

It should be noted that, since the data packets to be transmitted belonging to the second priority may be sent beyond the data packets to be transmitted belonging to the first priority, in some embodiments of the present application, the packet type storage unit needs to sequentially store the received packet types of the data packets to be transmitted belonging to the second priority. In order to achieve a weak ordering of the data to be transmitted of the second priority, a first-in first-out FIFO memory unit may be employed as the packet type memory unit.

A counter configured to count the number of overrun-transmittable data packets. That is, only the packet type storage unit is required to store the data packet to be transmitted corresponding to the non-overrunable transmission data packet, and the number of the data packets to be transmitted that are not transmitted is not required to be counted.

For example, the data packet to be transmitted may include N data packets to be transmitted with more than N packet types, and N counters are correspondingly set to count the data packets to be transmitted with various packet types, where N is an integer greater than or equal to 2. For example, if the transmission packet includes a Non-Posted packet type of packet to be transmitted and a response packet type of packet to be transmitted, the Non-Posted packet counter and the response packet counter may be set correspondingly.

It should be noted that, some embodiments of the present application implement the transmission sequence adjustment of the non-overridable transmission data packet and the overridable transmission data packet by controlling whether to read the next packet type from the packet type storage unit.

The modules of fig. 2 are exemplarily described below by taking an apparatus for transmitting a control packet running the PCIe protocol as an example. In the following example, the device controlling data packet transmission runs PCIe protocol bus protocol, and the corresponding packet type is: the data packets to be sent belonging to the first priority are data packets with loose ordering enabled, and the data packets to be sent belonging to the second priority are all data packets with loose ordering disabled.

To enhance the transmission process for different packet types, in some embodiments of the present application, the packet storage unit 310 illustratively includes: a first packet storage module (not shown), a second packet storage module (not shown), and a third packet storage module (not shown). The packet storage modules are described one by one.

The first data packet storage module is configured to store one or more data packets to be sent, which belong to the type of the Posted packet, and trigger the sending of one data packet to be sent, which belongs to the type of the Posted packet, through a first channel by a first read enable signal.

The first enable signal is generated at least when it is confirmed that the packet type read from the packet type storage unit is the stored address of the data packet to be transmitted of the stored packet type or the stored address of the stored packet type is stored in the address storage unit.

And the second data packet storage module is configured to store one or more data packets to be transmitted, which belong to the Non-disposed packet type, and trigger the transmission of one data packet to be transmitted, which belongs to the Non-disposed packet type, through a second channel by a second read enable signal.

The second enable signal is generated at least when it is determined that the packet type read from the packet type storage unit is the Non-processed packet type or the number of data packets to be transmitted, which belong to the Non-processed packet type and are recorded correspondingly by the counter, is Non-zero.

In some embodiments of the present application, the second enable signal is generated by a second enable signal generating module, and the structure of the second enable signal generating module will be described in the following examples, which are not repeated herein.

And the third data packet storage module is configured to store one or more data packets to be transmitted, which belong to the response packet type, and trigger the transmission of one data packet to be transmitted, which belongs to the response packet type, through a third channel by a third read enable signal.

In order to improve the data reading efficiency, in some embodiments of the present application, each data packet to be sent includes: and the packet header and the data are stored in the data packet storage unit separately. That is, the first packet storage module, the second packet storage module, and the third packet storage module may store the packet header and the data separately. The storage mode will be described with reference to the drawings, and will not be repeated here.

The third enable signal is generated at least when it is determined that the packet type read from the packet type storage unit is the response packet type or the number of data packets to be transmitted of the response packet type recorded correspondingly by the counter is non-zero.

In some embodiments of the present application, the third enable signal is generated by a third enable signal generating module, and the structure of the third enable signal generating module will be described in the following examples, which are not repeated herein.

It is understood that the first enable signal, the second enable signal, and the third enable signal are generated after determining the channel credits.

In order to address the data packets to be sent of different packet types more conveniently, in some embodiments of the present application, an address storage unit is set for each data packet to be sent of a packet type. For example, in some embodiments of the present application the address storage unit 320 includes: a first address pool storage module (not shown), a second address pool storage module (not shown), and a third address pool storage module (not shown). The function of each address storage module is exemplarily described below.

The first address pool storage module is configured to store the storage address of a first type of data packet to be sent on the first data packet storage module, wherein the first type of data packet to be sent is a data packet to be sent which belongs to the first priority and belongs to the type of the Posted packet.

The second address pool storage module is configured to store the storage address of a second type of data packet to be sent on the second data packet storage module, wherein the second type of data packet to be sent belongs to the first priority and belongs to the Non-casted packet type data packet to be sent.

And the third address pool storage module is configured to store the storage address of a third type of data packet to be transmitted on the third data packet storage module, wherein the third type of data packet to be transmitted belongs to the first priority and belongs to the response packet type data packet to be transmitted.

For the convenience of recording the number of packet types included in the overrun-transmittable data packet, an independent counter is set for each packet type belonging to the overrun-transmittable data packet. For example, the counter 340 includes: a first counter (not shown) and a second counter (not shown).

A first counter configured to perform an operation of adding 1 to a count value when the packet type read from the packet type storage unit is the Non-Posted packet type, and to perform a subtracting operation after transmitting a data packet to be transmitted belonging to the second priority and belonging to the Non-Posted packet type through the second channel.

And a second counter configured to perform an operation of adding 1 to a count value when the packet type read from the packet type storage unit is the response packet type, and to perform a subtracting operation after transmitting a data packet to be transmitted belonging to the second priority and being the response packet type through the third channel.

The structure of each enable signal generation module is exemplarily described below in connection with a plurality of address storage units and counters.

It should be noted that, the data packet to be sent of the type of the Posted packet belongs to the Non-overtaking transmission data packet, and the data packet to be sent of the type of the Non-Posted packet and the data packet to be sent of the type of the response packet both belong to the overtaking transmission data packet. The function of the packet type storage unit is exemplarily described below. For example, the packet type storage unit is configured to: if the content read from the packet type storage unit is the Non-casted packet type, detecting whether the packet type storage unit is empty, and if not, performing the next reading in the next cycle (namely reading the next packet type whether a data packet to be sent of the Non-casted packet type is sent or not); if the content read from the packet type storage unit is the response packet type, detecting whether the packet type storage unit is empty, and if not, performing the next reading in the next period (namely, reading the next packet type whether a data packet to be transmitted of the response packet type is transmitted or not); and if the content read from the packet type storage unit is the Posted packet type, firstly sending a data packet to be sent belonging to the Posted packet type, and then reading the next packet type from the packet type storage unit.

It will be appreciated that, by adopting the above technical solutions according to some embodiments of the present application, when the packet type is read from the packet type storage unit, a data packet to be sent belonging to the post type is sent, so that it is ensured that the data packets are not overridden by Non-post data packets and response data packets belonging to the data packet to be sent of the second priority. For reading the Non-Posted packet type or the response packet type, if the data cannot be sent (the upstream module cannot accept the data packet), the next packet type is directly read, and if the next read packet type is the Posted packet type, the data packet to be sent of the Posted packet type is sent in advance over the data packet corresponding to the Non-Posted packet type or the response packet type.

It may be appreciated that, in some embodiments of the present application, the apparatus for controlling the sending sequence of the data packets further includes: an addressing control module configured to: the addressing process for the data packet to be sent, which belongs to the first priority, comprises the steps of obtaining a storage address from the address storage unit; the addressing procedure for the data packet to be sent belonging to the second priority comprises: and skipping if the address of the data packet to be transmitted currently obtained through address accumulation belongs to the storage address in the address storage unit.

An apparatus for controlling the transmission sequence of data packets is exemplarily described below with reference to fig. 3. It will be appreciated that processing for PCIe order occurs at one TC (Traffic Class), and that there is no processing for order between different TCs. The packet type of a PCIe packet (as a specific example of a data packet to be transmitted), i.e., a TLP packet, is: three types, posted, non-Posted, completion (i.e., response packet type).

The implementation structure of the apparatus for controlling the sending sequence of the data packet according to some embodiments of the present application is shown in fig. 3.

The packet storage unit of fig. 3 includes: a posted packet storage unit (i.e., a first packet storage module), a Non-posted packet storage unit (i.e., a second packet storage module), and a response packet storage unit (i.e., a third packet storage module).

The packet storage units of fig. 3 store the data packets to be transmitted in a manner of separately storing packet headers and data. For example, as shown in fig. 4, the TLP content (i.e. a data packet to be sent is received), the packet header of the TLP is stored in the P header storage unit, the data of the TLP is stored in the P data storage unit, then the packet header can be read first when the data packet to be sent is read, and then the corresponding data portion is read according to the length information hole P data storage unit carried in the packet header.

For example, if a packet to be sent is a TLP, the TLP includes a header with a storage unit size of W128xD64 and data with a storage unit size of W128xD1024. Since the header of the TLP has two lengths, 96bits and 128bits, respectively, and the data may have a length of 0Bytes to 4096Bytes, typically 0Bytes to 512Bytes. Taking 512bytes as an example, a TLP occupies one header storage unit and 16 data storage units; when writing, writing a header into the header storage unit, and writing data into the data storage unit in sequence; when reading, reading a header, and acquiring the data number to be read according to the length information in the header, wherein length is 32/128 the data number to be read.

As can be seen from fig. 3, the Post packet storage unit is configured to send a Post channel read enable signal (i.e., a first enable signal) for triggering the Post channel (i.e., a first channel) to send a TLP packet, that is, send out a TLP packet corresponding to the Post channel under the triggering of the Post channel read enable signal. The Non-Post packet storage unit is configured to trigger the Non-Post packet storage unit to send a Non-Post channel read enable signal (i.e., a second enable signal) of a TLP packet through the Non-Post channel (i.e., the second channel), that is, send a TLP packet corresponding to the Non-Post channel under the triggering of the Non-Post channel read enable signal. The response packet storage unit sends a response channel read enable signal (i.e., a third enable signal) for a TLP packet through a response packet channel (i.e., a third channel), that is, sends out a TLP packet corresponding to the response packet channel under the triggering of the response channel read enable signal.

The address storage unit of fig. 3 includes: a poled address storage unit (i.e., a first address pool storage module), a Non-poled address storage unit (i.e., a second address pool storage module), and a response packet address storage unit (i.e., a third address pool storage module).

Note that, the storage addresses stored in the step address storage unit in fig. 3 are addresses on the step packet storage unit, that is, each storage address stored in the step address storage unit is an address on the step packet storage unit for storing a data packet to be transmitted of each step packet type. The storage addresses stored in the Non-post address storage unit of fig. 3 are addresses on the Non-post packet storage unit, that is, each storage address stored in the Non-post address storage unit is an address on the Non-post packet storage unit for storing a data packet to be transmitted of each Non-post packet type. The storage addresses stored in the response packet address storage unit of fig. 3 are addresses on the response packet storage unit, that is, each storage address stored in the response packet address storage unit is an address on the response packet storage unit for storing a data packet to be transmitted of each response packet type.

The packet type storage unit of fig. 3 sequentially reads the stored packet types under the trigger of the read enable signal, for example, the packet type storage unit may issue a Posted packet type, a Non-Posted packet type, and a response packet type under the trigger of the read enable signal.

The counter of fig. 3 includes a Non-Posted packet counter 341 (corresponding to the first counter, or simply referred to as NP counter) and a response packet counter 342 (i.e., the second counter, or simply referred to as CPL counter), and if the packet type read from the packet type storage unit at the current time (corresponding to the read instruction being ReadType) is a Non-Posted packet type, the Non-Posted packet counter performs a 1-up operation. And if the packet type read from the packet type storage unit at the current moment (corresponding to the read instruction is ReadType) is the response packet type, executing the 1 adding operation by the response packet counter. If the packet type read from the packet type storage unit at the current moment (the corresponding read instruction is ReadType) is of a Post packet type, reading a data packet to be transmitted from the Post packet storage unit to transmit when waiting for the Post channel to transmit data, and reading the next packet type from the packet type storage unit to perform corresponding processing only after the data packet is successfully transmitted.

The generation logic of the read enable signals for the channels of FIG. 3 is described in exemplary fashion below in conjunction with FIGS. 5-7.

As shown in fig. 5, the diagram generates a first enable signal generation circuit 315 that generates Post channel read enables.

The first enable signal generating circuit 315 includes an or gate and an and gate connected to an output end of the or gate, where two input signals of the or gate are: whether the content of the first address pool storage module is non-empty (for example, if the post address pool stored by the first address pool storage module is not empty, the corresponding input signal is 1) or whether the packet type read from the packet type storage unit is the Posted packet type (for example, if the packet type read from the packet type storage unit is a Posted packet type, i.e., readtype=p, the input signal is 1), the input signal of the and gate further includes whether the communication usage of the first channel (for example, the first channel is abbreviated as P in fig. 5) is sufficient (for example, the input signal is 1 if the P channel is sufficient). The output of the first enable signal generating module is a casted channel read enable signal, which can be used as a trigger signal for triggering the casted packet storage unit in fig. 3 to read data.

As shown in fig. 6, which is a second enable signal generation circuit 316 that generates Non-Post channel read enables.

The second enable signal generating circuit 316 of fig. 6 includes an or gate and an and gate connected to the output terminal of the or gate, wherein two input signals of the or gate include: whether the count value of the first counter is Non-zero (for example, if the count value of the first counter (i.e., the NP counter is not empty) is Non-zero, the corresponding input signal is 1), or whether the content of the second address pool storage module is Non-empty (for example, if the Non-post address stored in the second address pool storage module is Non-empty (i.e., the Non-post address pool corresponding to the Non-post address storage unit is not empty), the corresponding input signal is 1), and the input signal of the and gate includes whether the communication usage of the second channel (characterized as the NP channel) is sufficient (for example, the input signal is 1 when the NP channel usage is sufficient). The output of the second enable signal generating module is a Non-casted channel read enable signal, which can be used as a trigger signal for triggering the Non-casted packet storage unit in fig. 3 to perform data reading.

As shown in fig. 7, which is a second enable signal generation circuit 317 that generates Non-Post channel read enables.

The third enable signal generating circuit 317 of fig. 7 includes an or gate and an and gate connected to the output terminal of the or gate, wherein two input signals of the or gate include: whether the count value of the second counter is non-zero (for example, if the count value of the second counter (i.e., the CPL counter is not empty) is non-zero, the corresponding input signal is 1), or whether the content of the third address pool storage module is non-empty (for example, if the response packet address stored in the third address pool storage module is non-empty (i.e., the response packet address pool corresponding to the response packet address storage unit is not empty), the corresponding input signal is 1), and the input signal of the and gate includes whether the communication usage of the third channel (characterized as the CPL channel) is sufficient (for example, if the communication usage of the CPL channel is sufficient, the input signal is 1). The output of the third enable signal generating module is a response channel read enable signal, which can be used as a trigger signal for triggering the response packet storage unit in fig. 3 to perform data reading.

An implementation of the control packet transmission method is exemplarily described below with reference to fig. 3.

The first step: when a TLP packet for PCIe is received at a certain time, three kinds of information can be obtained:

(1) By parsing the header field of PCIe, it is possible to obtain which packet type, i.e., packet type information, the current TLP packet belongs to, is not-casted, and is a response packet.

As can be seen from the above description of some embodiments of the present application, if the TLP packet belongs to the data packet to be sent of the second priority (i.e. the RO field in the header is not set), the packet type information needs to be stored in the packet type storage unit of fig. 3.

(2) Header (i.e., header portion included in a TLP packet) and payload (i.e., data portion included in a TLP packet) information, which are stored in a packet storage unit, a Non-packet storage unit, or a response packet storage unit provided in fig. 3, respectively, according to packet type. For example, the three packet memory cells of fig. 3 may be implemented by static random access memory SRAM.

(3) If the bit corresponding to RO (Relax pattern) of the TLP is found to be set (i.e., the bit has a value of 1) (corresponding to the data packet to be sent belonging to the data packet to be sent of the first priority), the address information of the written SRAM is stored in the corresponding address pool, that is, stored in one of the three address storage units included in fig. 3 according to the packet type. That is, the three address storage units of fig. 3 are respectively used for storing three types of address pools, and the three address pools are respectively used for storing the ordered and Non-Posted, completion SRAM write addresses (i.e., the storage values on the corresponding packet storage units) of the RO bit, and when the RO bit of the TLP is not set (the corresponding packet to be sent belongs to the second-priority packet to be sent), the address pools are not written, that is, the storage addresses of the packets to be sent on the corresponding packet storage units are not stored.

Second, the transmission process of the TLP for the RO bit set is as follows:

because the RO bit set TLP may override any TLP, the RO bit set TLP has the highest priority. When the pool of the post/Non-post/Completion addresses is not empty (i.e. the addresses stored in the corresponding packet type of the local storage unit are not empty), the priority is highest, irrespective of the ordering management with other channels, if the credit of the current channel of the upstream module is sufficient (i.e. the upstream module has capacity to accept the TLP packet at this time), the address obtained from the pool of addresses is used as the read address of the SRAM, and the corresponding TLP is read from the SRAM (i.e. the corresponding packet storage unit) and sent out. The read address is recorded at the same time so that the address is skipped when the read address of the non-RO is updated.

Third, the transmission process of the TLP for the non-RO bit set is as follows:

(a) The TLP is sent to the SRAM of the corresponding channel (i.e., the packet header and data portion of the TLP are stored on the packet storage unit of the corresponding packet type), but the write address of the SRAM (the storage address on the packet storage unit) is not sent to the address pool (i.e., the address storage unit of the corresponding packet type), but the TLP type information (i.e., the packet type of the data packet to be sent) is sent to the packet type storage unit.

(b) When the packet type storage unit is not empty, a first read occurs:

when the read content of the packet type storage unit is the Non-poled packet type, the Non-poled packet counter is accumulated by 1, and meanwhile, whether the packet type storage unit is empty or not is detected, and if not, the next read is performed in the next period, namely, the stored next packet type is read.

When the content read by the packet type storage unit is the response packet type, the response packet counter is accumulated by 1, and meanwhile, whether the packet type storage unit is empty or not is detected, and if not, the next reading is performed in the next period, namely, the stored next packet type is read.

When the read content of the packet type storage unit is of a Posted type, the next read is not immediately performed, at the moment, whether the credit amount of a Posted channel is sufficient or not is detected, if so, a Posted TLP is read from the SRAM, at the moment, the next read is performed in the next period when the packet type storage unit is detected to be non-empty; if not, the SRAM read is always waited for when the credit is sufficient, during which no new data is read from the packet type storage unit, i.e. the stored next packet type is read.

Various types of reading conditions are shown in fig. 5-7, and are not repeated here.

(c) For Non-RO bit set response packets and Non-post TLPs (i.e., packets to be sent belonging to the second priority class), when it is detected that the corresponding channel credits are sufficient and the current Completion counter (corresponding to the second counter) and Non-post counter (corresponding to the first counter) are not 0, SRAM read (i.e., packets to be sent are read from the corresponding packet storage unit) occurs, and the read TLP is sent to the upper layer while the corresponding counter count value is decremented by 1.

Note that, for the SRAM of the post, non-Posted, completion (i.e., packet storage units of various packet types), TLPs set for ROs (i.e., packets to be transmitted belonging to the first priority) and TLPs set for Non-ROs (i.e., packets to be transmitted belonging to the second priority) are shared, and thus the read pointers of the three types of SRAMs (i.e., three packet storage units) are configured to: processing of the TLP for RO set: adopting the value read out from the address pool; TLP processing for non-RO set: the addresses are accumulated as needed, and skipped when encountering an address in the address pool. To avoid repeated reads of the TLP set for RO.

For example, the control manner of the read pointer is exemplarily described below using the Post channel as an example.

If 10 packets to be transmitted of the class of the Posted packet are received in a cumulative way, the packets are stored in a Posted packet storage unit according to the receiving order, and the storage addresses on the storage unit are respectively 0-9, wherein the storage addresses of 1 st, 5 th and 7 th are stored as the packets to be transmitted of the RO class (namely, the packets to be transmitted belonging to the first priority), and the rest of the storage addresses are stored as the packets to be transmitted belonging to the second priority. When performing Post readout (i.e. reading each stored data packet to be transmitted from the Post packet storage unit), the read pointer is maintained as follows:

firstly, address 0 is selected, address 0 is compared with the RO address pool, and 0 and 1/5/7 are not matched, which means that the Post of address 0 is not of RO type and is not read yet, and at this time, the Post TLP of address 0 is read. While updating the read pointer to address 1.

When the read enable condition is satisfied for the second time, address 1 is compared with the RO address pool, a match occurs at this time, indicating that the contents of address 1 is a TLP of RO type and has been read away, then the read pointer is incremented to 2, and address 2 is again compared with the RO address pool, and no match occurs, indicating that the Post of address 2 is not of RO type and has not yet been read away, at this time the Post TLP of address 2 is read, and the read pointer is updated to address 3.

And (5) sequentially and circularly carrying out. It should be noted that when the address pointed to by the read pointer matches the address pool and the read pointer is accumulated, the matching pointer content in the address pool needs to be cleared.

It will be appreciated that the above implementation can implement a weak Ordering and a relaxed Ordering of PCIe order: for a TLP set by RO, no blocking transmission can be performed, as long as the Credit of the current channel is sufficient; for Non-RO set poled TLPs, it is guaranteed that subsequent Non-poled and Completion TLPs will not override the poled TLPs. For Non-RO set Non-poled and Completion TLPs, it is guaranteed that the previous poled TLPs are not exceeded, but when the current Non-poled and Completion TLPs are blocked due to insufficient Credit, they are incremented in the corresponding counters, and the subsequent poled TLPs may override the currently blocked Non-poled and Completion TLPs.

Some embodiments of the present application provide a data packet transmission method, which may be applied to the apparatus for controlling the data transmission sequence of the present application as described in the above embodiments. The operation of the device, i.e. the process of transmitting data, will be exemplarily described below using any bus channel as an example. It should be noted that, the device for controlling the sending sequence of the data packets corresponding to the following method sets a data packet storage module, an address pool storage module and a bus channel for each data packet to be sent of each packet type, where, for any bus channel, the data packet sending method includes:

Reading a storage address from an address storage unit arranged in any bus channel pair, and confirming that an upstream module corresponding to any bus channel can accept a data packet, reading a data packet to be sent from a data packet storage unit through the storage address, and sending the data packet to be sent through any bus channel, and repeating the process until the number of the storage addresses stored in the address storage unit is zero;

and if the storage address stored in the address storage unit corresponding to any bus channel is confirmed to be zero, confirming that the packet type read from the packet type storage unit is a data packet to be transmitted which needs to be transmitted through any channel, and executing an addition operation on the count value of a counter corresponding to any channel or transmitting a data packet to be transmitted, which is the same as the packet type of the data packet to be transmitted, when the condition is met.

Details of implementation of each step involved in the method and meanings of related terms may refer specifically to corresponding content in the device for sending control data packets, so that the method will not be described in detail herein to avoid redundancy.

Some embodiments of the present application also provide a method of controlling a transmission sequence of a packet, the method exemplarily illustrating a method performed by the apparatus for controlling a transmission sequence of a packet provided by the above embodiments from two steps of storing and reading, the method of controlling a transmission sequence of a packet including:

Receiving a data packet to be sent;

storing the data packet to be sent;

if the data packet to be sent belongs to the data packet to be sent with the first priority, further storing a storage address, and addressing and sending the data packet to be sent according to the storage address when a first condition is met;

and if the data packet to be transmitted belongs to the data packet to be transmitted with the second priority, storing the packet type of the data packet to be transmitted, and transmitting the data packet to be transmitted when the second condition is met.

In some embodiments of the present application, the addressing and sending the data packet to be sent according to the storage address when the first condition is satisfied includes: and if the channel capacity corresponding to the packet type of the data packet to be transmitted meets the requirement and the read storage address is the storage address of the data packet to be transmitted, reading the data packet to be transmitted according to the storage address and transmitting the data packet to be transmitted.

In some embodiments of the present application, the data packet to be sent that belongs to the second priority includes: a non-overrunable transmission data packet and a overrunable transmission data packet, the transmission order of the overrunable transmission data packet being overrunable by the non-overrunable transmission data packet, wherein the transmitting the data packet to be transmitted when the second condition is satisfied includes: if the data packet to be sent is the non-overrunable data packet, detecting whether the credit amount of a target channel for sending the data packet to be sent is sufficient, and if the credit amount of the target channel is sufficient, reading and sending the data packet to be sent; and if the credit amount of the target channel is insufficient, waiting until the credit amount of the target channel is sufficient, and reading and transmitting the data packet to be transmitted, wherein the next packet type is not read in the process of waiting for the credit amount of the target channel to be sufficient.

In some embodiments of the present application, the sending the data packet to be sent when the second condition is satisfied includes: if the data packet to be transmitted is the data packet which can be transmitted beyond, counting the data packet to be transmitted, detecting whether the credit amount of a target channel for transmitting the data packet to be transmitted is sufficient, if so, reading and transmitting a data packet to be transmitted, which is the same as the packet type of the data packet to be transmitted, and if not, reading the next packet type.

In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other manners as well. The apparatus embodiments described above are merely illustrative, for example, flow diagrams and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, the functional modules in the embodiments of the present application may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application, and various modifications and variations may be suggested to one skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Claims

1. An apparatus for controlling transmission of data packets, the apparatus comprising:

a packet storage unit configured to store a plurality of types of packets to be transmitted, and trigger transmission of the packets to be transmitted through a read enable signal, wherein the plurality of types of packets to be transmitted include packets to be transmitted belonging to a first priority and packets to be transmitted belonging to a second priority, the transmission priority of the packets to be transmitted belonging to the first priority is higher than that of the packets to be transmitted belonging to the second priority, the packets to be transmitted belonging to the second priority include non-transcendental packets and transcendental packets, and the transmission sequence of the transcendental packets can be transcendental by the non-transcendental packets;

an address storage unit configured to store a storage address of the data packet to be transmitted belonging to the first priority on the data packet storage unit;

a packet type storage unit configured to store a packet type of each of the data packets to be transmitted belonging to the second priority; and

a counter configured to count the number of the packets to be transmitted that belong to the overrunable transmission packet;

And adjusting the sending sequence of the non-overridable sending data packet and the overridable sending data packet by controlling whether the next packet type is read from the packet type storage unit.

2. The apparatus of claim 1, wherein the apparatus runs a PCIe protocol, the packet type is: a type of a Posted packet, a Non-Posted packet type, and a type of a response packet, wherein the data packets to be transmitted belonging to the first priority are loosely ordered enabled data packets, the data packets to be transmitted belonging to the second priority are all loosely ordered disabled data packets, wherein,

the data packet storage unit includes:

the first data packet storage module is configured to store one or more data packets to be sent, which belong to the type of the Posted packet, and trigger the data packets to be sent, which belong to the type of the Posted packet, to be sent through a first channel by a first read enable signal;

the second data packet storage module is configured to store one or more data packets to be sent, which belong to the Non-post packet type, and trigger the sending of one data packet to be sent, which belongs to the Non-post packet type, through a second channel by a second read enable signal; and

3. The apparatus of claim 2, wherein the first read enable signal is generated at least upon confirming that a packet type read from the packet type storage unit is the Posted packet type or that a storage address of a data packet to be transmitted of the Posted packet type is stored in the address storage unit.

4. The apparatus of claim 2, wherein the second read enable signal is generated at least when it is confirmed that a packet type read from the packet type storage unit is the Non-Posted packet type or the number of data packets to be transmitted belonging to the Non-Posted packet type, which are recorded correspondingly by the counter, is Non-zero.

5. The apparatus of claim 2, wherein the third read enable signal is generated at least upon confirming that a packet type read from the packet type storage unit is the response packet type or that a number of data packets to be transmitted of the response packet type recorded correspondingly by the counter is non-zero.

6. The apparatus of any of claims 3-5, wherein the first read enable signal, the second read enable signal, and the third read enable signal are each generated after determining a channel credit.

7. The apparatus of any of claims 2-5, wherein the address storage unit comprises:

the first address pool storage module is configured to store the storage address of a first type of data packet to be sent on the first data packet storage module, wherein the first type of data packet to be sent is a data packet to be sent which belongs to the first priority and belongs to the class of the Posted packet;

the second address pool storage module is configured to store the storage address of a second type of data packet to be sent on the second data packet storage module, wherein the second type of data packet to be sent belongs to the first priority and belongs to the Non-casted packet type data packet to be sent;

8. The apparatus of claim 7, wherein the apparatus further comprises:

the first enabling signal generating module comprises an OR gate and an AND gate connected with the output end of the OR gate, wherein two input signals of the OR gate are as follows: whether the content of the first address pool storage module is non-empty or whether the packet type read from the packet type storage unit is the Posted packet type, and the input signal of the and gate further includes whether the communication usage of the first channel is sufficient.

9. The apparatus of claim 7, wherein the counter comprises:

a first counter configured to perform an operation of adding 1 to a count value when the packet type read from the packet type storage unit is the Non-Posted packet type, and to perform a subtracting operation after transmitting a data packet to be transmitted belonging to the second priority and belonging to the Non-Posted packet type through the second channel; and

10. The apparatus of claim 9, wherein the apparatus further comprises:

the second enabling signal generating module comprises an OR gate and an AND gate connected with the output end of the OR gate, wherein two input signals of the OR gate comprise: whether the count value of the first counter is Non-zero or whether the packet type read from the packet type storage unit is the Non-Posted packet type, and the input signal of the and gate includes whether the communication usage of the second channel is sufficient.

11. The apparatus of claim 9, wherein the apparatus further comprises:

the third enabling signal generating module comprises an OR gate and an AND gate connected with the output end of the OR gate, wherein two input signals of the OR gate comprise: whether the count value of the second counter is non-zero or whether the packet type read from the packet type storage unit is the response packet type, and the input signal of the and gate further includes whether the communication usage of the third channel is sufficient.

12. The apparatus of claim 1, wherein the packets to be transmitted of the type of the postted packet belong to the Non-overridable transmission packet, wherein the packets to be transmitted of the type of the Non-postted packet and the packets to be transmitted of the type of the response packet both belong to the overridable transmission packet, wherein,

The packet type storage unit is configured to:

if the content read from the packet type storage unit is the Non-casted packet type, detecting whether the packet type storage unit is empty, and if not, reading the next packet type in the next period;

if the content read from the packet type storage unit is the response packet type, detecting whether the packet type storage unit is empty or not, and if not, reading the next packet type in the next period;

and if the content read from the packet type storage unit is the Posted packet type, firstly sending a data packet to be sent belonging to the Posted packet type, and then reading the next packet type from the packet type storage unit.

13. The apparatus of claim 1, wherein each data packet to be transmitted comprises: and the packet header and the data are stored in the data packet storage unit separately.

14. The apparatus of claim 1, wherein the apparatus further comprises:

an addressing control module configured to:

the addressing process for the data packet to be sent, which belongs to the first priority, comprises the steps of obtaining a storage address from the address storage unit;

The addressing procedure for the data packet to be sent belonging to the second priority comprises: and skipping if the address of the data packet to be transmitted currently obtained through address accumulation belongs to the storage address in the address storage unit.

15. A data packet transmission method, applied to the device according to any one of claims 1-14, characterized in that the device is provided with a data packet storage module, an address pool storage module and a bus channel for each data packet to be transmitted of a packet type, respectively,

for any bus channel, the data packet sending method comprises the following steps:

and if the storage address stored in the address storage unit corresponding to any bus channel is confirmed to be zero, confirming that the packet type read from the packet type storage unit is a data packet to be transmitted which needs to be transmitted through any bus channel, and executing an addition operation on the count value of a counter corresponding to any bus channel or transmitting a data packet to be transmitted, which is the same as the packet type of the data packet to be transmitted, when the condition is met.

16. A method for controlling a transmission sequence of data packets, the method comprising:

receiving a data packet to be sent;

storing the data packet to be sent;

17. The method of claim 16, wherein addressing and transmitting the data packet to be transmitted according to the memory address when the first condition is satisfied comprises:

and if the channel capacity corresponding to the packet type of the data packet to be transmitted meets the requirement and the read storage address is the storage address of the data packet to be transmitted, reading the data packet to be transmitted according to the storage address and transmitting the data packet to be transmitted.

18. The method of claim 16, wherein the data packet to be transmitted belonging to the second priority comprises: a non-overrunable transmission data packet and a overrunable transmission data packet, the transmission order of which is overrunable by the non-overrunable transmission data packet, wherein,

And sending the data packet to be sent when the second condition is met, including:

if the data packet to be sent is the non-overrunable data packet, detecting whether the credit amount of a target channel for sending the data packet to be sent is sufficient, and if the credit amount of the target channel is sufficient, reading and sending the data packet to be sent; and if the credit amount of the target channel is insufficient, waiting until the credit amount of the target channel is sufficient, and reading and transmitting the data packet to be transmitted, wherein the next packet type is not read in the process of waiting for the credit amount of the target channel to be sufficient.

19. The method of claim 18, wherein the sending the data packet to be sent when the second condition is satisfied comprises:

if the data packet to be transmitted is the data packet which can be transmitted beyond, counting the data packet to be transmitted, detecting whether the credit amount of a target channel for transmitting the data packet to be transmitted is sufficient, if so, reading and transmitting a data packet to be transmitted, which is the same as the packet type of the data packet to be transmitted, and if not, reading the next packet type.