CN116048456A - Matrix multiplier, method of matrix multiplication, and computing device - Google Patents

Abstract

A matrix multiplier, a method of matrix multiplication, and a computing device, the matrix multiplier comprising: the device comprises a comparison circuit and a first operation circuit, wherein the comparison circuit is used for determining whether first target data and/or second target data are data in a first set, the first operation circuit is used for outputting a first result of multiplying the first target data and the second target data according to the fact that the first target data and/or the second target data are data in the first set, and the first set comprises: 0. 2 ⁿ N is an integer, and the first result includes: 0 or third data, wherein the third data is obtained by shifting the first target data or the second target data according to n pairs, or is obtained by shifting and inverting the first target data or the second target data according to n pairs. The matrix multiplier can save power consumption.

Description

Matrix multiplier, method of matrix multiplication and computing device

technical field

The present application relates to the field of chip design, and more particularly, to a matrix multiplier, a matrix multiplication method, and a computing device.

Background technique

Matrix multiplication (matric multiplication, MM) is one of the most important mathematical operations in modern artificial intelligence related technologies such as neural networks and machine learning. As an example, the operation of matrix multiplication can be performed by a matrix multiplier.

In the related technical solution, since many multiplication operations and addition operations are involved in the matrix multiplication, the matrix multiplier in the related technical solution includes a conventional multiplication circuit, which needs to include multiple adders, shifters, bit registers and multiple multipliers. When performing matrix multiplication, the conventional multiplication circuit has relatively high power consumption because it includes multiple adders, shifters, and multiple multipliers.

Therefore, how to reduce the power consumption of the matrix multiplier has become an urgent technical problem to be solved.

Contents of the invention

The present application provides a matrix multiplier, a matrix multiplication method and a computing device, and the matrix multiplier can save power consumption.

In a first aspect, a matrix multiplier is provided, and the matrix multiplier includes: a comparison circuit, and a first operation circuit.

A comparison circuit for determining whether the first target data and/or the second target data are data in the first set, wherein the first target data is data in the first matrix, and the second target data is the second matrix In the data, the first set includes: 0, 2 ⁿ , where n is an integer;

A first operation circuit, configured to output a first result of multiplying the first target data and the second target data according to the first target data and/or the second target data being data in the first set, the The first result includes: 0 or the third data, wherein the third data is shifted according to n pairs of the first target data or the second target data, or shifted according to n pairs of the first target data or the second target data And negate the obtained.

The above matrix multiplier can directly output the corresponding special data (for example, the data is 0 or ±2 ⁿ ) when multiplying the data in the two matrices. the result of. In this way, high power consumption caused by conventional multiplication operations can be reduced. Moreover, since the matrix multiplier performs multiplication operations on data in two matrices, a large number of operations are involved, and the benefits brought about by saving power consumption are even more considerable.

With reference to the first aspect, in some implementation manners of the first aspect, the first operation circuit is specifically configured to output the first result as 0 according to the first target data being 0.

With reference to the first aspect, in some implementations of the first aspect, the first operation circuit is specifically configured to output the first result as the third data according to the first target data being 2 ⁿ , and the third The data is obtained by shifting left or right |n| bits of the second target data.

With reference to the first aspect, in some implementations of the first aspect, the first operation circuit is specifically configured to: according to the first target data being 2 ⁿ and the n being a positive integer, the first output result is the first Three data, the third data is obtained by shifting the second target data to the left by n bits; or according to the first target data being 2 ⁿ and the n being a negative integer, the first output result is the third data, The third data is obtained by right shifting |n| bits of the second target data.

With reference to the first aspect, in some implementation manners of the first aspect, the first operation circuit is specifically configured to output the first result according to the first target data being -2 ⁿ as the third Data, the third data is obtained by shifting the second target data left or right by |n| bits and inverting it.

With reference to the first aspect, in some implementations of the first aspect, the comparison circuit is further configured to determine the first operation according to the first target data and/or the second target data as data in the first set code, wherein the value of the first operation code indicates that the first target data and/or the second target data is 0 or ±2 ⁿ ; the first operation circuit is specifically used for taking the first operation code according to value and the first target data and/or the second target data, determine that the first result is 0 or the third data.

With reference to the first aspect, in some implementations of the first aspect, the matrix multiplier further includes at least one first register, the at least one first register is respectively connected to the comparison circuit and the first operation circuit, and the at least one The first register is used to obtain the first target data and the second target data from the comparison circuit; the at least one first register is also used to output the first target data and the second target data to the first operating circuit.

With reference to the first aspect, in some implementations of the first aspect, the at least one first register is also used to obtain the first operation code from the comparison circuit, and output the first operation code to the first operation code circuit.

With reference to the first aspect, in some implementations of the first aspect, the matrix multiplier further includes at least one second register and a second operating circuit, the at least one second register is connected to the second operating circuit, and the at least one The second register is used to output the obtained first target data and the second target data when the comparison circuit determines that the first target data and the second target data are not data in the first set To the second operation circuit; the second operation circuit is used to perform a conventional multiplication operation on the received first target data and the second target data, and output the multiplication of the first target data and the second target data the second result of .

With reference to the first aspect, in some implementations of the first aspect, the matrix multiplier further includes a data selector MUX, the MUX is respectively connected to the second operating circuit and the first operating circuit, and the MUX is used to select The first result or the second result is used as the output of the matrix multiplier.

With reference to the first aspect, in some implementation manners of the first aspect, the comparison circuit is further configured to, when the comparison circuit determines that the first target data and/or the second target data are data in the first set In this case, an enable signal with a value of 1 is output to the at least one first register; the at least one first register is specifically used to combine the first target data with the first target data according to the enable signal with a value of 1. The two target data are output to the first operation circuit.

With reference to the first aspect, in some implementations of the first aspect, the matrix multiplier further includes an inversion circuit, and the inversion circuit is respectively connected to the comparison circuit and the at least one second register, and the comparison circuit is also used When the comparison circuit determines that the first target data and the second target data are not data in the first set, output an enable signal with a value of 0 to the at least one first register; the inversion A circuit, configured to perform an inversion operation on the enable signal with a value of 0 output by the comparison circuit to obtain an enable signal with a value of 1, and output the enable signal with a value of 1 to the at least one second register; the at least one second register is specifically configured to output the acquired first target data and the second target data to the second operating circuit based on the enable signal with a value of 1.

With reference to the first aspect, in some implementation manners of the first aspect, the negation circuit is a NOT gate.

With reference to the first aspect, in some implementations of the first aspect, the MUX is specifically configured to: after receiving an enable signal with a value of 1, use the first result as the output of the matrix multiplier; or After receiving the enable signal whose value is 0, the second result is used as the output of the matrix multiplier.

In a second aspect, a matrix multiplication method is provided, the method is applied to a matrix multiplier, and the matrix multiplier is used to perform matrix multiplication operations on the first matrix and the second matrix, and the method includes: the comparison circuit determines the first whether the target data and/or the second target data are data in the first set, wherein the first target data is the data in the first matrix, the second target data is the data in the second matrix, and the first A set includes: 0, ±2 ⁿ , where n is an integer; the first operating circuit outputs the first target data and the second target data according to the first target data and/or the second target data as data in the first set The first result of the multiplication of two target data, the first result includes: 0 or the third data, wherein the third data is shifted according to n pairs of the first target data or the second target data, or obtained according to n pairs of Obtained by shifting and inverting the first target data or the second target data.

With reference to the second aspect, in some implementation manners of the second aspect, the first operation circuit outputs the first result as 0 according to the first target data as 0.

With reference to the second aspect, in some implementations of the second aspect, the first operation circuit outputs the first result as the third data according to the first target data being 2 ⁿ , and the third data is for the The second target data is obtained by shifting left or right by |n| bits.

With reference to the second aspect, in some implementations of the second aspect, the first operating circuit outputs the first result as the third data according to the first target data being 2 ⁿ and the n being a positive integer, and the The third data is obtained by shifting the second target data to the left by n bits; or the first operation circuit outputs the first result as the third data according to the first target data being 2 ⁿ and the n being a negative integer , the third data is obtained by right shifting |n| bits of the second target data.

With reference to the second aspect, in some implementations of the second aspect, the first operation circuit outputs the first result according to the first target data being -2 ⁿ , and the third data is the third data for the second The target data is obtained by shifting left or right |n| bits and inverting.

With reference to the second aspect, in some implementations of the second aspect, the method further includes: the comparison circuit determines the first target data and/or the second target data as data in the first set, operation code, wherein the value of the first operation code indicates that the first target data and/or the second target data is 0 or ±2 ⁿ ; the first operation circuit according to the value of the first operation code and the The first target data and/or the second target data, the first result of determining is 0 or the third data.

With reference to the second aspect, in some implementations of the second aspect, the method further includes: at least one first register acquires the first target data and the second target data from the comparison circuit, and the at least one first register respectively It is connected with the comparison circuit and the first operation circuit; the at least one first register outputs the first target data and the second target data to the first operation circuit.

With reference to the second aspect, in some implementations of the second aspect, the method further includes: the at least one first register acquires the first operation code from the comparison circuit, and outputs the first operation code to the first operating circuit.

With reference to the second aspect, in some implementations of the second aspect, the method further includes: at least one second register, when the comparison circuit determines that neither the first target data nor the second target data is in the first set In the case of data, output the obtained first target data and the second target data to the second operation circuit, and the at least one second register is connected to the second operation circuit; A conventional multiplication operation is performed on the first target data and the second target data, and a second result of multiplying the first target data and the second target data is output.

With reference to the second aspect, in some implementations of the second aspect, the method further includes: the data selector MUX takes the first result or the second result as an output of the matrix multiplier, and the UX is respectively connected with the second The operating circuit is connected to the first operating circuit.

With reference to the second aspect, in some implementations of the second aspect, the method further includes: the comparison circuit determines that the first target data and/or the second target data are data in the first set In the case of , an enable signal with a value of 1 is output to the at least one first register; the at least one first register outputs the first target data and the second target data according to the enable signal with a value of 1 output to the first operating circuit.

With reference to the second aspect, in some implementations of the second aspect, the method further includes: the comparison circuit determines that neither the first target data nor the second target data is data in the first set when the comparison circuit determines In this case, an enable signal with a value of 0 is output to the at least one first register; enable signal, and output the enable signal with a value of 1 to the at least one second register, and the negation circuit is respectively connected to the comparison circuit and the at least one second register; the at least one second register is based on the fetch An enable signal with a value of 1 outputs the acquired first target data and the second target data to the second operating circuit.

With reference to the second aspect, in some implementation manners of the second aspect, the negation circuit is a NOT gate.

In conjunction with the second aspect, in some implementations of the second aspect, after receiving the enable signal with a value of 1, the MUX uses the first result as the output of the matrix multiplier; or the MUX receives the After receiving the enable signal whose value is 0, the second result is used as the output of the matrix multiplier.

In a third aspect, a computing device is provided, including at least one processor and at least one memory, and optionally, an input/output interface. The at least one processor is used to control the input and output interface to send and receive information, the at least one memory is used to store a computer program, and the at least one processor is used to call and run the computer program from the at least one memory, so that the computing device executes the second A method in any possible implementation of the aspect or the second aspect.

Optionally, the at least one processor may be a general-purpose processor, and may be implemented by hardware or software. When implemented by hardware, the at least one processor can be a logic circuit, an integrated circuit, etc.; when implemented by software, the at least one processor can be a general-purpose processor, by reading the software code stored in at least one memory For implementation, the at least one memory may be integrated in at least one processor, or may be located outside the at least one processor and exist independently.

In a fourth aspect, a chip is provided, and the chip includes the matrix multiplier in the first aspect or any possible implementation manner of the first aspect.

In a fifth aspect, a chip is provided, and the chip acquires an instruction and executes the instruction to implement the above-mentioned second aspect and the method in any implementation manner of the second aspect.

Optionally, as an implementation manner, the chip includes a processor and a data interface, and the processor reads instructions stored in the memory through the data interface, and executes the second aspect and any implementation manner of the second aspect. Methods.

Optionally, as an implementation manner, the chip may further include a memory, the memory stores instructions, the processor is used to execute the instructions stored in the memory, and when the instructions are executed, the processor is used to execute the first A method in any two implementation manners of the aspect and the second aspect.

In a sixth aspect, a computer program product including instructions is provided, and when the instructions are executed by a computer, the computer is made to execute the method in the above-mentioned second aspect and any one of the implementation manners of the second aspect.

In a seventh aspect, there is provided a computer-readable storage medium, including computer program instructions. When the computer program instructions are executed by a computer, the computer executes the method in any implementation manner of the above-mentioned second aspect and the second aspect. .

As an example, these computer-readable storages include, but are not limited to, one or more of the following: read-only memory (read-only memory, ROM), programmable ROM (programmable ROM, PROM), erasable PROM (erasable PROM, EPROM ), Flash memory, electrical EPROM (electrically EPROM, EEPROM) and hard drive (harddrive).

Optionally, as an implementation manner, the foregoing storage medium may specifically be a nonvolatile storage medium.

Description of drawings

FIG. 1 is a schematic block diagram of a matrix multiplier 100 provided by an embodiment of the present application.

FIG. 2 is a schematic block diagram of another matrix multiplier 200 provided by an embodiment of the present application.

Fig. 3 is a schematic block diagram of a matrix multiplication method provided by an embodiment of the present application.

FIG. 4 is a schematic block diagram of an apparatus 400 for matrix multiplication provided by an embodiment of the present application.

FIG. 5 is a schematic structural diagram of a computing device 1500 provided by an embodiment of the present application.

Detailed ways

The technical solution in this application will be described below with reference to the accompanying drawings.

The present application presents various aspects, embodiments or features in terms of a system comprising a number of devices, components, modules and the like. It is to be understood and appreciated that the various systems may include additional devices, components, modules, etc. and/or may not include all of the devices, components, modules etc. discussed in connection with the figures. In addition, combinations of these schemes can also be used.

In addition, in the embodiments of the present application, words such as "exemplary" and "for example" are used as examples, illustrations or explanations. Any embodiment or design described herein as "example" is not to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of the word example is intended to present concepts in a concrete manner.

In the embodiments of the present application, "corresponding (corresponding, relevant)" and "corresponding (corresponding)" may sometimes be used interchangeably. It should be noted that when the difference is not emphasized, the meanings they intend to express are consistent.

The business scenarios described in the embodiments of the present application are to illustrate the technical solutions of the embodiments of the present application more clearly, and do not constitute limitations on the technical solutions provided by the embodiments of the present application. With the emergence of new business scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

Reference to "one embodiment" or "some embodiments" or the like in this specification means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in other embodiments," etc. in various places in this specification are not necessarily All refer to the same embodiment, but mean "one or more but not all embodiments" unless specifically stated otherwise. The terms "including", "comprising", "having" and variations thereof mean "including but not limited to", unless specifically stated otherwise.

In this application, "at least one" means one or more, and "multiple" means two or more. "And/or" describes the association relationship of associated objects, indicating that there may be three types of relationships, for example, A and/or B, which may indicate: including the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A, B can be singular or plural. The character "/" generally indicates that the contextual objects are an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be single or multiple .

Matrix multiplication (matric multiplication, MM) is one of the most important mathematical operations in modern artificial intelligence related technologies such as neural networks and machine learning. As an example, the operation of matrix multiplication can be performed by a matrix multiplier. In the related technical solution, since many multiplication operations and addition operations are involved in the matrix multiplication, the matrix multiplier in the related technical solution includes a conventional multiplication circuit, which needs to include multiple adders, shifters, bit registers and multiple multipliers. The conventional multiplication circuit has relatively high power consumption when performing matrix multiplication operations.

In view of this, an embodiment of the present application provides a matrix multiplier, which can save power consumption of the matrix multiplier when performing matrix multiplication.

A matrix multiplier provided by an embodiment of the present application will be described in detail below in conjunction with FIG. 1 .

FIG. 1 is a schematic block diagram of a matrix multiplier 100 provided by an embodiment of the present application. As shown in FIG. 1 , the matrix multiplier 100 may include: a comparison circuit 110 and a first operation circuit 120 , and the functions of the comparison circuit 110 and the first operation circuit 120 will be described in detail below.

It should be understood that, for ease of description, the matrix multiplier 100 is used to perform matrix multiplication on the first matrix and the second matrix as an example for description below.

A comparison circuit 110, configured to obtain the first target data in the first matrix and the second target data in the second matrix, and determine whether at least one of the first target data and the second target data is in the first set data, wherein, the data in the first set may include but not limited to: 0, ±2 ⁿ , n is an integer. That is, n may be a positive integer, may also be 0, or may also be a negative integer, which is not specifically limited in this embodiment of the present application.

That is, as an example, the comparison circuit 110 may determine whether the first target data is data in the first set. As another example, the comparison circuit 110 may determine whether the second target data is data in the first set. As another example, the comparison circuit 110 may determine whether the first target data and the second target data are both data in the first set.

It should be noted that the embodiment of the present application does not specifically limit the order in which the comparison circuit 110 judges whether the first target data and/or the second target data are data in the first set, and the first target data may be judged first , or the second target data can be judged first, or the first target data and the second target data can be judged at the same time.

The first operation circuit 120 is configured to output a first result of multiplying the first target data and the second target data according to the first target data and/or the second target data as data in the first set, the first result including : 0 or third data. That is to say, the first operation circuit 120 can directly output the first target data and the second target data when the comparison circuit 110 judges that at least one of the first target data and the second target data is data in the first set. The first result of data multiplication is 0 or the third data.

It should be understood that there are many ways to implement the above third data, which is not specifically limited in this embodiment of the present application, and is specifically determined according to values of the first target data and/or the second target data. In a possible implementation manner, the third data output by the first operation circuit 120 is obtained by shifting the first target data to the left by n bits or n absolute value (|n|) bits. In another possible implementation manner, the third data output by the first operation circuit 120 is obtained by shifting the first target data to the left by n bits or n absolute value (|n|) bits and inverting it. In another possible implementation manner, the third data output by the first operation circuit 120 is obtained by right-shifting the first target data by n bits or n absolute value (|n|) bits. In another possible implementation manner, the third data output by the first operation circuit 120 is obtained by right-shifting the first target data by n bits or n absolute value (|n|) bits and inverting it. In another possible implementation manner, the third data output by the first operation circuit 120 is obtained by shifting the second target data to the left by n bits or n absolute value (|n|) bits. In another possible implementation manner, the third data output by the first operation circuit 120 is obtained by shifting the second target data to the left by n bits or n absolute value (|n|) bits and inverting it. In another possible implementation manner, the third data output by the first operation circuit 120 is obtained by right-shifting the second target data by n bits or n absolute value (|n|) bits. In another possible implementation manner, the third data output by the first operation circuit 120 is obtained by right-shifting the second target data by n bits or n absolute value (|n|) bits and inverting it.

The first result of multiplying the first target data and the second target data output by the first operation circuit 120 will be illustrated below with reference to different examples.

As an example, assuming that at least one of the first target data and the second target data is 0, the first operation circuit 120 may directly output a first result of multiplying the first target data and the second target data as 0.

For another example, assuming that the first target data is 2 ⁿ , the first operation circuit 120 may shift the second target data to the left or right by n bits to obtain third data, and use the third data as the first target data and the first target data The first result of multiplying the two target data. For example, assuming that n is a positive integer, the first operation circuit 120 may left-shift the second target data by n bits to obtain the third data. For another example, assuming that n is a negative integer, the first operation circuit 120 may right-shift the second target data by n absolute value (|n|) bits to obtain the third data. For another example, assuming that n is 0, the first operation circuit 120 can shift the second target data by 0 bits to obtain the third data, that is, the output third data is the second target data itself.

For another example, assuming that the first target data is -2 ⁿ , the first operation circuit 120 may shift the second target data to the left or right by n bits to obtain third data, and use the third data as the first target data and The first result of multiplying the second target data. For example, assuming that n is a positive integer, the first operation circuit 120 may left-shift the second target data by n bits and invert it to obtain the third data. For another example, assuming that n is a negative integer, the first operation circuit 120 may right-shift the second target data by n absolute value (|n|) bits and invert to obtain the third data. For another example, assuming that n is 0, the first operation circuit 120 can shift 0 bits of the second target data and invert to obtain the third data, that is, the output third data is the data obtained after inverting the second target data .

For another example, assuming that the second target data is 2 ⁿ , the first operation circuit 120 may shift the first target data to the left or right by n bits to obtain third data, and use the third data as the first target data and the first target data The first result of multiplying the two target data. For example, assuming that n is a positive integer, the first operation circuit 120 can shift the first target data to the left by n bits to obtain the third data. For another example, assuming that n is a negative integer, the first operation circuit 120 may right-shift the first target data by n absolute value (|n|) bits to obtain the third data. For another example, assuming that n is 0, the first operation circuit 120 can shift the first target data by 0 bits to obtain the third data, that is, the output third data is the first target data itself.

For another example, assuming that the second target data is -2 ⁿ , the first operation circuit 120 may shift the first target data to the left or right by n bits to obtain third data, and use the third data as the first target data and The first result of multiplying the second target data. For example, assuming that n is a positive integer, the first operation circuit 120 may left-shift the first target data by n bits and invert it to obtain the third data. For another example, assuming that n is a negative integer, the first operation circuit 120 may right-shift the first target data by n absolute value (|n|) bits and invert to obtain the third data. As another example, assuming that n is 0, the first operation circuit 120 can shift 0 bits of the first target data and invert to obtain the third data, that is, the output third data is the data obtained after inverting the first target data .

Optionally, in some embodiments, the comparison circuit 110 is further configured to determine an operation code (opcode) for the data in the first set according to the first target data and/or the second target data, and the operation code (opcode) The value is used to indicate that the first target data and/or the second target data is 0 or ±2 ⁿ . In this way, the first operation circuit 120 can directly determine the first result of multiplying the first target data and the second target data according to the value of the operation code (opcode) corresponding to the first target data and/or the second target data.

It should be noted that the comparison circuit 110 can determine and output an opcode according to whether the first target data and/or the second target data are 0 or ±2 ⁿ , or can also determine and output the first target data and the second target data The opcodes corresponding to the data are not specifically limited in this embodiment of the present application.

For illustration, the following takes the comparison circuit 110 to output the opcode corresponding to the first target data and the second target data respectively as an example, and describes several possible implementations of the opcode in detail.

In one example, the value of the opcode corresponding to the first target data is 0, which may be used to indicate that the first target data is 0. In this way, the first operation circuit 120 may determine that the first result of multiplying the first target data and the second target data is 0 according to the value of the opcode corresponding to the first target data is 0.

In another example, the value of the opcode corresponding to the second target data is 0, which may be used to indicate that the second target data is 0. In this way, the first operation circuit 120 may determine that the first result of multiplying the first target data and the second target data is 0 according to the value of the opcode corresponding to the second target data is 0.

In another example, the value of the opcode corresponding to the first target data is 2 ⁿ , which may be used to indicate that the first target data is 2 ⁿ . In this way, the first operation circuit 120 can shift the second target data to the left ^or right by |n| The third data is used as the first result of multiplying the first target data and the second target data. For the process of the first operating circuit 120 determining the third data according to the second target data and the value of n, please refer to the above description, and details will not be described here.

In another example, the value of the opcode corresponding to the first target data is -2 ⁿ , which may be used to indicate that the first target data is -2 ⁿ . In this way, the first operation circuit 120 can shift the second target data to the left or right by |n| bits according to the value of the opcode corresponding to the first target data is 2 ⁿ and the value of n and inverts to obtain the third data, And the third data is used as the first result of multiplying the first target data and the second target data. For the process of the first operating circuit 120 determining the third data according to the second target data and the value of n, please refer to the above description, and details will not be described here.

In another example, the value of the opcode corresponding to the second target data is 2 ⁿ , which may be used to indicate that the second target data is 2 ⁿ . In this way, the first operation circuit 120 can shift the first target data to the left or right by | ⁿ | The third data is used as the first result of multiplying the first target data and the second target data. For the process of the first operating circuit 120 determining the third data according to the first target data and the value of n, please refer to the above description, and details will not be described here.

In another example, the value of the opcode corresponding to the second target data is -2 ⁿ , which may be used to indicate that the second target data is 2 ⁿ . In this way, the first operation circuit 120 can shift the first target data to the left or right by |n| bits and invert it to obtain the third data according to the value of the opcode corresponding to the second target data is 2 ⁿ and the value of n, And the third data is used as the first result of multiplying the first target data and the second target data. For the process of the first operating circuit 120 determining the third data according to the first target data and the value of n, please refer to the above description, and details will not be described here.

Optionally, in some embodiments, the matrix multiplier 100 may further include at least one first register, and the at least one first register is connected to the comparison circuit 110 and the first operation circuit 120 respectively. Wherein, the at least one first register is used to obtain the first target data and the second target data from the comparison circuit 110 , and output the first target data and the second target data to the first operation circuit 120 . In a possible implementation manner, after the input end of at least one first register receives the first target data and the second target data from the comparison circuit 110, it can store the first target data and the second target data, and store the first target data and the second target data in its After receiving the clock control signal (clk) from the clock control unit, the clock input terminal transmits the first target data and the second target data to the first operation circuit 120 from the output terminal.

Optionally, in some embodiments, the at least one first register may also receive an opcode from the comparison circuit 110 and transmit it to the first operation circuit 120 . In a possible implementation manner, the at least one first register transmits the opcode from the output end to the first operation circuit 120 after receiving a clock control signal (clk) from the clock control unit at the clock pulse input end of the at least one first register.

It should be noted that the first target data and the second target data may be stored in the same first register, or may also be stored in different first registers, which is not specifically limited in this embodiment of the present application.

It should also be noted that the opcode may be stored in the same first register as the first target data and/or the second target data, or may also be stored in a different first register, which is not the case in this embodiment of the present application. Specific limits.

Optionally, in some embodiments, the matrix multiplier 100 may further include at least one second register and a second operation circuit, and the at least one second register is connected to the second operation circuit. Wherein, at least one second register is used for outputting the acquired first target data and second target data to the second target data when the comparison circuit 110 determines that neither the first target data nor the second target data is data in the first set. Two operation circuits; the second operation circuit is used to perform a conventional multiplication operation on the received first target data and second target data, and output a second result of multiplying the first target data and the second target data.

It should be understood that, in the above-mentioned embodiment, when the first target data and/or the second target data are data in the first set, the first operation circuit 120 can be used to output the multiplication of the first target data and the second target data and use the first result as the final output result of the matrix multiplier 100, so that the power consumption of the matrix multiplier 100 can be saved. If neither the first target data nor the second target data is the data in the first set, the second operation circuit is used to perform the multiplication operation of the first target data and the second target data to obtain a second result, and the second The result serves as the final output of the matrix multiplier 100 .

In a possible implementation process, a data selector (multiplexer, MUX) may be used to select whether to use the above-mentioned first result as the final output result of the matrix multiplier 100 or to use the above-mentioned second result as the final output result of the matrix multiplier 100 .

In the embodiment of the present application, the enable signal can be used to determine whether to use the second operation circuit to determine the result of multiplying the first target data and the second target data, or to use the first operation circuit 120 to determine the first target data and the second target data The result of the multiplication.

For example, the input terminal of at least one first register is the first target data, the second target data, the corresponding opcode and the first enable signal, and the input terminal of at least one second register is the first target data, the second target data and a second enabling signal, wherein the value of the second enabling signal is opposite to that of the first enabling signal. As an example, assuming that the first target data and/or the second target data are data in the first set, the comparison circuit 110 will output a first enable signal with a value of 1 in this case. The at least one first register outputs the first target data, the second target data and the corresponding opcode obtained from the input terminal from its output terminal according to receiving the first enable signal with a value of 1. The at least one second register will not output the first target data and the second target data obtained from its input terminal according to receiving the second enable signal with a value of 0, that is, at least one second register receives After the enable signal with a value of 0, the data at the output terminal of at least one second register remains unchanged, and the data at the output terminal is still the output data of the last clock cycle, and will not change with the change of the data at the input terminal. For another example, assuming that neither the first target data nor the second target data is data in the first set, the comparison circuit 110 will output a first enable signal with a value of 0 in this case. The at least one first register will not output the first target data, second target data and corresponding opcode obtained from its input terminal according to receiving the first enable signal with a value of 0, that is, at least one first After the register receives the enable signal with a value of 0, the data at the output of at least one first register remains unchanged, and the data at the output is still the output data of the previous clock cycle, and will not change with the change of the data at the input. Change. The at least one second register outputs the first target data and the second target data acquired from the input terminal through its output terminal according to receiving the second enable signal with a value of 1.

Optionally, in some embodiments, an operation in which the values of the first enable signal and the second enable signal are reversed may be realized by an inversion circuit. As an example, the inverting circuit is a NOT gate.

Optionally, in some embodiments, the above-mentioned MUX may also select the first result as the final output result of the matrix multiplier 100 or select the second result as the final output result of the matrix multiplier 100 according to the first enable signal. Specifically, in a possible implementation manner, the value of the first enable signal output by the comparison circuit 110 is 1, and the MUX can use the first result as the final output of the matrix multiplier 100 according to the value of the first enable signal the result of. In another possible implementation, the value of the first enable signal output by the comparison circuit 110 is 0, and the MUX can use the second result as the final output result of the matrix multiplier 100 according to the value of the first enable signal .

The above matrix multiplier can directly output the corresponding special data (for example, the data is 0 or 2 ⁿ ) when multiplying the data in the two matrices. result. In this way, high power consumption caused by conventional multiplication operations can be reduced. Moreover, since the matrix multiplier performs multiplication operations on data in two matrices, a large number of operations are involved, and the benefits brought about by saving power consumption are even more considerable.

Another matrix multiplier 200 provided by the embodiment of the present application will be described in detail below with reference to FIG. 2 . It should be understood that the example in FIG. 2 is only intended to help those skilled in the art understand the embodiment of the present application, and is not intended to limit the embodiment of the application to the specific values or specific scenarios illustrated in FIG. 2 . Those skilled in the art can obviously make various equivalent modifications or changes according to the following example given in FIG. 2 , and such modifications and changes also fall within the scope of the embodiments of the present application.

FIG. 2 is a schematic block diagram of another matrix multiplier 200 provided by an embodiment of the present application. As shown in FIG. 2 , the matrix multiplier 200 may include: a comparator 210, a register 1, a register 2, a register 3, a register 4, a first operating circuit 220, a second operating circuit 230, a MUX 240, and a NOT gate 250.

It should be noted that the embodiment of the present application does not specifically limit the number of first registers and second registers. For the convenience of description, two first registers (register 3 and register 4) and two second registers are used in Figure 2 (Register 1, Register 2) as an example to illustrate.

Referring to Fig. 2, operand A (corresponding to the first target data above) and operand B (corresponding to the second target data above) are input to comparator 210, and comparator 210 determines operand A and Whether the operand B is at least the data in the first set, and output a corresponding enable signal, wherein the data in the first set may include but not limited to: 0, ±2 ⁿ , n is an integer.

As an example, the following takes the value of operand A as 2 and the value of operand B as 3 as an example to describe each part included in the matrix multiplier 200 in detail.

Comparator 210, according to the value of operand A is the data in the first set (2 ⁿ , the value of n is 1), output operand A, the opcode corresponding to operand A (the value of opcode is 1, indicating The value of operand A is 2 ¹ ), operand B and an enable signal with value 1.

The NOT gate 250 performs an inversion operation on the enable signal output from the comparator 210 with a value of 1 to obtain an enable signal with a value of 0, and outputs the enable signal with a value of 0 to register 1 and register 2.

Register 1, the data received by its input terminal (D1) includes operand A, the enable signal received by its enable terminal (EN1) is the enable signal output by the NOT gate 250 with a value of 0, and its clock pulse input The terminal (clk 1) receives the clock signal (clk) sent by the clock control unit. When the rising edge of the clock pulse signal at the clk 1 terminal (that is, low level to high level) arrives, since the value of the enable signal is 0, the output terminal (Q1) of register 1 will not output the input terminal (D1) to receive to the operand A.

Register 2, the data received by its input terminal (D2) includes operand B, the enable signal received by its enable terminal (EN2) is the enable signal output by the NOT gate 250 with a value of 0, and its clock pulse input The terminal (clk 2) receives the clock signal (clk) sent by the clock control unit. When the rising edge of the clock pulse signal at the clk 2 terminal (that is, low level to high level) arrives, since the value of the enable signal is 0, the output terminal (Q2) of register 2 will not output the input terminal (D2) to receive to operand B.

Register 3, the data received by its input terminal (D3) includes operand A and the opcode corresponding to operand A (the value of opcode is 1, indicating that the value of operand A is 2 ¹ ), and its enable terminal (EN3 ) the value of the enable signal received is 1, and the clock pulse input terminal (clk 3) receives the clock signal (clk) sent by the clock control unit. When the rising edge of the clock pulse signal at the clk 3 terminal (that is, low level to high level) arrives, since the value of the enable signal is 1, the register 3 will correspond to the operand A of the input terminal (D3) and the operand A The opcode (the value of opcode is 1, indicating that the value of operand A is 2 ¹ ) is output from the output terminal (Q3).

Register 4, the data received by its input terminal (D4) includes operand B, the value of the enable signal received by its enable terminal (EN4) is 1, and the value received by its clock pulse input terminal (clk 4) is Clock signal (clk) from the clock control unit. When the rising edge of the clock pulse signal at the clk 4 terminal (that is, low level to high level) arrives, since the value of the enable signal is 1, register 4 transfers the operand B of the input terminal (D4) from the output terminal (Q4 ) output.

The first operation circuit 220 is used to obtain the output data from the register 3 and the register 4 . Specifically, the data acquired by the input terminal of the first operation circuit 220 includes operand A, the opcode corresponding to the operand A (the value of opcode is 1, indicating that the value of operand A is 2 ¹ ) and operand B. The first operation circuit 220 determines the value of operand A to be 2 ¹ according to the value of opcode 1, therefore, the first operation circuit 220 can shift operand B to the left by 1 bit, and shift operand B to the left The result after 1 bit is used as the output result (first result) of the output terminal of the first operation circuit 220 .

The second operation circuit 230 is used for obtaining output data from the register 1 and the register 2 . Since the output terminals of register 1 and register 2 do not output operand A and operand B, or the data output by register 1 and register 2 in the last clock cycle, the second operation circuit 230 does not perform operand A and operand B. multiplication operation. The multiplication output result (second result) at the output terminal of the second operation circuit 230 is still the calculation result of the last clock cycle.

The data received at the input terminal of MUX 240 includes the first result and the second result, and the enable signal received at the enable terminal (EN5) is an enable signal with a value of 1. The MUX 240 uses the first result output by the first operation circuit 220 as the final output result of the matrix multiplier 200 according to the enable signal whose value is 1.

For another example, the following takes the value of operand A as 5 and the value of operand B as 3 as an example to describe each part included in the matrix multiplier 200 in detail.

Comparator 210, according to the value of operand A and the value of operand B are not data in the first set (the data in the first set includes 0, 2 ⁿ , n is a positive number), comparator 210 output operation Number A, operand B, and an enable signal with a value of 1.

The NOT gate 250 performs an inversion operation on the enable signal with a value of 0 output from the comparator 210 to obtain an enable signal with a value of 1, and outputs the enable signal with a value of 1 to register 1 and register 2.

Register 1, the data received by its input terminal (D1) includes operand A, the enable signal received by its enable terminal (EN1) is the enable signal output by the NOT gate 250 with a value of 1, and its clock pulse input The terminal (clk 1) receives the clock signal (clk) sent by the clock control unit. When the rising edge of the clock pulse signal at the clk 1 terminal (that is, low level to high level) arrives, since the value of the enable signal is 1, register 1 transfers the operand A of the input terminal (D1) from the output terminal (Q1 ) output.

Register 2, the data received by its input terminal (D2) includes operand B, the enable signal received by its enable terminal (EN2) is an enable signal with a value of 1 output by the NOT gate 250, and its clock pulse input The terminal (clk 2) receives the clock signal (clk) sent by the clock control unit. When the rising edge of the clock pulse signal at the clk 2 terminal (that is, low level to high level) arrives, since the value of the enable signal is 1, register 2 transfers the operand B of the input terminal (D2) from the output terminal (Q2 ) output.

Register 3, the data received by its input terminal (D3) includes operand A, the value of the enable signal received by its enable terminal (EN3) is 0, and the value received by its clock pulse input terminal (clk 3) is Clock signal (clk) from the clock control unit. When the rising edge of the clock pulse signal at the clk 3 terminal (that is, low level to high level) arrives, since the value of the enable signal is 0, the output terminal (Q3) of register 3 will not output the input terminal (D3) to receive to the operand A.

Register 4, the data received by its input terminal (D4) includes operand B, the value of the enable signal received by its enable terminal (EN4) is 0, and the value received by its clock pulse input terminal (clk 4) is Clock signal (clk) from the clock control unit. When the rising edge of the clock pulse signal at the clk 4 terminal (that is, low level to high level) arrives, since the value of the enable signal is 0, the output terminal (Q4) of register 3 will not output the input terminal (D4) to receive to operand B.

The second operation circuit 230 is used to obtain the output operand A and operand B from register 1 and register 2 respectively, and perform a conventional multiplication operation on operand A and operand B, and obtain the result as the second operation circuit The multiplication output result (second result) at the output of 230 .

The first operation circuit 220 is used to obtain the output data from the register 3 and the register 4 . Since the output terminals of register 3 and register 4 do not output operand A and operand B, the output result (first result) of the output terminal of the first operation circuit 220 is still the result of the last clock cycle.

The data received at the input terminal of MUX 240 includes the first result and the second result, and the enable signal received at the enable terminal (EN5) is an enable signal with a value of 0. The MUX 240 uses the second result output by the second operation circuit 230 as the final output result of the matrix multiplier 200 according to the enable signal whose value is 0.

A method of matrix multiplication provided by the embodiment of the present application will be described in detail below with reference to FIG. 3 .

Fig. 3 is a schematic block diagram of a matrix multiplication method provided by an embodiment of the present application. The method is applied to a matrix multiplier for performing a matrix multiplication operation on a first matrix and a second matrix. As shown in FIG. 3, the method may include steps 310-320, and the steps 310-320 will be described in detail below.

Step 310: The comparison circuit determines whether the first target data and/or the second target data are the data in the first set, wherein the first target data is the data in the first matrix, and the second target data is the first target data The data in the second matrix, the first set includes: 0, ±2 ⁿ , where n is an integer.

Step 320: The first operating circuit outputs a first result of multiplying the first target data and the second target data according to the first target data and/or the second target data as data in the first set, and the first target data is multiplied by the second target data. A result includes: 0 or third data.

Wherein, the third data is obtained by shifting n pairs of first target data or second target data, or by shifting and inverting n pairs of first target data or second target data.

Optionally, the first operation circuit outputs the first result as 0 according to the first target data as 0.

Optionally, according to the first target data being 2 ⁿ , the first operation circuit outputs the first result as the third data, and the third data is shifted left or right by |n| of the second target data bit got.

Optionally, according to the first target data being 2 ⁿ and n being a positive integer, the first result output by the first operation circuit is the third data, and the third data is a left shift of the second target data by n bit obtained; or the first operation circuit according to the first target data is 2 ⁿ and the n is a negative integer, the output of the first result is the third data, the third data is the right of the second target data obtained by shifting |n| bits.

Optionally, according to the first target data being -2 ⁿ , the first output result of the first operation circuit is the third data, and the third data is left-shifted or right-shifted by |n| bits and Get the negation.

Optionally, the method further includes: the comparison circuit determines a first operation code according to the first target data and/or the second target data as data in the first set, wherein the first operation code is The value indicates that the first target data and/or the second target data is 0 or ±2 ⁿ ; the first operation circuit is based on the value of the first operation code and the first target data and/or the second target data , determine that the first result is 0 or the third data.

Optionally, the method further includes: at least one first register acquires the first target data and the second target data from the comparison circuit, and the at least one first register is respectively connected to the comparison circuit and the first operation circuit; The at least one first register outputs the first target data and the second target data to the first operating circuit.

Optionally, the method further includes: the at least one first register acquires the first operation code from the comparison circuit, and outputs the first operation code to the first operation circuit.

Optionally, the method further includes: at least one second register, when the comparison circuit determines that neither the first target data nor the second target data is data in the first set, the acquired first target The data and the second target data are output to a second operating circuit, the at least one second register is connected to the second operating circuit; the second operating circuit performs normal operation on the received first target data and the second target data multiplication operation, outputting a second result of multiplying the first target data and the second target data.

Optionally, the method further includes: a data selector MUX takes the first result or the second result as an output of the matrix multiplier, and the UX is respectively connected to the second operation circuit and the first operation circuit.

Optionally, the method further includes: when the comparison circuit determines that the first target data and/or the second target data are data in the first set, outputting a value of An enable signal of 1; the at least one first register outputs the first target data and the second target data to the first operating circuit according to the enable signal with a value of 1.

Optionally, the method further includes: when the comparison circuit determines that neither the first target data nor the second target data is data in the first set, outputting a value of 0 to the at least one first register the enable signal; the inversion circuit performs an inversion operation on the enable signal with a value of 0 output by the comparison circuit to obtain an enable signal with a value of 1, and outputs the enable signal with a value of 1 To the at least one second register, the inverting circuit is respectively connected to the comparison circuit and the at least one second register; the at least one second register is based on the enable signal with a value of 1, and the first target to be acquired The data and the second target data are output to the second operation circuit.

Optionally, the negation circuit is a NOT gate.

Optionally, after the MUX receives the enable signal with a value of 1, the first result is used as the output of the matrix multiplier; or after the MUX receives the enable signal with a value of 0, The second result is used as the output of the matrix multiplier.

It should be understood that the description of the method embodiment shown in FIG. 3 corresponds to the description of the matrix multiplier shown in FIG. 1 or FIG. 2 . Therefore, for parts not described in detail, reference may be made to the foregoing embodiments of the matrix multiplier.

The method provided by the embodiment of the present application is described in detail above with reference to FIG. 3 , and the embodiment of the device of the present application will be described in detail below in conjunction with FIGS. 4-5 . It should be understood that the descriptions of the method embodiments correspond to the descriptions of the device embodiments, therefore, for parts not described in detail, reference may be made to the foregoing method embodiments.

FIG. 4 is a schematic block diagram of an apparatus 400 for matrix multiplication provided by an embodiment of the present application. The device 400 can be implemented by software, hardware or a combination of both. The device 400 provided in the embodiment of the present application can realize the method flow shown in FIG. Whether the first target data and/or the second target data are the data in the first set, wherein the first target data is the data in the first matrix, the second target data is the data in the second matrix, the The first set includes: 0, ± ²ⁿ , where n is an integer; the determination module 420 is used for the first operation circuit to determine the first target data and/or the second target data as the data in the first set. The first result of multiplying the first target data and the second target data, the first result includes: 0 or third data, wherein the third data is obtained by shifting the first target data or the second target data according to n pairs , or obtained by shifting and inverting the first target data or the second target data according to n; the output module 430 is configured to output the first result.

Optionally, the determining module 420 is specifically configured to: the first operating circuit determines that the first result is 0 according to the first target data being 0.

Optionally, the determining module 420 is specifically configured to: the first operation circuit determines that the first result is the third data according to the first target data being 2 ⁿ , and the third data is left-shifted or Obtained by right shifting |n| bits.

Optionally, the determination module 420 is specifically configured to: the first operating circuit determines that the first result is the third data according to the first target data being 2 ⁿ and the n is a positive integer, and the third data is the third data for the first target data. The second target data is shifted to the left by n bits; or the first operation circuit outputs the first result according to the first target data being 2 ⁿ and the n being a negative integer, which is the third data, and the third data is the pair The second object data is shifted right by |n| bits.

Optionally, the determining module 420 is specifically configured to: the first operation circuit determines that the first result is the third data according to the first target data being -2 ⁿ , and the third data is a left shift of the second target data Or shift right |n| bits and invert to get the resulting.

Optionally, the determination module 420 is further configured to: the comparison circuit determines a first operation code according to the first target data and/or the second target data as data in the first set, wherein the first operation code The value indicates that the first target data and/or the second target data is 0 or ± ²ⁿ ; the first operation circuit according to the value of the first operation code and the first target data and/or the second target data , determine that the first result is 0 or the third data.

Optionally, the device 400 further includes: an acquisition module, configured to acquire the first target data and the second target data from the comparison circuit by at least one first register, the at least one first register is respectively connected to the comparison circuit and the second target data An operation circuit is connected; the output module 430 is also used for the at least one first register to output the first target data and the second target data to the first operation circuit.

Optionally, the obtaining module is also used for the at least one first register to obtain the first operation code from the comparison circuit; the output module 430 is also used for the at least one first register to output the first operation code to the first operating circuit.

Optionally, the device 400 further includes: a multiplication module, and the output module 430 is also used for at least one second register when the comparison circuit determines that neither the first target data nor the second target data is data in the first set Next, output the obtained first target data and the second target data to the second operation circuit, the at least one second register is connected to the second operation circuit; the multiplication module is used for the second operation circuit to receive the The first target data and the second target data perform a conventional multiplication operation to obtain a second result of multiplying the first target data and the second target data; the output module 430 is also used for the second operation circuit to output the first target data A second result of multiplying the first target data and the second target data.

Optionally, the output module 430 is also used for the data selector MUX to use the first result or the second result as an output of the matrix multiplier, and the UX is respectively connected to the second operation circuit and the first operation circuit.

Optionally, the output module 430 is further configured to output a value of An enable signal of 1; the at least one first register outputs the first target data and the second target data to the first operating circuit according to the enable signal with a value of 1.

Optionally, the device 400 further includes: an inversion module, and the output module 430 is also used for the comparison circuit to send at least A first register outputs an enable signal with a value of 0; the inversion module is used for the inversion circuit to perform an inversion operation on the enable signal with a value of 0 output by the comparison circuit to obtain an enable with a value of 1 signal, the inversion circuit is respectively connected to the comparison circuit and the at least one second register; the output module 430 is also used for the inversion module to output the enable signal with a value of 1 to the at least one second register; the output module 430 is further used for the at least one second register to output the acquired first target data and the second target data to the second operating circuit based on the enable signal with a value of 1.

Optionally, the negation circuit is a NOT gate.

Optionally, the output module 430 is also used for the MUX to use the first result as the output of the matrix multiplier after receiving the enable signal with a value of 1; or the MUX receives the value of 0 After the enable signal of , the second result is used as the output of the matrix multiplier.

The apparatus 400 here may be embodied in the form of functional modules. The term "module" here may be implemented in the form of software and/or hardware, which is not specifically limited.

The modules of each example described in the embodiments of the present application can be realized by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present application.

It should be noted that: when the device provided in the above embodiment executes the above method, the division of the above functional modules is used as an example for illustration. In practical applications, the above function distribution can be completed by different functional modules according to needs, that is, the device The internal structure of the system is divided into different functional modules to complete all or part of the functions described above. For example, the comparison module 410 may be used to perform any step in the above method, the determination module 420 may be used to perform any step in the above method, and the output module 430 may be used to perform any step in the above method. The steps that the comparison module 410, the determination module 420, and the output module 430 are responsible for can be specified as required, and the comparison module 410, the determination module 420, and the output module 430 respectively implement different steps in the above-mentioned method to realize all functions of the above-mentioned device.

In addition, the device and the method embodiments provided in the above embodiments belong to the same idea, and the specific implementation process thereof is detailed in the method embodiments above, and will not be repeated here.

The method provided in the embodiment of the present application may be executed by a computing device, and the computing device may also be called a computer system. Including the hardware layer, the operating system layer running on the hardware layer, and the application layer running on the operating system layer. The hardware layer includes hardware such as processing unit, memory and memory control unit, and then the function and structure of the hardware will be described in detail. The operating system is any one or more computer operating systems that implement business processing through processes, for example, Linux operating system, Unix operating system, Android operating system, iOS operating system, or windows operating system. The application layer includes browsers, address books, word processing software, instant messaging software and other applications. Moreover, optionally, the computer system is a handheld device such as a smart phone, or a terminal device such as a personal computer, which is not particularly limited in this application, as long as it can pass the method provided by the embodiment of this application. The execution subject of the method provided by the embodiment of the present application may be a computing device, or a functional module in the computing device capable of invoking a program and executing the program.

A computing device provided by an embodiment of the present application will be described in detail below with reference to FIG. 5 .

FIG. 5 is a schematic structural diagram of a computing device 1500 provided by an embodiment of the present application. The computing device 1500 may be a server or a computer or other devices with computing capabilities. The computing device 1500 shown in FIG. 5 includes: at least one processor 1510 and a memory 1520 .

It should be understood that the present application does not limit the number of processors and memories in the computing device 1500 .

The processor 1510 executes the instructions in the memory 1520, so that the computing device 1500 implements the method provided in this application. Alternatively, the processor 1510 executes the instructions in the memory 1520, so that the computing device 1500 implements each functional module provided in this application, thereby realizing the method provided in this application.

Optionally, the computing device 1500 also includes a communication interface 1530 . The communication interface 1530 implements communication between the computing device 1500 and other devices or communication networks by using transceiver modules such as but not limited to network interface cards and transceivers.

Optionally, the computing device 1500 further includes a system bus 1540 , wherein the processor 1510 , the memory 1520 and the communication interface 1530 are respectively connected to the system bus 1540 . The processor 1510 can access the memory 1520 through the system bus 1540 , for example, the processor 1510 can read and write data or execute codes in the memory 1520 through the system bus 1540 . The system bus 1540 is a peripheral component interconnect express (PCI) bus or an extended industry standard architecture (EISA) bus or the like. The system bus 1540 is divided into address bus, data bus, control bus and so on. For ease of representation, only one thick line is used in FIG. 5 , but it does not mean that there is only one bus or one type of bus.

In a possible implementation manner, the function of the processor 1510 is mainly to interpret instructions (or codes) of computer programs and process data in computer software. Wherein, the instructions of the computer program and the data in the computer software can be stored in the memory 1520 or the cache 1516 .

Optionally, the processor 1510 may be an integrated circuit chip, which has a signal processing capability. By way of example and not limitation, processor 1510 is a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), an off-the-shelf programmable gate array (field programmable gate array, FPGA) Or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. Among them, the general-purpose processor is a microprocessor or the like. For example, the processor 1510 is a central processing unit (central processing unit, CPU).

Optionally, each processor 1510 includes at least one processing unit 1512 and a memory control unit 1514 .

Optionally, the processing unit 1512 is also called a core (core) or core, and is the most important component of the processor. The processing unit 1512 is manufactured by a certain production process of single crystal silicon, and all calculations, receiving commands, storing commands, and processing data of the processor are executed by the core. The processing units run the program instructions independently, and use the ability of parallel computing to speed up the running speed of the program. Various processing units have a fixed logical structure. For example, a processing unit includes logical units such as a first-level cache, a second-level cache, an execution unit, an instruction-level unit, and a bus interface.

In one implementation example, the memory control unit 1514 is configured to control data interaction between the memory 1520 and the processing unit 1512 . Specifically, the memory control unit 1514 receives a memory access request from the processing unit 1512, and controls access to memory based on the memory access request. As an example but not a limitation, the memory control unit is a device such as a memory management unit (memory management unit, MMU).

In an implementation example, each memory control unit 1514 addresses the memory 1520 through a system bus. And an arbiter (not shown in FIG. 5 ) is configured in the system bus, and the arbiter is responsible for processing and coordinating competing accesses of multiple processing units 1512 .

In one implementation example, the processing unit 1512 and the memory control unit 1514 are communicatively connected through a connection line inside the chip, such as an address line, so as to realize communication between the processing unit 1512 and the memory control unit 1514 .

Optionally, each processor 1510 also includes a cache 1516, where a cache is a buffer (called cache) for data exchange. When the processing unit 1512 wants to read data, it will first search for the required data from the cache, if it finds it, it will execute it directly, if it cannot find it, it will find it from the memory. Since the cache runs much faster than the memory, the role of the cache is to help the processing unit 1512 run faster.

The memory 1520 can provide running space for the processes in the computing device 1500 , for example, the memory 1520 stores computer programs (specifically, program codes) for generating processes. After the computer program is run by the processor to generate a process, the processor allocates a corresponding storage space for the process in the memory 1520 . Further, the above storage space further includes a text segment, an initialization data segment, a bit initialization data segment, a stack segment, a heap segment, and the like. The memory 1520 stores data generated during the running of the process, such as intermediate data or process data, in the storage space corresponding to the above process.

Optionally, the storage is also referred to as memory, and its function is to temporarily store calculation data in the processor 1510 and exchange data with external storage such as a hard disk. As long as the computer is running, the processor 1510 will transfer the data to be calculated into the memory for calculation, and the processing unit 1512 will transmit the result after the calculation is completed.

By way of example and not limitation, memory 1520 is either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. Among them, non-volatile memory is read-only memory (read-only memory, ROM), programmable read-only memory (programmable ROM, PROM), erasable programmable read-only memory (erasablePROM, EPROM), electrically erasable Programmable read-only memory (electrically EPROM, EEPROM) or flash memory. Volatile memory is random access memory (RAM), which acts as external cache memory. By way of illustration and not limitation, many forms of RAM are available such as static random access memory (static RAM, SRAM), dynamic random access memory (dynamic RAM, DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous connection dynamic random access memory (synchlink DRAM, SLDRAM ) and direct memory bus random access memory (direct rambus RAM, DRRAM). It should be noted that memory 1520 of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

The structure of the computing device 1500 listed above is only an example, and the present application is not limited thereto. The computing device 1500 in the embodiment of the present application includes various hardware in the computer system in the prior art. For example, the computing device 1500 also includes Other storages other than the storage 1520, for example, disk storage and the like. Those skilled in the art should understand that the computing device 1500 may also include other devices necessary for normal operation. Meanwhile, according to specific needs, those skilled in the art should understand that the above computing device 1500 may also include hardware devices for implementing other additional functions. In addition, those skilled in the art should understand that the above-mentioned computing device 1500 may only include components necessary to realize the embodiment of the present application, and does not necessarily include all the components shown in FIG. 5 .

In this embodiment, a chip including the above-mentioned matrix multiplier is also provided.

In this embodiment, a computer program product containing instructions is also provided. The computer program product may be a software or program product containing instructions that can run on a computing device or be stored in any available medium. When it runs on the computing device, it makes the computing device execute the method provided above, or makes the computing device realize the function of the device provided above.

In this embodiment, a computer-readable storage medium is also provided. The computer-readable storage medium may be any available medium capable of being stored by a computing device or a data storage device such as a data center including one or more available media. The available medium may be a magnetic medium (for example, a floppy disk, a hard disk, or a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid-state hard disk), and the like. The computer-readable storage medium includes instructions, and when the instructions in the computer-readable storage medium are executed on the computing device, the computing device is made to execute the method provided above.

It should be understood that, in various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the order of execution, and the execution order of the processes should be determined by their functions and internal logic, and should not be used in the embodiments of the present application. The implementation process constitutes any limitation.

Those skilled in the art can appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present application.

Those skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the above-described system, device and unit can refer to the corresponding process in the foregoing method embodiment, which will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods may be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.

If the functions described above are realized in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (read-only memory, ROM), random access memory (random access memory, RAM), magnetic disk or optical disk and other media that can store program codes. .

The above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. Should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims (32)

1. A matrix multiplier, characterized in that, said matrix multiplier comprises: A comparison circuit, configured to determine whether the first target data and/or the second target data are data in the first set, wherein the first target data is data in the first matrix, and the second target data is the data in the first matrix The data in the second matrix, the first set includes: 0, ±2 ⁿ , the n is an integer; A first operation circuit, configured to output the result of multiplying the first target data and the second target data according to the first target data and/or the second target data being data in the first set The first result, the first result includes: 0 or third data, wherein the third data is obtained by shifting the first target data or the second target data according to the n, or the The third data is obtained by shifting and inverting the first target data or the second target data according to the n. 2. The matrix multiplier according to claim 1, wherein The first operation circuit is specifically configured to output the first result as 0 according to the first target data being 0. 3. The matrix multiplier according to claim 1, wherein The first operation circuit is specifically configured to output the first result as the third data according to the first target data being 2 ⁿ , and the third data is a left shift of the second target data Or right shift |n| bits to get. 4. The matrix multiplier according to claim 3, wherein the first operating circuit is specifically used for: According to the first target data being 2 ⁿ and the n being a positive integer, the outputted first result is the third data, and the third data is obtained by shifting the second target data to the left by n bits of; or According to the first target data being 2 ⁿ and the n being a negative integer, the outputted first result is the third data, and the third data is a right shift of the second target data by |n| bit got. 5. The matrix multiplier according to claim 1, wherein The first operation circuit is specifically configured to output the first result as the third data according to the first target data being -2 ⁿ , and the third data is the left and right of the second target data shift or right |n| bits and negate. 6. The matrix multiplier according to any one of claims 1 to 5, characterized in that, The comparison circuit is further configured to determine a first operation code according to the first target data and/or the second target data as data in the first set, wherein the first operation code is a value indicating that said first target data and/or said second target data is 0 or ±2 ⁿ ; The first operation circuit is specifically configured to determine that the first result is 0 or the third target data according to the value of the first operation code and the first target data and/or the second target data data. 7. The matrix multiplier according to any one of claims 1 to 5, characterized in that, the matrix multiplier also includes at least one first register, and the at least one first register is respectively connected to the comparison circuit, The first operating circuit is connected to, said at least one first register for obtaining said first target data and said second target data from said comparison circuit; The at least one first register is further configured to output the first target data and the second target data to the first operating circuit. 8. The matrix multiplier according to claim 7, wherein The at least one first register is further used to obtain the first operation code from the comparison circuit, and output the first operation code to the first operation circuit. 9. The matrix multiplier according to any one of claims 1 to 5, characterized in that, the matrix multiplier also includes at least one second register and a second operating circuit, and the at least one second register and the The second operating circuit is connected, The at least one second register is used to obtain the first target data and the second target data when the comparison circuit determines that neither the first target data nor the second target data is data in the first set. outputting the target data and the second target data to the second operation circuit; The second operation circuit is configured to perform a conventional multiplication operation on the received first target data and the second target data, and output the first target data multiplied by the second target data Two results. 10. matrix multiplier according to claim 9, is characterized in that, described matrix multiplier also comprises data selector MUX, and described MUX is connected with described second operation circuit, described first operation circuit respectively, The MUX is configured to use the first result or the second result as an output of the matrix multiplier. 11. The matrix multiplier according to claim 7, wherein The comparison circuit is further configured to, when the comparison circuit determines that the first target data and/or the second target data are data in the first set, send to the at least one first register Output an enable signal with a value of 1; The at least one first register is specifically configured to output the first target data and the second target data to the first operating circuit according to the enable signal with a value of 1. 12. The matrix multiplier according to claim 9, wherein the matrix multiplier also includes an inversion circuit, and the inversion circuit is respectively connected with the comparison circuit and the at least one second register, The comparison circuit is further configured to output to the at least one first register when the comparison circuit determines that neither the first target data nor the second target data is data in the first set An enable signal whose value is 0; The inversion circuit is used to invert the enable signal with a value of 0 output by the comparison circuit to obtain an enable signal with a value of 1, and convert the enable signal with a value of 1 to outputting an enable signal to the at least one second register; The at least one second register is specifically configured to output the acquired first target data and the second target data to the second operating circuit based on the enable signal with a value of 1. 13. The matrix multiplier according to claim 12, wherein the negation circuit is a NOT gate. 14. The matrix multiplier according to claim 10, wherein the MUX is specifically used for: After receiving an enable signal with a value of 1, using the first result as an output of the matrix multiplier; or After receiving the enable signal whose value is 0, the second result is used as the output of the matrix multiplier. 15. A method for matrix multiplication, characterized in that the method is applied to a matrix multiplier, and the matrix multiplier is used to perform matrix multiplication operations on the first matrix and the second matrix, and the method comprises: The comparison circuit determines whether the first target data is the data in the first matrix and/or the second target data is the data in the first set, wherein the first target data is the data in the first matrix, and the second target data is the data in the For the data in the second matrix, the first set includes: 0, ±2 ⁿ , where n is an integer; The first operation circuit outputs a first result of multiplying the first target data and the second target data according to the first target data and/or the second target data being data in the first set, so The first result includes: 0 or third data, wherein the third data is obtained by shifting the first target data or the second target data according to the n, or the third data is It is obtained by shifting and inverting the first target data or the second target data according to the n. 16. The method according to claim 15, wherein the first operating circuit outputs the first target data and/or the second target data as data in the first set, and outputs the first The first result of multiplying the target data and the second target data includes: The first operation circuit outputs the first result as 0 according to the first target data as 0. 17. The method according to claim 15, wherein the first operating circuit outputs the first target data and/or the second target data as data in the first set according to the first operation circuit The first result of multiplying the target data and the second target data includes: According to the first target data being 2 ⁿ , the first operation circuit outputs the first result as the third data, and the third data is shifted left or right of the second target data | n| bits are obtained. 18. The method according to claim 17, wherein the first operation circuit outputs the first result as the third data according to the first target data being 2 ⁿ , comprising: According to the first target data being 2 ⁿ and the n being a positive integer, the first operation circuit outputs the first result as the third data, and the third data is for the second target obtained by shifting the data to the left by n bits; or According to the first target data being 2 ⁿ and the n being a negative integer, the first operation circuit outputs the first result as the third data, and the third data is a reference to the second target The data is shifted right by |n| bits. 19. The method according to claim 15, wherein the first operation circuit outputs the first target data and/or the second target data as data in the first set, and outputs the first The first result of multiplying the target data and the second target data includes: According to the first target data being -2 ⁿ , the first operation circuit outputs the first result as the third data, and the third data is left-shifted or right-shifted for the second target data |n| bits and negate them. 20. The method according to any one of claims 15 to 19, further comprising: The comparison circuit determines a first operation code according to the first target data and/or the second target data as data in the first set, wherein the value of the first operation code indicates the The first target data and/or the second target data are 0 or ±2 ⁿ ; The first operation circuit outputs a first result of multiplying the first target data and the second target data according to the first target data and/or the second target data as data in the first set ,include: The first operation circuit determines that the first result is 0 or the third data according to the value of the first operation code and the first target data and/or the second target data. 21. The method according to any one of claims 15 to 19, further comprising: At least one first register acquires the first target data and the second target data from the comparison circuit, and the at least one first register is respectively connected to the comparison circuit and the first operation circuit; The at least one first register outputs the first object data and the second object data to the first operation circuit. 22. The method of claim 21, further comprising: The at least one first register obtains the first operation code from the comparison circuit and outputs the first operation code to the first operation circuit. 23. The method according to any one of claims 15 to 19, further comprising: at least one second register, when the comparison circuit determines that neither the first target data nor the second target data is data in the first set, the acquired first target data and the The second target data is output to a second operating circuit, and the at least one second register is connected to the second operating circuit; The second operation circuit performs a conventional multiplication operation on the received first target data and the second target data, and outputs a second result of multiplying the first target data and the second target data. 24. The method of claim 23, further comprising: The data selector MUX takes the first result or the second result as the output of the matrix multiplier, and the UX is respectively connected to the second operation circuit and the first operation circuit. 25. The method of claim 21, further comprising: When the comparison circuit determines that the first target data and/or the second target data are data in the first set, output an enable value of 1 to the at least one first register Signal; The at least one first register outputs the first target data and the second target data to the first operating circuit, comprising: The at least one first register outputs the first target data and the second target data to the first operating circuit according to the enable signal with a value of 1. 26. The method of claim 23, further comprising: When the comparison circuit determines that neither the first target data nor the second target data is data in the first set, output an enable signal with a value of 0 to the at least one first register ; The inversion circuit performs an inversion operation on the enable signal with a value of 0 output by the comparison circuit to obtain an enable signal with a value of 1, and outputs the enable signal with a value of 1 to the The at least one second register, the inversion circuit is respectively connected to the comparison circuit and the at least one second register; When the at least one second register determines that neither the first target data nor the second target data is data in the first set, the acquired first target data and The second target data is output to a second operating circuit, including: The at least one second register outputs the obtained first target data and the second target data to the second operating circuit based on the enable signal with a value of 1. 27. The method according to claim 26, wherein the negation circuit is a NOT gate. 28. The method according to claim 24, wherein the data selector MUX uses the first result or the second result as the output of the matrix multiplier, comprising: After the MUX receives the enable signal whose value is 1, the first result is used as the output of the matrix multiplier; or The MUX uses the second result as an output of the matrix multiplier after receiving the enable signal whose value is 0. 29. A chip, characterized in that the chip comprises the matrix multiplier according to any one of claims 1 to 14. 30. A computing device characterized by, at least one processor; and at least one memory coupled to said at least one processor; Wherein, instructions executable by the at least one processor are stored in the at least one memory, and the at least one processor is used to execute the instructions stored in the at least one memory, so that the computing device performs the The method described in any one of 15 to 28. 31. A computer program product comprising instructions, characterized in that, when the instructions are executed by the computer, the computer is caused to perform the method according to any one of claims 15 to 28. 32. A computer-readable storage medium, characterized in that it includes computer program instructions, and when the computer program instructions are executed by the computer, the computer executes the computer program according to any one of claims 15 to 28. method.

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