CN116048051A - Timeout verification method, device, equipment and storage medium - Google Patents
Timeout verification method, device, equipment and storage medium Download PDFInfo
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- CN116048051A CN116048051A CN202310073216.XA CN202310073216A CN116048051A CN 116048051 A CN116048051 A CN 116048051A CN 202310073216 A CN202310073216 A CN 202310073216A CN 116048051 A CN116048051 A CN 116048051A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B23/00—Testing or monitoring of control systems or parts thereof
- G05B23/02—Electric testing or monitoring
- G05B23/0205—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults
- G05B23/0208—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterized by the configuration of the monitoring system
- G05B23/0213—Modular or universal configuration of the monitoring system, e.g. monitoring system having modules that may be combined to build monitoring program; monitoring system that can be applied to legacy systems; adaptable monitoring system; using different communication protocols
Abstract
The embodiment of the invention provides a timeout time verification method, a timeout time verification device, timeout time verification equipment and a storage medium, and relates to the technical field of controller testing; the timeout time of the lost message detected by the controller can be automatically and accurately verified. A tester for use in a timeout validation system, the method performing a timeout validation process a plurality of times, comprising: sending test messages to a controller to be diagnosed in different message periods; and verifying the overtime time of the controller to be diagnosed for detecting the lost message according to the message period corresponding to the target test message detected by the controller to be diagnosed.
Description
[ field of technology ]
The embodiment of the invention relates to the technical field of controller testing, in particular to a timeout verification method, device and equipment and a storage medium.
[ background Art ]
Under the large trend of intellectualization and electric drive, various controllers are widely applied to automobiles. In order to ensure that the messages of the network nodes of the whole vehicle are normally transmitted and received and the bus of the whole vehicle is normally communicated, the related field detects whether faults such as node loss exist in the whole vehicle or not through diagnosis specifications, so that a controller to be applied to the whole vehicle is required to detect whether the message transmission and reception are normal or not, and the overtime time of the controller for detecting the lost message is verified so as to confirm that the controller can detect the existence of the faults within a specified time, and corresponding fault codes are reported.
The current means for verifying the timeout time of the lost message detected by the controller is single, and the problem that some timeout time cannot be accurate exists, and an automatic test method is lacking.
[ invention ]
The embodiment of the application provides a timeout time verification method, device, equipment and storage medium, which can automatically and accurately verify the timeout time of a lost message detected by a controller.
In a first aspect, an embodiment of the present invention provides a timeout verification method, applied to a tester of a timeout verification system, where the method performs a timeout verification process multiple times, including: sending test messages to a controller to be diagnosed in different message periods; and verifying the overtime time of the controller to be diagnosed for detecting the lost message according to the message period corresponding to the target test message detected by the controller to be diagnosed.
Setting a timeout time verification system for verifying timeout time of a controller, sending test messages to the controller to be diagnosed in different periods through a tester, obtaining period time corresponding to a lost target test message detected by the controller to be diagnosed, and measuring the time of the controller to be diagnosed detecting the lost message through the period time corresponding to the lost target test message detected by the controller to be diagnosed; the method for verifying the timeout time is automatically realized by sending the message to the controller to be diagnosed through the tester, and the timeout time of the lost message detected by the controller is automatically and accurately verified, so that the testing time consumption is reduced, and the testing coverage integrity is ensured.
In one possible implementation manner, sending test messages to a controller to be diagnosed in different message periods includes:
the test message is sent to the controller to be diagnosed for the Nth time in a target period; the target period is obtained after overlapping the preset time length for N-1 times by taking the period to be detected as the initial period;
outputting a fault code aiming at the test message which is transmitted for the nth time and is lost by the controller to be diagnosed when the controller to be diagnosed is read, and outputting the time corresponding to the target period;
verifying the timeout time of the detection of the lost message by the controller to be diagnosed according to the message period corresponding to the target test message detected to be lost by the controller to be diagnosed, wherein the method comprises the following steps:
and verifying the overtime time of the lost message detected by the controller to be diagnosed according to the time corresponding to the target period.
In one possible implementation manner, when the to-be-diagnosed controller fails to read the fault code output by the to-be-diagnosed controller aiming at the missing test message sent by the nth time, a preset time length is increased for the target period, and the test message is sent to the to-be-diagnosed controller by the (n+1) th time.
In one possible implementation manner, verifying, according to a message period corresponding to the target test message in which the controller to be diagnosed detects the missing target test message, a timeout period in which the controller to be diagnosed detects the missing target test message, includes:
when the controller to be diagnosed detects that the message period corresponding to the lost target test message is within the error range of the period to be diagnosed, verifying that the overtime time of the controller to be diagnosed, which detects the lost message, is within the lost time range corresponding to the period to be diagnosed, and determining that the overtime time of the controller to be diagnosed is normal.
In one possible implementation manner, verifying, according to a message period corresponding to the target test message in which the controller to be diagnosed detects the missing target test message, a timeout period in which the controller to be diagnosed detects the missing target test message, includes:
and when the controller to be diagnosed detects that the message period corresponding to the lost target test message is not in the error range of the period to be diagnosed, determining that the timeout time of the controller to be diagnosed is abnormal.
In one possible implementation manner, the timeout verification system further includes a programmable power supply, and before sending the test message to the controller to be diagnosed in different message periods in each timeout verification process, the system further includes:
controlling the program-controlled power supply to be electrified, and clearing the historical fault code;
and verifying the timeout time of the detection of the lost message by the controller to be diagnosed according to the message period corresponding to the target test message detected to be lost by the controller to be diagnosed, and further comprising:
recording the result of overtime verification of the controller to be diagnosed for detecting the lost message;
controlling the program-controlled power supply to be powered down;
and checking the timeout verification result of the lost message detected by the controller to be diagnosed after the timeout verification is executed for a plurality of times.
In a second aspect, an embodiment of the present invention provides a timeout period verification apparatus, provided in an electronic device, including:
the message sending module is used for sending test messages to the controller to be diagnosed in different message periods;
and the verification module is used for verifying the timeout time of the detection of the lost message by the controller to be diagnosed according to the message period corresponding to the target test message which is detected to be lost by the controller to be diagnosed.
In one possible implementation manner, the message sending module includes:
the period sending submodule is used for sending the test message to the controller to be diagnosed for the nth time in the target period; the target period is obtained after overlapping the preset time length for N-1 times by taking the period to be detected as the initial period;
the reading sub-module is used for outputting a fault code aiming at the test message which is transmitted for the nth time and outputting the time corresponding to the target period when the controller to be diagnosed is read;
the verification module is specifically configured to verify the timeout time of the detection of the lost message by the controller to be diagnosed according to the time corresponding to the target period.
In one possible implementation manner, the reading sub-module is further configured to, when the to-be-diagnosed controller is not read, output a fault code for the nth transmitted test message, increase the target period by a preset time length, and send the test message to the to-be-diagnosed controller for the n+1th time.
In one possible implementation manner, the verification module is specifically configured to verify that, when the controller to be diagnosed detects that the packet period corresponding to the lost target test packet is within the error range of the cycle to be diagnosed, the timeout time of the controller to be diagnosed when the controller to be diagnosed detects that the lost packet is within the lost time range corresponding to the cycle to be diagnosed, and determine that the timeout time of the controller to be diagnosed is normal.
In one possible implementation manner, the verification module is specifically further configured to determine that the timeout period of the controller to be diagnosed is abnormal when the controller to be diagnosed detects that the packet period corresponding to the lost target test packet is not within the error range of the period to be diagnosed.
In one possible implementation manner, the timeout verification system further comprises a programmable power supply; the apparatus further comprises:
the clear module is used for clearing the historical fault codes;
the power supply control module is used for controlling the program-controlled power supply to be electrified before sending test messages to the controller to be diagnosed in different message periods in the process of executing timeout time verification each time; according to the message period corresponding to the target test message which is detected to be lost by the controller to be diagnosed, after verifying the overtime time of the detection of the lost message by the controller to be diagnosed, controlling the program-controlled power supply to be powered down;
the recording module is used for recording the result of timeout time verification of the controller to be diagnosed for detecting the lost message in the timeout time verification process of each execution;
and the checking module is used for checking the overtime verification result of the detection of the lost message of the controller to be diagnosed after the overtime verification is executed for a plurality of times.
In a third aspect, an embodiment of the present invention provides an apparatus, including at least one processor; and at least one memory communicatively coupled to the processor, wherein the device is coupled to the tester, the memory storing program instructions executable by the processor, the processor invoking the program instructions to perform the method provided in the first aspect.
In a fourth aspect, embodiments of the present invention provide a computer-readable storage medium storing computer instructions that cause a computer to perform the method provided in the first aspect.
It should be understood that, the second to fourth aspects of the embodiments of the present invention are consistent with the technical solutions of the first aspect of the embodiments of the present invention, and the beneficial effects obtained by each aspect and the corresponding possible implementation manner are similar, and are not repeated.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present specification, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart illustrating steps of a timeout verification method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a timeout verification system in one example of the present application;
FIG. 3 is a flowchart illustrating steps of a timeout verification method according to another embodiment of the present application;
FIG. 4 is a schematic diagram of a timeout verification system in another example of the present application;
FIG. 5 is an information flow diagram of another example implementation of the timeout verification method of the present application;
FIG. 6 is a functional block diagram of a timeout verification device according to an embodiment of the present invention
Fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
[ detailed description ] of the invention
For a better understanding of the technical solutions of the present specification, the following detailed description of the embodiments of the present invention refers to the accompanying drawings.
It should be understood that the described embodiments are only some, but not all, of the embodiments of the present description. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present disclosure.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the description. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
Fig. 1 is a flowchart of steps of a timeout verification method according to an embodiment of the present application, where, as shown in fig. 1, the timeout verification includes the steps of:
s11: the tester sends test messages to the controller to be diagnosed in different message periods.
In order to realize that an automatic verification controller detects the overtime of a lost message, the embodiment of the application constructs an overtime verification system which comprises a tester and a controller to be diagnosed.
The controller to be diagnosed can be any controller in various control systems of the whole vehicle, the controller is mounted to the vehicle after completing various detection, and the controller is used as different nodes of the whole vehicle system to cooperatively complete different instructions in operation. For example, the controller to be diagnosed may include at least one of: the vehicle control unit VCU, the automatic transmission controller TCU, the vehicle body control unit BCM, the electric control unit EPS of the electric power steering system, the steering wheel angle sensor SAS and the like are not limited.
The embodiment of the application aims at any controller which can not normally receive the message, and can automatically verify whether the controller which can not normally receive the message can normally report the fault to the condition of losing the message.
The tester may be a device capable of implementing the simulated test function. The tester in one example of the present application is a bus emulation test device (CAN open environment, CANoe), and fig. 2 is a schematic structural diagram of a timeout verification system in one example of the present application, as shown in fig. 2, a hardware part VN1640 of the tester CANoe is connected to a controller under diagnosis DUT through can_h and can_l; the CANoe can run a related program to simulate a message received by the controller to be diagnosed in the whole vehicle, and the message is used as a test message to be sent to the controller to be diagnosed so as to verify whether the controller to be diagnosed can report a fault code aiming at the condition of message loss within a specified time range.
Step S12: and the tester verifies the timeout time of the controller to be diagnosed for detecting the lost message according to the message period corresponding to the target test message detected by the controller to be diagnosed.
The tester sends a message A, a message B and a message C to the controller to be diagnosed, wherein the fault code given by the controller to be diagnosed corresponds to the message B, and the message B is a target test message which is detected to be lost by the controller to be diagnosed, and indicates that the controller to be diagnosed cannot detect that the message A and the message C are lost;
the controller to be diagnosed which can normally detect the message loss can detect the message loss in the time of N times of the period to be detected, so that whether the controller to be diagnosed can detect the message loss in a preset range or not can be reversely deduced through the period corresponding to the lost message detected by the controller to be diagnosed.
If the controller to be diagnosed can report the fault code of the lost test message in the preset range, namely the controller to be diagnosed can read the fault code, the controller to be diagnosed indicates that the overtime time of the lost test message is normal, if the controller to be diagnosed cannot report the fault code of the lost test message in the preset range, the controller to be diagnosed indicates that the overtime time of the lost test message is abnormal, and because the limited time range for measuring whether the overtime time is normal is associated with the period of the message, the embodiment of the invention adopts the tester to simulate the test message to be sent to the controller to be diagnosed, so that the overtime time is deduced according to the period corresponding to the message of which the controller to be diagnosed can report the fault code, and the automatic verification of the overtime time is realized.
For example, the period of the message received by the controller to be diagnosed in normal is T, and the controller to be diagnosed needs to report a fault code to the lost message in the time of NT; the tester sends a plurality of test messages with different periods to the controller to be diagnosed, the controller to be diagnosed reports that the missing message corresponding to the fault code is a test message Q, the period corresponding to the test message Q is T+t, the controller to be diagnosed calculates N (T+t) -NT & gt2N, and the controller to be diagnosed can confirm that the overtime time for verifying the controller to be diagnosed to detect the missing message is abnormal.
Further, the embodiment of the application further provides an implementation mode for verifying the timeout time of the detection of the lost message by the controller to be diagnosed according to the message period corresponding to the target test message detected to be lost by the controller to be diagnosed;
and verifying the timeout time of the lost message detected by the controller to be diagnosed by judging whether the message period corresponding to the lost target test message detected by the controller to be diagnosed is in an error range.
When the controller to be diagnosed detects that the message period corresponding to the lost target test message is within the error range of the period to be diagnosed, verifying that the overtime time of the controller to be diagnosed, which detects the lost message, is within the lost time range corresponding to the period to be diagnosed, and determining that the overtime time of the controller to be diagnosed is normal.
And when the controller to be diagnosed detects that the message period corresponding to the lost target test message is not in the error range of the period to be diagnosed, determining that the timeout time of the controller to be diagnosed is abnormal.
The error range of the message period can be obtained through standard timeout time corresponding to the period to be detected. The to-be-diagnosed controller receives a message with a period of T in the whole vehicle running process, the to-be-diagnosed controller can be T in timeout time verification of the to-be-diagnosed controller, the to-be-diagnosed controller needs to detect message loss in the NT time in the whole vehicle running process according to the whole vehicle communication protocol, and the loss time range corresponding to the to-be-diagnosed period can be determined to be (N-1) T to (N+1) T; accordingly, the error range of the period to be diagnosed may be (N-1) T/N to (N+1) T/N.
Fig. 3 is a flowchart illustrating steps of a timeout verification method according to another embodiment of the present application, as shown in fig. 3, including:
s31: and sending the test message to the controller to be diagnosed for the Nth time in the target period.
And superposing the target period with the period to be detected as an initial period for N-1 times of preset time length. And superposing the preset time length for N-1 times by taking the period to be detected as the initial period, wherein the period for transmitting the test message for the Nth time is obtained by increasing the preset time length on the basis of the period for transmitting the test message for the Nth-1 time.
The preset time period may be set according to the initial period, and may be, for example, one hundredth of the initial period.
In one embodiment of the present invention, the tester may implement "send test messages to the controller to be diagnosed with different message periods" by gradually increasing the message periods.
For example, the controller to be diagnosed may receive a message with a period of T in the whole vehicle, may take T as an initial period, the tester may first send the message with the period of T to the controller to be diagnosed, increase the period of the message for the second time with a step length of 0.05T, send the message with a period of t+0.05t to the controller to be diagnosed, increase the period of the message for the third time with a step length of 0.05T, send the message with the period of t+0.1t to the controller to be diagnosed, and so on, if the fault code is read, no longer send the test message to the controller to be diagnosed, output the current period, if the fault code is not read, continue to send the test message with a step length of 0.05T for increasing time on the basis of the last time period of sending the test message, obtain a new period, and send the test message with the new period until the fault code is read to the controller to be diagnosed.
S32: when the tester reads that the to-be-diagnosed controller outputs a fault code aiming at the lost test message sent by the Nth time, outputting the time corresponding to the target period. And verifying the overtime time of the lost message detected by the controller to be diagnosed according to the time corresponding to the target period.
The tester reads the fault code to indicate that the controller to be diagnosed detects the message loss, and then can verify the overtime time when the controller to be diagnosed detects the message loss, namely, verify how long the controller to be diagnosed can detect the message loss.
S33: and when the to-be-diagnosed controller fails to read the fault code output by aiming at the lost test message sent by the Nth time, increasing the preset time length for the target period, and sending the test message to the to-be-diagnosed controller by the (n+1) th time.
The tester does not read the fault code, which indicates that the controller to be diagnosed does not detect the message loss, and needs to continuously send the test message to the controller to be diagnosed, because the controller to be diagnosed does not detect the message sent in the target period for the nth time, the period of sending the message is modified on the basis of the target period, and the time that the controller to be diagnosed can detect the lost message is tested in the new period.
Therefore, when the to-be-diagnosed controller fails to read the fault code output by aiming at the missing test message sent by the Nth time, the preset time length is increased for the target period, and the test message is sent to the to-be-diagnosed controller for the (n+1) th time of a new period obtained after the preset time length is increased for the target period.
The embodiment of the invention also provides that the overtime verification process can be executed for a plurality of times, the overtime of the message loss detected by the controller to be diagnosed is verified for a plurality of times, the result of the overtime of the message loss detected by the controller to be diagnosed is verified for a plurality of times is checked, and the accuracy of the overtime verification is ensured.
The overtime verification system further comprises a programmable power supply;
in each execution of the timeout period verification process, before sending the test message to the controller to be diagnosed in different message periods, the method further comprises:
and controlling the program-controlled power supply to be electrified, and clearing the historical fault code.
The automatic switching of the verification process of the timeout time is realized by controlling the program-controlled power supply; after each power-on, the historical fault code is cleared, and the fact that the controller to be diagnosed can accurately obtain the lost target message identified by the controller to be diagnosed through the mode of reading the fault code is guaranteed, so that the time that the controller to be diagnosed detects that the message is lost is accurately obtained.
And verifying the timeout time of the detection of the lost message by the controller to be diagnosed according to the message period corresponding to the target test message detected to be lost by the controller to be diagnosed, and further comprising:
recording the result of overtime verification of the controller to be diagnosed for detecting the lost message;
controlling the program-controlled power supply to be powered down;
and checking the timeout verification result of the lost message detected by the controller to be diagnosed after the timeout verification is executed for a plurality of times.
Fig. 4 is a schematic structural diagram of a timeout verification system in another example of the present application, as shown in fig. 4, a tester is connected to a programmable power supply through a USB, the tester is connected to a controller to be diagnosed through can_h and can_l, and the controller to be diagnosed is connected to the programmable power supply through K15 and K30.
FIG. 5 is an information flow diagram of another example execution timeout verification method of the present application, as shown in FIG. 5, based on the timeout verification system of FIG. 4, the execution timeout verification method by a tester includes the steps of:
k11: the tester controls the programmable power supply to be electrified, and clears the historical fault code of the controller to be diagnosed.
K12: and sending a message with the simulation period of T to a controller to be diagnosed by the tester.
K13: and judging whether the fault code of the lost message is read from the controller to be diagnosed.
K14: and reading the fault code output by the controller to be diagnosed and outputting the period T of the corresponding message. And verifying that the timeout time of the detection of the lost message by the controller to be diagnosed is normal by calculating that the period T of the detection of the lost message by the controller to be diagnosed is within a preset time range (9T/10-11T/10).
K15: and if the fault code output by the controller to be diagnosed is not read, increasing the message period by 0.05T, and sending the message with the simulation period of T+0.05T to the controller to be diagnosed.
K16: and judging whether the fault code of the lost message is read from the controller to be diagnosed.
K17: and reading the fault code output by the controller to be diagnosed, and outputting the period T+0.05T of the corresponding message. And verifying that the timeout time of the detection of the lost message by the controller to be diagnosed is normal by calculating that the period T of the detection of the lost message by the controller to be diagnosed is within a preset time range (9T/10-11T/10). For example, if the period of the test message is 20ms, the controller to be diagnosed needs to report the corresponding fault code within 180ms-220ms, and if the fault code is not reported or is reported in advance, the timeout verification is not passed.
K18: if the fault code output by the controller to be diagnosed is not read, the message period is increased by 0.05T, the message with the simulation period of T+0.1T is sent to the controller to be diagnosed, and the partial contents of the steps K13 to K15 are repeated: judging whether the fault code of the lost message is read from the controller to be diagnosed, and outputting the fault code to the controller to be diagnosed and outputting the period of the corresponding message; and if the fault code output by the controller to be diagnosed is not read, increasing the message period by 0.05T, and continuing to send the simulation message to the controller to be diagnosed until the fault code output by the controller to be diagnosed is read.
K19: and recording a timeout verification result of the detection of the lost message by the controller to be diagnosed.
K20: the tester controls the programmable power supply to be powered down.
Fig. 6 is a functional block diagram of a timeout checking apparatus according to an embodiment of the present invention, where the timeout checking apparatus is provided in an electronic device, as shown in fig. 6, and the apparatus includes:
the electronic device may be a computer, an integrated computer, or the like.
A message sending module 61, configured to send test messages to the controller to be diagnosed in different message periods;
and the verification module 62 is configured to verify the timeout period of the detection of the missing message by the controller to be diagnosed according to the message period corresponding to the target test message detected to be missing by the controller to be diagnosed.
The timeout verification device provided in the embodiment shown in fig. 6 may be used to implement the technical solutions of the method embodiments shown in fig. 1 to 5 in the present specification, and the principle and technical effects thereof may be further described with reference to the related descriptions in the method embodiments.
Optionally, the message sending module includes:
the period sending submodule is used for sending the test message to the controller to be diagnosed for the nth time in the target period; the target period is obtained after overlapping the preset time length for N-1 times by taking the period to be detected as the initial period;
the reading sub-module is used for outputting a fault code aiming at the test message which is transmitted for the nth time and outputting the time corresponding to the target period when the controller to be diagnosed is read;
the verification module is specifically configured to verify the timeout time of the detection of the lost message by the controller to be diagnosed according to the time corresponding to the target period.
Optionally, the reading sub-module is further configured to, when the to-be-diagnosed controller is not read, output a fault code for the N-th transmitted test message, increase the preset time length for the target period, and n+1th transmit the test message to the to-be-diagnosed controller.
Optionally, the verification module is specifically configured to verify that, when the controller to be diagnosed detects that the packet period corresponding to the lost target test packet is within the error range of the cycle to be diagnosed, the timeout time of the controller to be diagnosed when the controller to be diagnosed detects that the lost packet is within the lost time range corresponding to the cycle to be diagnosed, and determine that the timeout time of the controller to be diagnosed is normal.
Optionally, the verification module is specifically further configured to determine that the timeout period of the controller to be diagnosed is abnormal when the controller to be diagnosed detects that the packet period corresponding to the lost target test packet is not within the error range of the period to be diagnosed.
Optionally, the timeout verification system further comprises a programmable power supply; the apparatus further comprises:
the clear module is used for clearing the historical fault codes;
the power supply control module is used for controlling the program-controlled power supply to be electrified before sending test messages to the controller to be diagnosed in different message periods in the process of executing timeout time verification each time; according to the message period corresponding to the target test message which is detected to be lost by the controller to be diagnosed, after verifying the overtime time of the detection of the lost message by the controller to be diagnosed, controlling the program-controlled power supply to be powered down;
the recording module is used for recording the result of timeout time verification of the controller to be diagnosed for detecting the lost message in the timeout time verification process of each execution;
and the checking module is used for checking the overtime verification result of the detection of the lost message of the controller to be diagnosed after the overtime verification is executed for a plurality of times.
The device provided by the above-described embodiment is used for executing the technical scheme of the above-described method embodiment, and its implementation principle and technical effects may further refer to the related description in the method embodiment, which is not repeated herein.
The device provided by the above-described embodiment may be, for example: a chip or a chip module. The device provided by the above-described embodiment is used for executing the technical scheme of the above-described method embodiment, and its implementation principle and technical effects may further refer to the related description in the method embodiment, which is not repeated herein.
With respect to each module/unit included in each apparatus described in the above embodiments, it may be a software module/unit, or may be a hardware module/unit, or may be a software module/unit partially, or a hardware module/unit partially. For example, for each device applied to or integrated in a chip, each module/unit included in the device may be implemented in hardware such as a circuit, or at least part of the modules/units may be implemented in software program, where the software program runs on a processor integrated in the chip, and the rest of the modules/units may be implemented in hardware such as a circuit; for each device applied to or integrated in the chip module, each module/unit contained in the device may be implemented in a hardware manner such as a circuit, and different modules/units may be located in the same component (e.g. a chip, a circuit module, etc.) of the chip module or different components, or at least part of the modules/units may be implemented in a software program, where the software program runs on a processor integrated in the chip module, and the rest of the modules/units may be implemented in a hardware manner such as a circuit; for each device applied to or integrated in the electronic terminal device, each module/unit included in the device may be implemented in hardware such as a circuit, and different modules/units may be located in the same component (for example, a chip, a circuit module, etc.) or different components in the electronic terminal device, or at least part of the modules/units may be implemented in a software program, where the software program runs on a processor integrated in the electronic terminal device, and the remaining (if any) part of the modules/units may be implemented in hardware such as a circuit.
Fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present invention, where the electronic device 700 includes a processor 710, a memory 711, and a computer program stored in the memory 711 and capable of running on the processor 710, where the steps in the foregoing method embodiments are implemented when the processor 710 executes the program, and the electronic device according to the embodiment may be used to execute the technical solutions of the foregoing method embodiments, and the implementation principles and technical effects may be further referred to in the related descriptions of the method embodiments and are not repeated herein.
Embodiments of the present invention provide a computer-readable storage medium storing computer instructions that cause a computer to execute the timeout period verification method provided in the embodiments shown in fig. 1 to 5 of the present specification. Computer-readable storage media may refer to non-volatile computer storage media.
Any combination of one or more computer readable media may be utilized as the above-described computer readable storage media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (erasable programmable read only memory, EPROM) or flash memory, an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
The computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, radio Frequency (RF), etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for the present specification may be written in one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a local area network (local area network, LAN) or a wide area network (wide area network, WAN), or may be connected to an external computer (e.g., connected via the internet using an internet service provider).
The foregoing describes specific embodiments of the present disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
In the description of embodiments of the present invention, a description of reference to the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present specification. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present specification, the meaning of "plurality" means at least two, for example, two, three, etc., unless explicitly defined otherwise.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and additional implementations are included within the scope of the preferred embodiment of the present specification in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present specification.
Depending on the context, the word "if" as used herein may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to detection". Similarly, the phrase "if determined" or "if detected (stated condition or event)" may be interpreted as "when determined" or "in response to determination" or "when detected (stated condition or event)" or "in response to detection (stated condition or event), depending on the context.
It should be noted that, the terminal according to the embodiment of the present invention may include, but is not limited to, a personal computer (personal computer, PC), a personal digital assistant (personal digital assistant, PDA), a wireless handheld device, a tablet computer (tablet computer), a mobile phone, an MP3 player, an MP4 player, and the like.
In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the elements is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
In addition, each functional unit in each embodiment of the present specification may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in hardware plus software functional units.
The integrated units implemented in the form of software functional units described above may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to perform part of the steps of the methods described in the embodiments of the present specification. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a read-only memory (ROM), a random-access memory (RAM), a magnetic disk, or an optical disk, etc.
The foregoing description of the preferred embodiments is provided for the purpose of illustration only, and is not intended to limit the scope of the disclosure, since any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the disclosure are intended to be included within the scope of the disclosure.
Claims (10)
1. A timeout verification method, applied to a tester of a timeout verification system, the method performing a timeout verification process a plurality of times, comprising:
sending test messages to a controller to be diagnosed in different message periods;
and verifying the overtime time of the controller to be diagnosed for detecting the lost message according to the message period corresponding to the target test message detected by the controller to be diagnosed.
2. The method of claim 1, wherein sending test messages to the controller to be diagnosed at different message periods comprises:
the test message is sent to the controller to be diagnosed for the Nth time in a target period; the target period is obtained after overlapping the preset time length for N-1 times by taking the period to be detected as the initial period;
outputting a fault code aiming at the test message which is transmitted for the nth time and is lost by the controller to be diagnosed when the controller to be diagnosed is read, and outputting the time corresponding to the target period;
verifying the timeout time of the detection of the lost message by the controller to be diagnosed according to the message period corresponding to the target test message detected to be lost by the controller to be diagnosed, wherein the method comprises the following steps:
and verifying the overtime time of the lost message detected by the controller to be diagnosed according to the time corresponding to the target period.
3. The method of claim 2, wherein when the controller to be diagnosed is not read to output a fault code for the test message sent for the nth time that is lost, adding a preset time length to the target period, and sending the test message to the controller to be diagnosed for the n+1th time.
4. The method according to claim 1, wherein verifying the timeout period for the controller to be diagnosed to detect the missing message according to the message period corresponding to the target test message detected to be missing by the controller to be diagnosed comprises:
when the controller to be diagnosed detects that the message period corresponding to the lost target test message is within the error range of the period to be diagnosed, verifying that the overtime time of the controller to be diagnosed, which detects the lost message, is within the lost time range corresponding to the period to be diagnosed, and determining that the overtime time of the controller to be diagnosed is normal.
5. The method according to claim 1, wherein verifying the timeout period for the controller to be diagnosed to detect the missing message according to the message period corresponding to the target test message detected to be missing by the controller to be diagnosed comprises:
and when the controller to be diagnosed detects that the message period corresponding to the lost target test message is not in the error range of the period to be diagnosed, determining that the timeout time of the controller to be diagnosed is abnormal.
6. The method of claim 1, wherein the timeout verification system further comprises a programmable power supply, each time a timeout verification process is performed, before sending test messages to the controller to be diagnosed with different message periods, further comprising:
controlling the program-controlled power supply to be electrified, and clearing the historical fault code;
and verifying the timeout time of the detection of the lost message by the controller to be diagnosed according to the message period corresponding to the target test message detected to be lost by the controller to be diagnosed, and further comprising:
recording the result of overtime verification of the controller to be diagnosed for detecting the lost message;
controlling the program-controlled power supply to be powered down;
and checking the timeout verification result of the lost message detected by the controller to be diagnosed after the timeout verification is executed for a plurality of times.
7. A timeout validation apparatus, wherein the tester is configured to validate a timeout, the method performing a timeout validation process a plurality of times, comprising:
the message sending module is used for sending test messages to the controller to be diagnosed in different message periods;
and the verification module is used for verifying the timeout time of the detection of the lost message by the controller to be diagnosed according to the message period corresponding to the target test message which is detected to be lost by the controller to be diagnosed.
8. The apparatus of claim 7, wherein the message sending module comprises:
the period sending submodule is used for sending the test message to the controller to be diagnosed for the nth time in the target period; the target period is obtained after overlapping the preset time length for N-1 times by taking the period to be detected as the initial period;
the reading sub-module is used for outputting a fault code aiming at the test message which is transmitted for the nth time and outputting the time corresponding to the target period when the controller to be diagnosed is read;
the verification module is specifically configured to verify the timeout time of the detection of the lost message by the controller to be diagnosed according to the time corresponding to the target period.
9. An apparatus, comprising:
at least one processor; and at least one memory communicatively coupled to the processor, wherein the device is coupled to the tester, the memory storing program instructions executable by the processor, the processor invoking the program instructions to control the tester to perform the method of any of claims 1-6.
10. A computer readable storage medium storing computer instructions for causing a computer to perform the method of any one of claims 1 to 6.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116820866A (en) * | 2023-08-28 | 2023-09-29 | 北京芯驰半导体科技有限公司 | Verification method and platform for abnormality detection circuit of AXI bus transmission |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116820866A (en) * | 2023-08-28 | 2023-09-29 | 北京芯驰半导体科技有限公司 | Verification method and platform for abnormality detection circuit of AXI bus transmission |
| CN116820866B (en) * | 2023-08-28 | 2023-11-28 | 北京芯驰半导体科技有限公司 | Verification method and platform for abnormality detection circuit of AXI bus transmission |
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