CN116047278A - FPGA logic parallel loading circuit fault diagnosis system and method - Google Patents

FPGA logic parallel loading circuit fault diagnosis system and method Download PDF

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CN116047278A
CN116047278A CN202211701604.XA CN202211701604A CN116047278A CN 116047278 A CN116047278 A CN 116047278A CN 202211701604 A CN202211701604 A CN 202211701604A CN 116047278 A CN116047278 A CN 116047278A
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fpga
prom
signal
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fault diagnosis
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朱志强
杨媛媛
孙靖国
李斌
黄海涛
徐玉杰
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Xian Aeronautics Computing Technique Research Institute of AVIC
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3177—Testing of logic operation, e.g. by logic analysers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract

The invention provides a fault diagnosis system and a fault diagnosis method for an FPGA logic parallel loading circuit, wherein the fault diagnosis system comprises the following steps: logic parallel loading circuit formed by interconnection of FPGA chip and PROM chip; taking a plurality of signal points between the FPGA chip and the PROM chip as specific test points; the intelligent logic parallel loading circuit further comprises a microprocessor, the microprocessor accesses a host interface designed in the FPGA chip through an external host interface, samples signals on specific test points through discrete quantity interfaces, reads JTAG interface information of the FPGA module through JTAG interfaces to execute a fault diagnosis program, and simultaneously, the microprocessor intelligently analyzes test results and accurately positions fault points of the logic parallel loading circuit in combination with external tests among the specific test points. The invention realizes the intelligent detection and analysis of the FPGA logic parallel loading circuit, and greatly improves the detection efficiency and the positioning accuracy of the FPGA logic loading abnormality related faults.

Description

FPGA logic parallel loading circuit fault diagnosis system and method
Technical Field
The invention relates to the technical field of embedded system design of FPGA (field programmable gate array), in particular to a fault diagnosis system and method for an FPGA logic parallel loading circuit.
Background
The embedded system design technology based on the FPGA is widely applied to various high and new technology application fields, different functions can be realized by loading different logics and using the FPGA as a core functional circuit, the logic loading of the FPGA is realized by adopting parallel loading circuit design at present, the logic is stored in a PROM, and the logic is loaded to the FPGA by the PROM after power-on operation.
The embedded products applied to the new generation avionics system have the characteristics of high module density, complex use environment and the like, and in the processes of module production, debugging and outfield use, the situation that the FPGA cannot normally load logic due to various problems such as chips, welding spots, power supply and the like often occurs, so that the products cannot normally work, the FPGA and PROM devices in the parallel loading circuit are BGA packaging devices, the signals are numerous, and the testing is difficult due to the fact that no external test point exists, so that the logic loading fault positioning is extremely complex and difficult.
Disclosure of Invention
In view of this, the embodiment of the application provides a fault diagnosis method for an FPGA logic parallel loading circuit, which realizes intelligent detection and analysis of logic failure loading faults caused by chip, welding spot, power supply and other anomalies of the FPGA logic parallel loading circuit, and greatly improves detection efficiency and positioning accuracy of faults related to loading anomalies of the FPGA logic.
The embodiment of the application provides the following technical scheme: an FPGA logic parallel loading circuit fault diagnosis system comprising:
logic parallel loading circuit formed by interconnection of FPGA chip and PROM chip; taking a plurality of signal points between the FPGA chip and the PROM chip as specific test points;
the system comprises a logic parallel loading circuit, a specific test point, a microprocessor, a discrete quantity interface, a fault diagnosis program and an intelligent analysis on test results by accessing the host interface designed in the FPGA chip through the external host interface, sampling signals on the specific test point through the discrete quantity interface, reading JTAG interface information of the FPGA module through the JTAG interface, and simultaneously combining impedance detection and signal waveform detection among the specific test points.
According to one embodiment of the application, a PROM access control unit is designed inside the FPGA chip, and the microprocessor performs access control operation on the PROM access control unit through a host interface so as to perform read/write access control on the PROM chip.
According to one embodiment of the present application, the PROM access control unit includes a host interface and a PROM control interface, where the PROM access control unit receives a PROM read/write command issued by the host through the host interface, and executes the PROM read/write command on the PROM chip through the PROM control interface after parsing the PROM read/write command.
According to one embodiment of the present application, the plurality of signal points includes a pull-up/pull-down resistor signal terminal pad and a power signal point between the FPGA chip and the PROM chip.
The application also provides a fault diagnosis method based on the FPGA logic parallel loading circuit fault diagnosis system, which comprises the following steps:
taking a plurality of signal points between the FPGA chip and the PROM chip as specific test points;
and performing access control on a PROM access control unit designed in the FPGA chip by adopting a microprocessor, sampling signals on the specific test points, reading JTAG interface information of the FPGA module to execute a fault diagnosis program, performing intelligent analysis on test results by combining a signal waveform detection and impedance detection method on the specific test points, and finally positioning the failure loading of the FPGA to a determined failure signal and a determined FPGA or PROM failure pin.
According to one embodiment of the present application, the detection types in the fault diagnosis program include:
DONE load completion signal detection, program_b signal detection, init_b signal detection, M0, M1, M2 mode select signal detection, CLK clock signal detection, W write signal detection, R read signal detection, CS chip select signal detection, data signal detection, address signal detection.
According to one embodiment of the present application, the fault diagnosis program performs power supply detection before starting, where the power supply detection is that a microprocessor loads the logic in parallel, and the logic parallel loading circuit includes: the method comprises the steps that voltages of FPGA kernel voltage VCC_INT, FPGA configuration circuit voltage VCC_CFG, FPGA auxiliary voltage VCC_AUX, FPGA interface voltage VCCO, PROM power supply voltage VCC_1.8V and VCC_3.3V are tested, and if one voltage value is incorrect, a diagnosis result is that the power supply of the related voltage is abnormal; if the starting time among the voltages does not meet the power-on time sequence requirement, the power-on time sequence is diagnosed as abnormal, and the test result is output through the serial port.
According to one embodiment of the present application, the signal waveform detection and impedance detection method includes: and defining a signal end welding spot of the pull-up/pull-down resistor between the FPGA chip and the PROM chip as a specific test point, measuring the static resistance value of the signal end welding spot of the pull-up/pull-down resistor by adopting a universal meter, and measuring the signal waveform at the signal end welding spot of the pull-up/pull-down resistor by adopting an oscilloscope.
Aiming at the problems that logic cannot be loaded and faults are difficult to locate due to the abnormality of chips, welding spots, power supply and the like in the production and use processes of the FPGA logic parallel loading circuit, the invention innovatively provides a fault diagnosis method of the FPGA logic parallel loading circuit, thereby realizing the intelligent detection and analysis of the related faults of the FPGA logic parallel loading circuit and greatly improving the detection efficiency and the positioning accuracy of the related faults of the FPGA logic loading abnormality. The specific technical effects are as follows:
(1) The invention provides an effective means of fault detection: aiming at a dual BGA device interconnection circuit formed by the FPGA and the PROM, an effective means of fault detection is provided;
(2) The invention provides a test point-free interconnection signal testing method: aiming at direct connection signals between the FPGA and the PROM, an intelligent detection means based on host interface access is provided;
(3) Intelligent analysis and positioning fault points: and designing a PROM access control unit, executing diagnosis test operation by a microprocessor, and intelligently analyzing and positioning related fault points of the FPGA logic parallel loading circuit by combining related external test results.
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In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a circuit diagram of fault diagnosis of an FPGA logic parallel loading circuit according to an embodiment of the present invention.
Detailed Description
Embodiments of the present application are described in detail below with reference to the accompanying drawings.
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The technical solution of the present invention will be clearly and completely described below in detail with reference to the accompanying drawings in combination with the embodiments, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1, the embodiment of the invention provides a fault diagnosis system for an FPGA logic parallel loading circuit, which is based on a microprocessor executing a fault diagnosis program, and performs access control on a host interface designed inside the FPGA through an external host access interface, a discrete quantity interface and the like, samples a power supply and related control signals, and reads JTAG interface information of the FPGA; the FPGA is internally provided with a PROM access control unit, and the microprocessor can operate the PROM access control unit by a host interface so as to realize read/write access control on the PROM; the microprocessor executes diagnostic test operation, combines relevant external tests, performs intelligent analysis based on the test results, and finally accurately locates fault points such as relevant chips, welding points, welding spots, power supply and the like of the FPGA logic parallel loading circuit. The detection efficiency and the positioning accuracy of the FPGA logic loading abnormal related faults are greatly improved.
Aiming at a dual BGA device interconnection circuit formed by an FPGA and a PROM and direct connection signals between the FPGA and the PROM, the invention provides an intelligent detection means based on host interface access, designs a PROM access control unit, and a microprocessor executes diagnostic test operation and intelligently analyzes and locates relevant fault points of an FPGA logic parallel loading circuit in combination with relevant external test results.
The present embodiment executes a fault diagnosis program based on a microprocessor, and the fault diagnosis circuit is designed as shown in fig. 1. The interconnection between the FPGA and the PROM is the basic connection relation of the logic parallel loading circuit. The FPGA is internally provided with a PROM access control unit, and the microprocessor performs access control on a host interface which is internally arranged in the FPGA through an external host interface, so that read/write access control on the PROM is realized based on the PROM access control unit; the microprocessor samples the power supply and related control signals through a discrete quantity interface; and the microprocessor reads JTAG interface information of the FPGA through the JTAG interface.
The PROM access control unit comprises a host interface and a PROM control interface, and has the function of executing PROM read-write operation issued by the host. In the read-write process, a PROM access control unit firstly analyzes a read/write command of a host interface, then sends the read/write command to the PROM interface, and executes command ending operation at a specific time point; data on the bus needs to be latched and passed to the host interface at a specific point in time for a read operation. The PROM access control unit and other main functional logic in the FPGA share host interface resources and run in parallel with other functional logic.
And the microprocessor executes diagnostic test operation, combines related external tests, performs intelligent analysis based on the test results, and finally accurately locates related faults of the FPGA logic parallel loading circuit.
The diagnostic method is described below in connection with the relevant signals and the specific operation.
(1) Power supply detection
The microprocessor tests voltages such as FPGA kernel voltage VCC_INT, FPGA configuration circuit voltage VCC_CFG, FPGA auxiliary voltage VCC_AUX, FPGA interface voltage VCCO, PROM power supply related voltage VCC_1.8V or VCC_3.3V related to the FPGA parallel loading circuit through an IO interface, and if a certain voltage value is incorrect, the diagnosis result is that the related voltage power supply is abnormal; if the starting time among the voltages does not meet the power-on time sequence requirement, the power-on time sequence is diagnosed as abnormal. And outputting the test result through a serial port.
(2) DONE load complete signal detection
The point A is defined as a pin welding point of a DONE loading completion signal of the FPGA, and a microprocessor reads a DONE loading completion signal state mark DONE_JTAG through a JTAG interface after the module is electrified; the microprocessor reads a DONE loading completion signal state mark DONG_MCU through an IO interface; and judging the relevant faults of the DONE loading completion signal according to the following diagnosis table, and outputting the test result through the serial port.
TABLE 1DONE loading completion signal detection table
Figure BDA0004024388190000061
(3) Program_B signal detection
The point B is defined as a pull-up resistor signal end welding spot of a PROGRAM_B signal, the point C is defined as a PROGRAM_B signal pin welding spot of an FPGA, and the point D is defined as a PROGRAM_B signal pin welding spot of a PROM. Measuring a static resistance value R_PROGRAM_B at the point B through a universal meter; after the module is powered on, the microprocessor reads a PROGRAM_B_MCU through an IO interface. And judging the related faults of the PROGRAM_B signal according to the following diagnosis table, and outputting the test result through the serial port.
Table 2PROGRAM_B signal detection table
Figure BDA0004024388190000062
Figure BDA0004024388190000071
(4) INIT_B signal detection
The E point is defined as the pull-up resistor signal end welding point of the INIT_B signal, the F point is defined as the INIT_B signal pin welding point of the FPGA, and the G point is defined as the INIT_B signal pin welding point of the PROM. Measuring a static resistance value R_INIT_B at the E point through a universal meter; after the module is powered on, the microprocessor reads the INIT_B signal state flag INIT_B_MCU through the IO interface. And judging the related faults of the INIT_B signal according to the following diagnosis table, and outputting the test result through the serial port.
Table 3init_b signal detection table
Figure BDA0004024388190000072
(5) M0, M1, M2 mode select signal detection
The H point is defined as a pull-up resistor signal end welding spot of a mode selection signal 'M0 signal', the I point is defined as a pull-up resistor signal end welding spot of a mode selection signal 'M1 signal', the G point is defined as a pull-up resistor signal end welding spot of a mode selection signal 'M2 signal', the K point is an 'M0 signal' pin welding spot of an FPGA, the L point is an 'M1 signal' pin welding spot of the FPGA, and the M point is an 'M2 signal' pin welding spot of the FPGA. Measuring a static resistance value R_M0 through a universal meter at a point H, measuring a static resistance value R_M1 through a universal meter at a point I, and measuring a static resistance value R_M2 through a universal meter at a point J; after the module is electrified, the microprocessor sets an M0 signal state mark M0_MCU through an IO interface, the microprocessor sets an M1 signal state mark M1_MCU through the IO interface, and the microprocessor sets an M2 signal state mark M2_MCU through the IO interface; the microprocessor reads the M0 signal state mark M0_JTAG through the JTAG interface, the microprocessor reads the M1 signal state mark M1_JTAG through the IO interface, and the microprocessor reads the M2 signal state mark M2_JTAG through the IO interface. And judging related faults of M0, M1 and M2 signals according to the following diagnosis table, and outputting test results through a serial port.
Table 4M0 signal detection table
Figure BDA0004024388190000081
Table 5M1 signal detection table
Figure BDA0004024388190000082
Figure BDA0004024388190000091
Table 6M2 signal detection table
Figure BDA0004024388190000092
(6) CLK clock signal detection
The output end of the crystal oscillator with the N point defined as the CLK clock signal is connected with a welding spot on the side of the resistor FPGA, the O point is a welding spot of a pin of the CLK clock signal of the FPGA, and the P point is a welding spot of a pin of the CLK clock signal of the PROM. Measuring a static resistance value R_CLK at the N point through a universal meter; after the module is electrified, measuring the waveform of the CLK clock signal at the N point by using an oscilloscope; the microprocessor respectively sets the values of M0, M1 and M2 through the IO interface, so that the loading mode of the FPGA after being electrified is a Master active mode and a Slave passive mode, when the FPGA is in the Master active mode, the resistor at the N position is removed, the FPGA outputs a CLK clock signal to the PROM, when the FPGA is in the Slave passive mode, the resistor at the N position is reserved, and the FPGA and the PROM receive the CLK clock signal provided by the crystal oscillator. And judging the related faults of the INIT_B signal according to the following diagnosis table, and outputting the test result through the serial port.
Table 7CLK clock signal detection table
Figure BDA0004024388190000101
(7) W write signal detection
A Q point is defined as a pull-up resistor signal end welding spot of a W write signal, a R point is defined as a W write signal pin welding spot of an FPGA, and a S point is defined as a W write signal pin welding spot of a PROM. Measuring a static resistance value R_W at a Q point through a universal meter; after the module is electrified, the waveform of the W writing signal is measured by an oscilloscope at the Q point, and the microprocessor controls the PROM access control unit to write the PROM through the host interface, and the W writing signal status flag W_PORT is used. And judging related faults of the W write signal according to the following diagnosis table, and outputting test results through the serial port.
Table 8W write signal detection table
Figure BDA0004024388190000111
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(8) R-read signal detection
The T point is defined as the signal end welding spot of the pull-down resistor of R read signal, the U point is defined as the pin welding spot of the R read signal of the FPGA, and the V point is defined as the pin welding spot of the R read signal of the PROM. Measuring a static resistance value R_R at a point T through a universal meter; after the module is electrified, the waveform of the W writing signal is measured by an oscilloscope at the T point, and the microprocessor controls the PROM access control unit to write the PROM through the host interface, and the R reading signal status flag R_PORT is used for the module. And judging the related faults of the R reading signals according to the following diagnosis table, and outputting test results through a serial port.
Table 9R read signal detection table
Figure BDA0004024388190000112
(9) CS chip select signal detection
The W point is defined as the signal end welding spot of the pull-down resistor of the CS chip select signal, the X point is defined as the pin welding spot of the W write signal of the FPGA, and the Y point is defined as the pin welding spot of the CS chip select signal of the PROM. Measuring a static resistance value R_CS at a W point through a universal meter; after the module is electrified, the waveform of the CS chip selection signal is measured by an oscilloscope at the W point, and the microprocessor controls the PROM access control unit to read/write the PROM through the host interface, and the CS chip selection signal status flag CS_PORT is used for controlling the microprocessor to read/write the PROM. And judging the related faults of the CS chip selection signals according to the following diagnosis table, and outputting test results through the serial port.
TABLE 10CS chip select Signal detection Table
Figure BDA0004024388190000121
(10) Data signal detection
And defining the Z point as a pull-down resistor signal end welding spot of a data signal, and measuring the waveform of the data signal at the Z point by using an oscilloscope after the module is powered on. The microprocessor operates the PROM access control unit through the host interface, sequentially writes the values 0x0, 0x1, 0x2, 0x4, 0x8, …, 0x80000, 0x100000, 0x200000 and 0x400000 into the address unit appointed by the PROM, reads the value in the address, judges whether the value is the same as the expected value, and circularly writes and reads the data to finish the traversal test of the high level '1' of all the data lines. And sequentially writing the values 0xFFFFFF, 0xFFFFFE, 0xFFFFFD, 0xFFFFFB, 0Xfffff7 …, 0Xf7FFFF, 0xEFFFFF, 0xFFFFF and 0xBFFFF into address units appointed by the PROM and reading the values in the addresses, judging whether the values are the same as expected values, and circularly writing and reading the data to finish traversal test of high level '0' of all data lines. And judging the related faults of the CS chip selection signals according to the following diagnosis table, and outputting test results through the serial port.
Table 11 data signal detection table
Figure BDA0004024388190000131
(11) Address signal detection
The microprocessor operates the PROM access control unit through the host interface, and aiming at a continuous address space (covering an address line to be tested) in the PROM, the current address value is given to the current address, the high-level 1 traversal is performed, the low-level 0 traversal is performed, the stored values are read out from the corresponding addresses in sequence, and the values are compared with the current address value to judge whether the reading and writing of the address bus are correct; and then turning the two traversing orders, firstly performing '0' traversing, then performing '1' traversing, then sequentially reading the stored numerical values from the corresponding addresses, comparing the numerical values with the current address values, and judging whether the reading and writing of the address bus are correct. And judging the related faults of the CS chip selection signals according to the following diagnosis table, and outputting test results through the serial port.
Table 12 address signal detecting table
Figure BDA0004024388190000132
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Figure BDA0004024388190000141
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions easily conceivable by those skilled in the art within the technical scope of the present application should be covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (8)

1. An FPGA logic parallel loading circuit fault diagnosis system, comprising:
logic parallel loading circuit formed by interconnection of FPGA chip and PROM chip; taking a plurality of signal points between the FPGA chip and the PROM chip as specific test points;
the system comprises a logic parallel loading circuit, a specific test point, a microprocessor, a discrete quantity interface, a fault diagnosis program and an intelligent analysis on test results by accessing the host interface designed in the FPGA chip through the external host interface, sampling signals on the specific test point through the discrete quantity interface, reading JTAG interface information of the FPGA module through the JTAG interface, and simultaneously combining impedance detection and signal waveform detection among the specific test points.
2. The FPGA logic parallel loading circuit fault diagnosis system according to claim 1, wherein a PROM access control unit is designed inside the FPGA chip, and the microprocessor performs access control operation on the PROM access control unit through a host interface to perform read/write access control on the PROM chip.
3. The fault diagnosis system of FPGA logic parallel loading circuit according to claim 2, wherein the PROM access control unit comprises a host interface and a PROM control interface, the PROM access control unit receives a PROM read/write command issued by a host through the host interface, and executes the PROM read/write command to the PROM chip through the PROM control interface after parsing.
4. The FPGA logic parallel loading circuit fault diagnosis system of claim 1, wherein the plurality of signal points include a pull-up/pull-down resistor signal terminal pad and a power signal point between the FPGA chip and the PROM chip.
5. A fault diagnosis method based on the FPGA logic parallel loading circuit fault diagnosis system according to any one of claims 1 to 4, comprising:
taking a plurality of signal points between the FPGA chip and the PROM chip as specific test points;
and performing access control on a PROM access control unit designed in the FPGA chip by adopting a microprocessor, sampling signals on the specific test points, reading JTAG interface information of the FPGA module to execute a fault diagnosis program, performing intelligent analysis on test results by combining a signal waveform detection and impedance detection method on the specific test points, and finally positioning the failure loading of the FPGA to a determined failure signal and a determined FPGA or PROM failure pin.
6. The fault diagnosis method according to claim 5, wherein the detection type in the fault diagnosis program includes:
DONE load completion signal detection, program_b signal detection, init_b signal detection, M0, M1, M2 mode select signal detection, CLK clock signal detection, W write signal detection, R read signal detection, CS chip select signal detection, data signal detection, address signal detection.
7. The method of claim 6, wherein the fault diagnosis program is characterized by detecting power supply before starting, and the power supply detection is implemented by a microprocessor in parallel loading circuit of the logic, and the method comprises the steps of: the method comprises the steps that voltages of FPGA kernel voltage VCC_INT, FPGA configuration circuit voltage VCC_CFG, FPGA auxiliary voltage VCC_AUX, FPGA interface voltage VCCO, PROM power supply voltage VCC_1.8V and VCC_3.3V are tested, and if one voltage value is incorrect, a diagnosis result is that the power supply of the related voltage is abnormal; if the starting time among the voltages does not meet the power-on time sequence requirement, the power-on time sequence is diagnosed as abnormal, and the test result is output through the serial port.
8. The fault diagnosis method according to claim 5, wherein the signal waveform detection and impedance detection method comprises: and defining a signal end welding spot of the pull-up/pull-down resistor between the FPGA chip and the PROM chip as a specific test point, measuring the static resistance value of the signal end welding spot of the pull-up/pull-down resistor by adopting a universal meter, and measuring the signal waveform at the signal end welding spot of the pull-up/pull-down resistor by adopting an oscilloscope.
CN202211701604.XA 2022-12-28 2022-12-28 FPGA logic parallel loading circuit fault diagnosis system and method Pending CN116047278A (en)

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