CN116033106A

CN116033106A - Image processing method and device for multiple sampling and electronic equipment

Info

Publication number: CN116033106A
Application number: CN202310297773.XA
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Moore Threads Technology Co Ltd
Current assignee: Moore Threads Technology Co Ltd
Priority date: 2023-03-24
Filing date: 2023-03-24
Publication date: 2023-04-28
Anticipated expiration: 2043-03-24
Also published as: CN116033106B

Abstract

The disclosure relates to the technical field of computers, and discloses an image processing method and device for multiple sampling, and electronic equipment, wherein the method comprises the following steps: transmitting a first data reading request for requesting to read a writing identifier and an edge identifier corresponding to a pixel block to be read stored in a target memory to the target memory; judging whether the pixel block to be read is an effective pixel block according to the writing identification corresponding to the pixel block to be read, and judging whether the pixel block to be read is positioned at the image edge according to the edge identification corresponding to the pixel block to be read; under the condition that the pixel block to be read is determined to be an effective pixel block and is not at the image edge, a second data reading request for requesting to read one sub-pixel point in each pixel point in the pixel block to be read is sent to a target memory; and receiving one sub-pixel point in each pixel point in the pixel block to be read returned by the target memory. The embodiment of the disclosure can effectively improve the data reading efficiency in the image processing process under the multi-sampling scene.

Description

Image processing method and device for multiple sampling and electronic equipment

Technical Field

The disclosure relates to the field of computer technology, and in particular, to an image processing method and apparatus for multiple sampling, and an electronic device.

Background

In image processing, processing of pixels may involve a read-write process of pixel data. The pixel data read at a time may occupy hundreds or thousands of bits wide, and the pixel data read and write of the entire image may involve an extra large order of magnitude of data interaction. In a multi-sampling scene, each pixel point further comprises a plurality of sub-pixel points, and the data interaction quantity is multiplied. In the related art, in a multi-sampling scene, redundant data interaction exists in a pixel data reading process in an image processing process, so that image processing efficiency is affected.

Disclosure of Invention

The disclosure provides an image processing method and device for multiple sampling and a technical scheme of electronic equipment.

According to an aspect of the present disclosure, there is provided an image processing method for multi-sampling, including: a first data reading request is sent to a target memory, wherein the first data reading request is used for requesting to read a writing identifier and an edge identifier corresponding to a pixel block to be read stored in the target memory, and each pixel point in the pixel block to be read comprises a plurality of sub-pixel points; judging whether the pixel block to be read is an effective pixel block according to the writing identification corresponding to the pixel block to be read returned by the target memory, and judging whether the pixel block to be read is at the image edge according to the edge identification corresponding to the pixel block to be read returned by the target memory; sending a second data reading request to the target memory under the condition that the pixel block to be read is an effective pixel block and is not at the image edge, wherein the second data reading request is used for requesting to read one sub-pixel point in each pixel point in the pixel block to be read; and receiving one sub-pixel point in each pixel point in the pixel block to be read returned by the target memory.

In one possible implementation, the method further includes: transmitting a third data reading request to the target memory under the condition that the pixel block to be read is an effective pixel block and is positioned at the image edge, wherein the third data reading request is used for requesting to read all sub-pixel points in each pixel point in the pixel block to be read; and receiving all sub-pixel points in each pixel point in the pixel block to be read returned by the target memory.

In one possible implementation manner, the writing identifier corresponding to the pixel block to be read includes a writing identifier corresponding to each pixel point in the pixel block to be read; the step of judging whether the pixel block to be read is an effective pixel block according to the writing identification corresponding to the pixel block to be read returned by the target memory, includes: determining the pixel block to be read as an effective pixel block under the condition that at least one effective writing identifier exists in the writing identifiers corresponding to the pixel block to be read, wherein the pixel point corresponding to the effective writing identifier is effective pixel data in the pixel block to be read; or determining that the pixel block to be read is not an effective pixel block under the condition that the writing identification corresponding to each pixel point in the writing identification corresponding to the pixel block to be read is an invalid writing identification.

In one possible implementation manner, in a case that the writing identifier corresponding to the pixel block to be read includes both a valid writing identifier and an invalid writing identifier, the method further includes: and replacing the pixel value of the sub-pixel point in the pixel point corresponding to the invalid writing mark in the read pixel block to be read with a preset background pixel value.

According to an aspect of the present disclosure, there is provided an image processing method for multiple sampling, the method being applied to a target memory divided into N pixel storage groups, where N is a positive integer greater than or equal to 2, the method comprising: receiving a data parallel write request, wherein the data parallel write request is used for requesting 2 in a target image ^m Writing the pixel blocks into the target memory in parallel, wherein 2 ^m Is a positive integer of 2 or more and N or less; determining said 2 ^m A pixel storage group identifier corresponding to each pixel block in the pixel blocks, wherein the pixel storage group identifier is 2 ^m Adjacent pixel blocks in the pixel blocks correspond to different pixel storage group identifications; according to said 2 ^m Storing group identifiers corresponding to each pixel block in the pixel blocks, and carrying out the process of 2 ^m Writing blocks of pixels in parallel to the target memory, and determining the 2 ^m And writing identification and edge identification corresponding to each pixel block in the pixel blocks.

In one possible implementation manner, each pixel storage group includes M pixel storage rows, where M is a positive integer greater than or equal to 2, and the target memory includes an identification storage unit with a size of m×n; said determining said 2 ^m The writing identification corresponding to each pixel block in the pixel blocks comprises the following steps: for said 2 ^m And determining a writing identification in the ith column and the jth row in the identification storage unit according to whether each pixel point in the pixel block is successfully written into the jth pixel storage row in the ith pixel storage group or not by any pixel block in the pixel blocks, wherein the writing identification in the ith column and the jth row comprises the writing identification corresponding to each pixel point in the pixel block.

In one possible implementation, the method is directed to the step 2 ^m Any one pixel block in the pixel blocks, determining the writing identification in the ith column and the jth row in the identification storage unit according to whether each pixel point in the pixel block is successfully written into the jth pixel storage row in the ith pixel storage group, wherein the writing identification comprises the following steps: for any pixel point in the pixel block, determining a writing identifier corresponding to the pixel point as an effective writing identifier when the pixel point is successfully written into the j-th pixel storage row in the i-th pixel storage group; or determining that the writing identification corresponding to the pixel point is an invalid writing identification under the condition that the pixel point is not successfully written into the j-th pixel storage row in the i-th pixel storage group.

In one possible implementation, each pixel includes a plurality of sub-pixels; said determining said 2 ^m The edge identifier corresponding to each pixel block in the pixel blocks comprises: for a pixel block written into the jth pixel storage row in the ith pixel storage group, determining an edge identifier in the ith column and the jth row in the identifier storage unit as a valid edge identifier in the case that at least one edge pixel point exists in the pixel block, wherein the valid edge identifier is used for indicating that the pixel block is at an image edge; or, in the case that all pixel points in the pixel block are non-edge pixel points, determiningAnd the edge mark in the ith column and the jth row in the mark storage unit is an invalid edge mark, wherein the invalid edge mark is used for indicating that the pixel block is not at the image edge.

According to an aspect of the present disclosure, there is provided an image processing method for multi-sampling, including: sending a first data parallel reading request to a target memory, wherein the first data parallel reading request is used for requesting to read 2 stored in the target memory in parallel ^m Writing identification and edge identification corresponding to pixel blocks to be read, wherein the target memory is divided into N pixel storage groups, and the target memory is divided into 2 pixel storage groups ^m The pixel blocks to be read are stored in different pixel storage groups, N is a positive integer greater than or equal to 2, 2 ^m Is a positive integer of 2 or more and N or less; for said 2 ^m Any one of the pixel blocks to be read is judged whether to be an effective pixel block according to a writing identification corresponding to the pixel block to be read returned by the target memory, and whether the pixel block to be read is positioned at an image edge or not is judged according to an edge identification corresponding to the pixel block to be read returned by the target memory; sending a second data parallel read request to the target memory, wherein the second data parallel read request is used for requesting the data of the data storage device 2 ^m In the effective pixel blocks to be read, one sub-pixel point in each pixel point in the effective pixel blocks to be read which are not positioned at the image edge and all sub-pixel points in each pixel point in the effective pixel blocks to be read which are positioned at the image edge are read in parallel; receiving the 2 returned by the target memory ^m In the effective pixel block to be read, one sub-pixel point in each pixel point in the effective pixel block to be read which is not positioned at the image edge, and all sub-pixel points in each pixel point in the effective pixel block to be read which is positioned at the image edge.

According to an aspect of the present disclosure, there is provided an image processing apparatus for multi-sampling, including: the device comprises an identification reading module, a target memory, a storage module and a storage module, wherein the identification reading module is used for sending a first data reading request to the target memory, the first data reading request is used for requesting to read a writing identification and an edge identification corresponding to a pixel block to be read stored in the target memory, and each pixel point in the pixel block to be read comprises a plurality of sub-pixel points; the judging module is used for judging whether the pixel block to be read is an effective pixel block according to the writing identification corresponding to the pixel block to be read returned by the target memory, and judging whether the pixel block to be read is at the image edge according to the edge identification corresponding to the pixel block to be read returned by the target memory; the pixel reading module is used for sending a second data reading request to the target memory under the condition that the pixel block to be read is determined to be an effective pixel block and is not positioned at the image edge, wherein the second data reading request is used for requesting to read one sub-pixel point in each pixel point in the pixel block to be read; and the receiving module is used for receiving one sub-pixel point in each pixel point in the pixel block to be read returned by the target memory.

According to an aspect of the present disclosure, there is provided an image processing apparatus for multiple sampling, the apparatus being applied to a target memory, the target memory being divided into N pixel storage groups, where N is a positive integer of 2 or more, the apparatus comprising: a pixel writing module for receiving a data parallel writing request, wherein the data parallel writing request is used for requesting 2 in a target image ^m Writing the pixel blocks into the target memory in parallel, wherein 2 ^m Is a positive integer of 2 or more and N or less; a storage packet selection module for determining said 2 ^m A pixel storage group identifier corresponding to each pixel block in the pixel blocks, wherein the pixel storage group identifier is 2 ^m Adjacent pixel blocks in the pixel blocks correspond to different pixel storage group identifications; an identification generation module for generating identification information according to the method 2 ^m Storing group identifiers corresponding to each pixel block in the pixel blocks, and carrying out the process of 2 ^m Writing blocks of pixels in parallel to the target memory, and determining the 2 ^m And writing identification and edge identification corresponding to each pixel block in the pixel blocks.

According to an aspect of the present disclosure, there is provided an image processing apparatus for multi-sampling, including: identification reading module The method comprises the steps of sending a first data parallel reading request to a target memory, wherein the first data parallel reading request is used for requesting to read 2 stored in the target memory in parallel ^m Writing identification and edge identification corresponding to pixel blocks to be read, wherein the target memory is divided into N pixel storage groups, and the target memory is divided into 2 pixel storage groups ^m The pixel blocks to be read are stored in different pixel storage groups, N is a positive integer greater than or equal to 2, 2 ^m Is a positive integer of 2 or more and N or less; a judging module for aiming at the 2 ^m Any one of the pixel blocks to be read is judged whether to be an effective pixel block according to a writing identification corresponding to the pixel block to be read returned by the target memory, and whether the pixel block to be read is positioned at an image edge or not is judged according to an edge identification corresponding to the pixel block to be read returned by the target memory; a pixel reading module, configured to send a second data parallel reading request to the target memory, where the second data parallel reading request is used to request the data processing unit 2 ^m In the effective pixel blocks to be read, one sub-pixel point in each pixel point in the effective pixel blocks to be read which are not positioned at the image edge and all sub-pixel points in each pixel point in the effective pixel blocks to be read which are positioned at the image edge are read in parallel; a receiving module, configured to receive the 2 returned by the target memory ^m In the effective pixel block to be read, one sub-pixel point in each pixel point in the effective pixel block to be read which is not positioned at the image edge, and all sub-pixel points in each pixel point in the effective pixel block to be read which is positioned at the image edge.

According to an aspect of the present disclosure, there is provided an electronic apparatus including: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to invoke the instructions stored in the memory to perform the above method.

According to an aspect of the present disclosure, there is provided a computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the above-described method.

In the embodiment of the disclosure, a first data reading request for requesting to read a writing identifier and an edge identifier corresponding to a pixel block to be read stored in a target memory is sent to the target memory, whether the pixel block to be read is an effective pixel block is judged according to the writing identifier corresponding to the pixel block to be read returned by the target memory, whether the pixel block to be read is at an image edge is judged according to the edge identifier corresponding to the pixel block to be read returned by the target memory, and a second data reading request for requesting to read one sub-pixel point in each pixel point in the pixel block to be read is sent to the target memory under the condition that the pixel block to be read is the effective pixel block and is not at the image edge. Because the pixel sources of the plurality of sub-pixel points in each pixel point in the effective pixel block which is not positioned at the image edge are the same, and the corresponding pixel values are the same, based on the writing identification and the edge identification, only one sub-pixel point in each pixel point in the effective pixel block which is not positioned at the image edge can be read, and repeated reading of the plurality of sub-pixel points with the same pixel value is not needed, so that the data reading efficiency in the image processing process under the multi-sampling scene is effectively improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the technical aspects of the disclosure.

Fig. 1 shows a schematic diagram of a multisampling sub-pixel point in accordance with an embodiment of the present disclosure.

Fig. 2 shows a flowchart of an image processing method for multisampling according to an embodiment of the present disclosure.

Fig. 3 shows a schematic diagram of identification and pixel data corresponding to one pixel block according to an embodiment of the present disclosure.

Fig. 4 shows a schematic diagram of identification and pixel data corresponding to one pixel block according to an embodiment of the present disclosure.

Fig. 5 shows a schematic diagram of identification and pixel data corresponding to one pixel block according to an embodiment of the present disclosure.

Fig. 6 shows a flowchart of an image processing method for multisampling according to an embodiment of the present disclosure.

Fig. 7 is a schematic diagram of a structure of a target memory according to an embodiment of the disclosure.

Fig. 8 shows a flowchart of an image processing method for multisampling according to an embodiment of the present disclosure.

Fig. 9 shows a block diagram of an image processing apparatus for multiple sampling according to an embodiment of the present disclosure.

Fig. 10 shows a block diagram of an image processing apparatus for multiple sampling according to an embodiment of the present disclosure.

Fig. 11 shows a block diagram of an image processing apparatus for multiple sampling according to an embodiment of the present disclosure.

Fig. 12 shows a block diagram of an electronic device, according to an embodiment of the disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, and may mean including any one or more elements selected from the group consisting of A, B and C.

Furthermore, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.

In image processing, processing of pixels may involve a process of reading pixel data. The pixel data read at a time may occupy hundreds or thousands of bits wide, and the pixel data read for the entire image may involve an extra large order of magnitude of data interaction. In the case where an image edge needs to be determined, for example, in a scene of edge extraction, image rasterization, or the like, multiple sampling needs to be performed on the image, and each pixel point in the image is divided into a plurality of smaller sub-pixel points, so that edge judgment is performed.

For example, in an image rasterization scene, the pixels covered by the triangles corresponding to the image rasterization are discrete and intermittent, thus forming jaggies. To approximate a real effect, the desired result is that each pixel contributes a color value proportionally to the area covered by the square of the current pixel by the triangle under the image subdivision. Namely, the image is subjected to multiple sampling, each pixel point in the image is divided into a plurality of smaller sub-pixel points, and then whether the center of the sub-pixel point is in a triangle is judged, so that a rough triangle coverage duty ratio result can be obtained. Fig. 1 shows a schematic diagram of a multisampling sub-pixel point in accordance with an embodiment of the present disclosure. As shown in fig. 1, for a triangle corresponding to an image at the time of rasterization, the image is subjected to multiple sampling, and each pixel point in the image is divided into 4 sub-pixel points. In a multi-sampling scene, the number of data interactions increases by a factor due to the fact that each pixel includes multiple sub-pixels.

In order to improve the pixel data reading rate and further improve the image processing efficiency, the disclosure provides an image processing method for multiple sampling, which can effectively improve the data reading rate in the image processing process under the multiple sampling scene and further improve the image processing efficiency. The image processing method for multi-sampling provided by the present disclosure is described in detail below.

Fig. 2 shows a flowchart of an image processing method for multisampling according to an embodiment of the present disclosure. The method may be performed by an electronic device, such as a terminal device or a server, the terminal device may be a User Equipment (UE), a mobile device, a User terminal, a cellular phone, a cordless phone, a personal digital assistant (Personal Digital Assistant, PDA), a handheld device, a computing device, a vehicle mounted device, a wearable device, etc., and the method may be implemented by a processor invoking computer readable instructions stored in a memory. Alternatively, the method may be performed by a server. As shown in fig. 2, the method includes:

in step S21, a first data reading request is sent to the target memory, where the first data reading request is used to request to read a write identifier and an edge identifier corresponding to a pixel block to be read stored in the target memory, and each pixel point in the pixel block to be read includes multiple sub-pixel points.

The target memory stores both the image and the writing identification and the edge identification corresponding to each pixel block in the image. For example, for any pixel block, after a write operation of writing the pixel block into the target memory is executed, a write identifier and an edge identifier corresponding to the pixel block are determined according to the actual write situation, and are stored in the target memory.

When image processing is required for a pixel block in an image, the pixel block needs to be read from the target memory. In order to reduce redundant data interaction, before a pixel block to be read is read, a first data reading request for requesting to read a writing identifier and an edge identifier corresponding to the pixel block to be read is sent to a target memory.

In step S22, according to the writing identifier corresponding to the pixel block to be read returned by the target memory, it is determined whether the pixel block to be read is an effective pixel block, and according to the edge identifier corresponding to the pixel block to be read returned by the target memory, it is determined whether the pixel block to be read is at the image edge.

After the writing identification and the edge identification corresponding to the pixel block to be read are read from the target memory, whether the pixel block to be read is an effective pixel block or not can be judged according to the writing identification corresponding to the pixel block to be read, namely, whether the pixel block to be read is an effective pixel block written into the target memory or not, and whether the pixel block to be read is positioned at the image edge or not is judged according to the edge identification corresponding to the pixel block to be read.

The detailed description of how to determine whether the pixel block to be read is an effective pixel block according to the writing identifier corresponding to the pixel block to be read and how to determine whether the pixel block to be read is at the image edge according to the edge identifier corresponding to the pixel block to be read will be described in detail later in connection with possible implementation manners of the disclosure, which is not repeated here.

In step S23, if the pixel block to be read is determined to be a valid pixel block and not located at the image edge, a second data read request is sent to the target memory, where the second data read request is used to request to read one sub-pixel point in each pixel point in the pixel block to be read.

Under the condition that the pixel block to be read is determined to be an effective pixel block and is not located at the image edge according to the writing identification corresponding to the pixel block to be read, as the pixel sources of a plurality of sub-pixel points in each pixel point in the effective pixel block which is not located at the image edge are the same, the corresponding pixel values are the same, and therefore a second data reading request for requesting to read one sub-pixel point in each pixel point in the pixel block to be read can be sent to the target memory. At this time, repeated reading of a plurality of sub-pixel points with the same pixel value is not needed, so that the data reading efficiency in the multi-sampling scene is improved.

In step S24, a sub-pixel point in each pixel point in the pixel block to be read returned by the target memory is received.

And based on the second data reading request, reading one sub-pixel point in each pixel point in the pixel block to be read from the target memory.

According to the embodiment of the disclosure, since the pixel sources of the plurality of sub-pixel points in each pixel point in the effective pixel block which is not at the image edge are the same, and the corresponding pixel values are the same, based on the writing identification and the edge identification, only one sub-pixel point in each pixel point in the effective pixel block which is not at the image edge can be read, and repeated reading of the plurality of sub-pixel points with the same pixel values is not needed, so that the data reading efficiency in the image processing process under the multi-sampling scene is effectively improved.

In one possible implementation, the method further includes: under the condition that the pixel block to be read is an effective pixel block and is positioned at the image edge, a third data reading request is sent to a target memory, wherein the third data reading request is used for requesting to read all sub-pixel points in each pixel point in the pixel block to be read; and receiving all sub-pixel points in each pixel point in the pixel block to be read returned by the target memory.

Under the condition that the pixel block to be read is determined to be an effective pixel block and is positioned at the image edge according to the writing identification corresponding to the pixel block to be read, a third data reading request for requesting to read all the sub-pixel points in each pixel point in the pixel block to be read can be sent to the target memory in order to ensure the complete validity of data in the multi-sampling scene because the pixel sources of the sub-pixel points in each pixel point in the effective pixel block positioned at the image edge are different.

The number of pixel points included in the pixel block to be read and the number of sub-pixel points included in each pixel point can be flexibly set according to actual situations, which is not particularly limited in the disclosure.

The sending of the first data reading request, the second data reading request and the third data reading request may be a pixel processing module, where the pixel processing module is configured to perform a subsequent image processing operation on the read pixel block to be read. The pixel processing module may be a hardware module or a software program, which is not specifically limited in this disclosure.

In one possible implementation manner, the writing identifier corresponding to the pixel block to be read includes a writing identifier corresponding to each pixel point in the pixel block to be read; judging whether the pixel block to be read is an effective pixel block according to the writing identification corresponding to the pixel block to be read returned by the target memory, comprising: under the condition that at least one effective writing identifier exists in the writing identifiers corresponding to the pixel blocks to be read, determining the pixel blocks to be read as effective pixel blocks, wherein the pixel points corresponding to the effective writing identifiers are effective pixel data in the pixel blocks to be read; or determining that the pixel block to be read is not an effective pixel block under the condition that the writing identification corresponding to each pixel point in the writing identifications corresponding to the pixel block to be read is an invalid writing identification.

The writing identification corresponding to the pixel block to be read comprises writing identification corresponding to each pixel point in the pixel block to be read, and if it is determined that at least one effective writing identification exists in the writing identification corresponding to the pixel block to be read, it can be determined that at least one pixel point in the pixel block to be read is effectively written into the target memory, and at this time, it can be determined that the pixel block to be read is an effective pixel block.

The pixel block to be read comprises a plurality of pixel points, and the writing identification corresponding to the pixel block to be read comprises the writing identification corresponding to each pixel point. For example, the valid write flag is denoted by 0, and the invalid write flag is denoted by 1. The valid writing mark and the invalid writing mark can be represented by 0 and 1, and can be represented by other forms according to actual situations, and the disclosure is not particularly limited.

Fig. 3 shows a schematic diagram of identification and pixel data corresponding to one pixel block according to an embodiment of the present disclosure. As shown in fig. 3, the pixel block a to be read includes 4 pixel points: pixel 0-pixel 3, wherein the writing mark corresponding to pixel 0 is 1, the writing mark corresponding to pixel 1 is 1, the writing mark corresponding to pixel 2 is 1, and the writing mark corresponding to pixel 3 is 0; at this time, the write flag corresponding to the pixel block a to be read is 0111.

And under the condition that at least one effective writing identifier exists in the writing identifiers corresponding to the pixel blocks to be read, the condition that at least one pixel point in the pixel blocks to be read is effectively written into the target memory is indicated, that is, part or all of sub-pixel points in the at least one pixel point in the pixel blocks to be read are effectively written into the target memory, and at the moment, the pixel blocks to be read are determined to be effective pixel blocks. As shown in fig. 3, the writing identifier of the pixel block a to be read is 0111, which includes 1 valid writing identifier 0, which indicates that there is one pixel (a part or all of sub-pixels in the pixel 3) in the pixel block a to be read is effectively written into the target memory, at this time, the pixel block a to be read is determined to be an effective pixel block, and the pixel 3 corresponding to the valid writing identifier 0 corresponds to the effective pixel data in the pixel block a to be read. The pixel data length of the pixel block A to be read is 256bits, and the pixel point 3 corresponds to effective pixel data in the pixel block A to be read.

Fig. 4 shows a schematic diagram of identification and pixel data corresponding to one pixel block according to an embodiment of the present disclosure. As shown in fig. 4, the pixel block B to be read includes 4 pixel points: pixel 0-pixel 3, wherein the writing mark corresponding to pixel 0 is 0, the writing mark corresponding to pixel 1 is 1, the writing mark corresponding to pixel 2 is 0, and the writing mark corresponding to pixel 3 is 0; at this time, the writing identifier corresponding to the pixel block B to be read is 0010, which includes 3 valid writing identifiers 0, which indicates that 3 pixel points (pixel point 0, pixel point 2, and part or all of sub-pixel points in the pixel point 3) in the pixel block B to be read are effectively written into the target memory; thus, the pixel block B to be read is determined as a valid pixel block. The pixel data length of the pixel block B to be read is 256bits, and the pixel point 0, the pixel point 2 and the pixel point 3 corresponding to the mark 0 are effectively written, and the effective pixel data in the pixel block B to be read are correspondingly written.

And under the condition that the writing identification corresponding to each pixel point in the writing identification corresponding to the pixel block to be read is an invalid writing identification, indicating that all the pixel points in the pixel block to be read have no valid writing target memory, and determining that the pixel block to be read is not a valid pixel block at the moment. Fig. 5 shows a schematic diagram of identification and pixel data corresponding to one pixel block according to an embodiment of the present disclosure. As shown in fig. 5, the pixel block C to be read includes 4 pixel points, the writing identifier corresponding to the pixel block C to be read is 1111, and includes 4 invalid writing identifiers, which indicates that all the pixel points in the pixel block C to be read have no valid writing target memory, and at this time, it is determined that the pixel block C to be read is not a valid pixel block.

In one possible implementation manner, determining whether the pixel block to be read is at an image edge according to an edge identifier corresponding to the pixel block to be read returned by the target memory includes: under the condition that the edge mark corresponding to the pixel block to be read is a valid edge mark, determining that the pixel block to be read is positioned at the image edge; or determining that the pixel block to be read is not at the image edge under the condition that the edge mark corresponding to the pixel block to be read is an invalid edge mark.

For example, a valid edge indicator is indicated by 0 and an invalid edge indicator is indicated by 1. The valid edge marks and the invalid edge marks can be represented by 0 and 1, and can also be represented by other forms according to actual conditions, and the disclosure is not particularly limited to the valid edge marks and the invalid edge marks.

As shown in fig. 3, the pixel block a to be read is an effective pixel block, and the edge identifier corresponding to the pixel block a to be read is an invalid standard edge identifier 1, so that it can be determined that the pixel block a to be read is an effective pixel block and is not located at the image edge, and as shown in fig. 3, all the pixel points 0 to 3 are non-edge pixel points. At this time, the pixel sources of the sub-pixels in each pixel in the pixel block a to be read are the same, and the corresponding pixel values are the same, so that only one sub-pixel in each pixel in the pixel block a to be read can be read. As shown in fig. 3, only sub-pixel 0 within each pixel in the pixel block a to be read is read.

As shown in fig. 4, the pixel block B to be read is an effective pixel block, and the edge identifier corresponding to the pixel block B to be read is an effective edge identifier 0, so that it can be determined that the pixel block B to be read is an effective pixel block and is located at an image edge, as shown in fig. 4, the pixel point 0, the pixel point 2 and the pixel point 3 are all edge pixel points, and the pixel point 1 is a non-edge pixel point. Since the pixel sources of the edge pixel points are different, for example, in an image rasterization scene, different sub-pixel points in one edge pixel point may be derived from different primitive triangles, so that the pixel sources of each sub-pixel point (sub-pixel point 0 to sub-pixel point n) in the edge pixel points (pixel point 0, pixel point 2 and pixel point 3) in the pixel block B to be read are different, in order to ensure the complete validity of data, n+1 sub-pixel points in each pixel point in the pixel block B to be read need to be sequentially read as shown in fig. 4.

As shown in fig. 5, the pixel block C to be read is an invalid pixel block, that is, all pixel points in the pixel block C to be read have no valid writing into the target memory, and at this time, it is unnecessary to consider what the edge identifier corresponding to the pixel block C to be read is, and it is unnecessary to read the pixel block C to be read.

In a possible implementation manner, in a case that the writing identifier corresponding to the pixel block to be read includes both a valid writing identifier and an invalid writing identifier, the method further includes: and replacing the pixel value of the sub-pixel point in the pixel point corresponding to the invalid writing mark in the read pixel block to be read with a preset background pixel value.

After the pixel block to be processed is read, if the writing identification corresponding to the pixel block to be read includes both the valid writing identification and the invalid writing identification, the pixel value of the pixel point corresponding to the invalid writing identification is not the pixel value in the valid writing target memory and may be uninitialized messy invalid data, so that the pixel value of the sub-pixel point in the pixel point corresponding to the invalid writing identification in the read pixel block to be read is replaced by the preset background pixel value in order to avoid uncontrollable and unexpected images and to effectively perform subsequent image processing. The specific value of the preset background pixel value can be flexibly set according to the actual image condition, which is not particularly limited in the disclosure.

As shown in fig. 3, the pixel point 0, the pixel point 1 and the pixel point 2 in the pixel block a to be read are corresponding to the invalid writing identifier 1, and at this time, the pixel values of the sub-pixel point 0 in the pixel point 0, the pixel point 1 and the pixel point 2 in the pixel block a to be read are respectively replaced with the preset background pixel value BGV.

As shown in fig. 4, the pixel point 1 in the pixel block B to be read corresponds to the invalid writing identifier 1, and at this time, the pixel values of the sub-pixel point 0 to the sub-pixel point n in the pixel point 1 in the pixel block B to be read are replaced with the preset background pixel value BGV.

The pixel points corresponding to the effective writing marks are written in the pixel blocks to be read, and the pixel points corresponding to the effective writing marks are pixel values in the image effective writing target memory, so that the sub-pixel points in the pixel points corresponding to the effective writing marks are written in the pixel blocks to be read, and pixel value replacement processing is not needed.

In the pixel data processing process in image processing, adjacent pixel blocks are usually requested together or are combined together for data transmission after processing, so if the pixel data of the adjacent pixel blocks can be written into a memory in parallel, the subsequent parallel reading is realized, the reading and writing speed of the pixel data is effectively accelerated, and the processing efficiency and the transmission efficiency of the image can be effectively improved.

The image processing method applied to the target memory under the multi-sampling scene can effectively realize parallel processing of a plurality of adjacent pixel blocks in the target image by using the target memory. The image processing method for multi-sampling provided by the present disclosure is described in detail below.

Fig. 6 shows a flowchart of an image processing method for multisampling according to an embodiment of the present disclosure. The method may be performed by an electronic device, such as a terminal device or a server, the terminal device may be a User Equipment (UE), a mobile device, a User terminal, a cellular phone, a cordless phone, a personal digital assistant (Personal Digital Assistant, PDA), a handheld device, a computing device, a vehicle mounted device, a wearable device, etc., and the method may be implemented by a processor invoking computer readable instructions stored in a memory. Alternatively, the method may be performed by a server. The method is applied to image processing by utilizing a target memory, wherein the target memory is divided into N pixel storage groups, and N is a positive integer greater than or equal to 2. As shown in fig. 6, the method includes:

In step S61, a data parallel write request is received, wherein the data parallel write request is for requesting 2 in the target image ^m Writing the pixel blocks into a target memory in parallel, wherein 2 ^m Is a positive integer of 2 or more and N or less.

The target image includes a plurality of pixel points, and the data amount of the pixel data of each pixel point can be flexibly set according to the actual situation, which is not particularly limited in the present disclosure. In order to improve the image processing efficiency, image processing is performed on a pixel block unit composed of a plurality of pixel points in a target image. The number of pixel points included in one pixel block may be flexibly set according to practical situations, which is not particularly limited in the present disclosure.

To further improve image processing efficiency, a single-pass best in the target memory is utilizedThe number of pixel blocks processed in large parallel is typically greater than 1, i.e. a plurality of pixel blocks are processed in parallel. Thus, to achieve parallel processing of 2 in a target image with target memory ^m A block of pixels, first, based on a data parallel write request, for requesting 2 in the target image ^m And writing the pixel blocks into the target memory in parallel. According to the difference of m values, 2, 4, 8, 16 and other pixel blocks in the target image can be written into the target memory in parallel, and the details are not repeated here.

The sending of the data parallel writing request may be a pixel generating module, where the pixel generating module is configured to write a plurality of pixel blocks in the target image into the target memory in parallel. The pixel generating module may be a hardware module or a software program, which is not specifically limited in this disclosure.

The number of N pixel storage groups in the target memory needs to meet the number of pixel blocks processed in a single maximum parallel. For example, when the number of pixel blocks processed in a single maximum parallel is 2, the target memory is divided into at least n=2 pixel storage groups.

Considering the parallelization expansion performance of the system, the number of N pixel storage groups divided into by the target memory can be larger than the number of the current single maximum parallel processing pixel blocks. For example, when the number of the current single maximum parallel processing pixel blocks is 2, the target memory is divided into at least n=4 pixel storage groups, so as to provide support for expanding the number of the single maximum parallel processing pixel blocks to 4. Fig. 7 is a schematic diagram of a structure of a target memory according to an embodiment of the disclosure. As shown in fig. 7, the target memory is divided into n=4 pixel storage groups: group 0 to group 3.

In step S62, it is determined that 2 ^m A pixel storage group identifier corresponding to each pixel block in the pixel blocks, wherein 2 ^m Adjacent ones of the pixel blocks correspond to different pixel storage group identifications.

Considering that there is an operation process on adjacent pixel data in the target image during the image processing or there is a packed transmission of a plurality of adjacent pixel data together after the process is finished to reduce the interactive interface, 2 ^m Individual pixelsAdjacent pixel blocks in the block are written into different pixel storage groups in the target memory, so that parallel processing of the adjacent pixel blocks by using the target memory is realized.

In one example, in the case where the target memory is a linear memory storage arrangement, determine 2 ^m The pixel storage group identifier corresponding to each pixel block in the pixel blocks comprises: at 2 ^m Each pixel block is 2 adjacent to the horizontal direction in the target image ^m Determining 2 when each pixel block is ^m The pixel blocks respectively correspond to different pixel storage group identifiers; or, at 2 ^m Each pixel block is 2 longitudinally adjacent in the target image ^m Determining 2 when each pixel block is ^m The pixel blocks respectively correspond to different pixel storage group identifications.

Under the condition that the target memory is in linear memory storage arrangement, pixel blocks in the target image are written into the target memory row by row and column by column for storage, so as to ensure 2 in the target image ^m The adjacent pixel blocks can be processed in parallel to enable 2 adjacent to each other in the transverse direction in the target image ^m Writing the pixel blocks into different pixel storage groups; and/or, 2 longitudinally adjacent in the target image ^m The blocks of pixels are written to different pixel storage groups.

In one example, in the case where the target memory is a Z-type memory storage arrangement, determine 2 ^m The pixel storage group identifier corresponding to each pixel block in the pixel blocks comprises: at 2 ^m When each pixel block comprises at least one 2×2 structure in the target image, determining that 4 pixel blocks in each 2×2 structure respectively correspond to different pixel storage group identifications.

Under the condition that the target memory is in Z-type memory storage arrangement, writing pixel blocks in the target image into the target memory for storage according to a 2X 2 structure, so as to ensure 2 in the target image ^m The adjacent pixel blocks can be processed in parallel, and 4 pixel blocks in each 2×2 structure in the target image are respectively written into different pixel storage groups.

In step S63, according to 2 ^m Storing group identifiers corresponding to each pixel block in the pixel blocks, and adding 2 ^m Writing the blocks of pixels in parallel to the target memory and determining 2 ^m And writing identification and edge identification corresponding to each pixel block in the pixel blocks.

In accordance with 2 ^m Storing group identifiers corresponding to each pixel block in the pixel blocks, and adding 2 ^m After each pixel block is written into the target memory in parallel, determining a writing identification corresponding to each pixel block according to the writing condition of each pixel block, and determining an edge identification corresponding to each pixel block according to whether each pixel block is at an image edge or not so as to prepare for a subsequent pixel block reading process. The details of how to determine the writing identifier and the edge identifier corresponding to each pixel block will be described in detail in connection with possible implementations of the present disclosure, which are not described herein.

In the embodiment of the disclosure, the target memory is divided into different pixel storage groups, adjacent pixel blocks in the target image are written into the different pixel storage groups in parallel, and the writing identification and the edge corresponding to each pixel block are determined, so that effective parallel reading of a plurality of adjacent pixel blocks in the target image by using the writing identification and repeated reading of a plurality of sub-pixel points with the same pixel value in a multi-sampling scene by using the edge identification can be realized, load power consumption caused by invalid data reading is reduced, and the data reading efficiency in the image processing process in the multi-sampling scene is effectively improved.

In one possible implementation, each pixel storage group includes M pixel storage rows, where M is a positive integer greater than or equal to 2, and the target memory includes an identification storage unit with a size of mxn; determination 2 ^m The writing identification corresponding to each pixel block in the pixel blocks comprises the following steps: for 2 ^m And determining a writing identifier in the ith column and the jth row in the identifier storage unit according to whether each pixel point in the pixel block is successfully written into the jth pixel storage row in the ith pixel storage group or not by any pixel block in the pixel blocks, wherein the writing identifier in the ith column and the jth row comprises the writing identifier corresponding to each pixel point in the pixel block.

In the target memory, each pixel storage group includes M pixel storage rows, one for storing one pixel block. And the target memory also comprises an identification storage unit with the size of M multiplied by N, which is used for storing the writing identification corresponding to the pixel block written into any pixel storage line in any pixel storage group. As shown in fig. 7, each pixel storage group includes 64 pixel storage lines, and the target memory includes an identification storage unit of 64×4 size.

A writing flag in the ith column and jth row in the flag storage unit indicates whether the jth pixel storage row in the ith pixel storage group is successfully written into the pixel block. That is, for any one pixel block, when the pixel block needs to be written into the jth pixel storage row in the ith pixel storage group, determining a writing identifier in the ith column and the jth row in the identifier storage unit according to whether each pixel point in the pixel block is successfully written into the jth pixel storage row in the ith pixel storage group, wherein the writing identifier in the ith column and the jth row comprises a writing identifier corresponding to each pixel point in the pixel block.

In one possible implementation, for 2 ^m Any one pixel block in the pixel blocks determines a writing identification in the ith column and the jth row in the identification storage unit according to whether each pixel point in the pixel block is successfully written into the jth pixel storage row in the ith pixel storage group, and the writing identification comprises the following steps: for any pixel point in the pixel block, determining a writing identifier corresponding to the pixel point as an effective writing identifier under the condition that the pixel point is successfully written into a jth pixel storage row in an ith pixel storage group; or determining the writing identification corresponding to the pixel point as an invalid writing identification under the condition that the pixel point is not successfully written into the j-th pixel storage row in the i-th pixel storage group.

For any one pixel block, when the pixel block needs to be written into the j-th pixel storage row in the i-th pixel storage group, that is, each pixel point in the pixel block needs to be written into the j-th pixel storage row in the i-th pixel storage group. For any pixel point in the pixel block, determining a writing mark corresponding to the pixel point as an effective writing mark 0 under the condition that the pixel point is successfully written into a jth pixel storage row in an ith pixel storage group; or, in the case that the pixel point is not successfully written into the j-th pixel storage row in the i-th pixel storage group, determining the writing identifier corresponding to the pixel point as an invalid writing identifier 1.

In one example, the default write identifications may be invalid write identification 1 when initialized in the identification storage unit. For any pixel point in the pixel block, under the condition that the pixel point is successfully written into the jth pixel storage row in the ith pixel storage group, updating the writing identification corresponding to the pixel point in the jth pixel storage row in the ith pixel storage group from the invalid writing identification 1 to the valid writing identification 0; or, in the case that the pixel point is not successfully written into the jth pixel storage row in the ith pixel storage group, keeping the writing identifier corresponding to the pixel point in the jth pixel storage row in the ith pixel storage group as the invalid writing identifier 1.

In one possible implementation, each pixel includes a plurality of sub-pixels; determination 2 ^m The edge identifier corresponding to each pixel block in the pixel blocks comprises: determining an edge identifier in the j-th row of the ith column in the identification storage unit as a valid edge identifier for writing into a pixel block in the j-th pixel storage row in the ith pixel storage group under the condition that at least one edge pixel point exists in the pixel block, wherein the valid edge identifier is used for indicating that the pixel block is at an image edge; or, in the case that all the pixel points in the pixel block are non-edge pixel points, determining that the edge mark in the ith column and the jth row in the mark storage unit is an invalid edge mark, wherein the invalid edge mark is used for indicating that the pixel block is not at the image edge.

For a pixel block written into a jth pixel storage row in the ith pixel storage group, determining that an edge identifier corresponding to the pixel block in the jth pixel storage row in the ith pixel storage group is a valid edge identifier 0 as long as at least one edge pixel point exists in the pixel block. Only if all the pixel points in the pixel block are non-edge pixel points, determining that the edge mark corresponding to the pixel block in the jth pixel storage row in the ith pixel storage group is invalid edge mark 1.

In one example, the default edge identifications may be invalid edge identification 1 when initialized in the identification storage unit. For a pixel block written into a j-th pixel storage row in the i-th pixel storage group, updating an edge identifier corresponding to the pixel block in the j-th pixel storage row in the i-th pixel storage group from an invalid edge identifier 1 to a valid edge identifier 0 under the condition that at least one edge pixel point exists in the pixel block; or, if all the pixel points in the pixel block are non-edge pixel points, maintaining the edge mark corresponding to the pixel block in the jth pixel storage row in the ith pixel storage group as invalid edge mark 1.

As shown in fig. 3, all of the pixel points 0 to 3 in the pixel block a to be read are non-edge pixel points, and therefore, the edge identifier corresponding to the pixel block a to be read is an invalid edge identifier 1.

As shown in fig. 4, pixel point 0, pixel point 2, and pixel point 3 in the pixel block B to be read are edge pixel points, and therefore, the edge identifier corresponding to the pixel block B to be read is valid edge identifier 0.

In an example, the process of writing the pixel point a (including the sub-pixel point 0 to the sub-pixel point 3) into the target memory by the pixel generation module may be as follows: and sending a data writing request to the target memory, wherein the data writing request is used for requesting to write the sub-pixels 0-3 in the pixel point a into the target memory, and the sub-pixels 0-3 correspond to the first pixel source. And writing the pixel point a into the target memory through one-time writing, wherein the pixel sources of the sub-pixel points in the pixel point a are the same, so that the pixel point a can be determined to be a non-edge pixel point. Wherein the pixel values of the sub-pixel points of the same pixel source are the same.

In an example, the process of writing the pixel point b (including the sub-pixel point 0 to the sub-pixel point 3) into the target memory by the pixel generation module may be as follows: a first data writing request is sent to a target memory, wherein the first data writing request is used for requesting to write a sub-pixel 0 and a sub-pixel 1 in a pixel point b into the target memory, and the sub-pixel 0 and the sub-pixel 1 correspond to a first pixel source; sending a second data writing request to the target memory, wherein the second data writing request is used for requesting to write the sub-pixel 2 and the sub-pixel 3 in the pixel point b into the target memory, and the sub-pixel 2 and the sub-pixel 3 correspond to a second pixel source; the first pixel source and the second pixel source are different, e.g., in an image rasterized scene, the first pixel source and the second pixel source are from different primitive triangles. And writing the pixel point b into the target memory through secondary writing, and determining the pixel point b as an edge pixel point because the pixel sources of the sub-pixel points in the pixel point b are different. The pixel values of the sub-pixel points of different pixel sources may be the same or different, which is not specifically limited in the present disclosure.

In an example, the process of writing the pixel point c (including the sub-pixel point 0 to the sub-pixel point 3) into the target memory by the pixel generation module may be as follows: and sending a data writing request to the target memory, wherein the data writing request is used for requesting to write the sub-pixel 0 and the sub-pixel 3 in the pixel point c into the target memory, and the sub-pixel 0 and the sub-pixel 3 correspond to the first pixel source. After writing part of the sub-pixel points in the pixel point c into the target memory through one writing, the writing process is ended, and as the pixel sources of the sub-pixel points in the pixel point c are different, namely, although the sub-pixel point 1 and the sub-pixel point 2 are not written, the pixel sources of the sub-pixel point 1, the sub-pixel point 2, the sub-pixel point 0 and the sub-pixel point 3 corresponding to different pixels can still be determined, for example, in an image rasterization scene, the sub-pixel point 1, the sub-pixel point 2, the sub-pixel point 0 and the sub-pixel point 3 come from different primitive triangles, so that the pixel point c can be determined to be an edge pixel point.

The manner of writing the pixel points in the pixel block into the target memory may be other manners besides the foregoing embodiments, and this disclosure is not limited specifically.

And storing the writing identification corresponding to each pixel point in one pixel block and the edge identification corresponding to the pixel block together by using an identification storage unit with the size of M multiplied by N, so that the writing identification corresponding to each pixel point in one pixel block and the edge identification corresponding to the pixel block can be read in parallel subsequently, and the data reading efficiency is improved.

And storing the writing identifications and the edge identifications corresponding to the N pixel blocks in the same pixel storage line in the 4 groups in the same line of the identification storage unit by using the identification storage unit with the M multiplied by N size, so that the writing identifications and the edge identifications corresponding to the N pixel blocks can be read in parallel subsequently, and the data reading efficiency is improved.

Fig. 8 shows a flowchart of an image processing method for multisampling according to an embodiment of the present disclosure. The method may be performed by an electronic device, such as a terminal device or a server, the terminal device may be a User Equipment (UE), a mobile device, a User terminal, a cellular phone, a cordless phone, a personal digital assistant (Personal Digital Assistant, PDA), a handheld device, a computing device, a vehicle mounted device, a wearable device, etc., and the method may be implemented by a processor invoking computer readable instructions stored in a memory. Alternatively, the method may be performed by a server. As shown in fig. 8, the method includes:

in step S81, a first data parallel read request is sent to the target memory, where the first data parallel read request is used to request parallel reading of 2 stored in the target memory ^m Writing identification and edge identification corresponding to pixel blocks to be read, wherein the target memory is divided into N pixel storage groups, 2 ^m The pixel blocks to be read are stored in different pixel storage groups, N is a positive integer greater than or equal to 2, 2 ^m Is a positive integer of 2 or more and N or less.

The storage manner of each pixel block in the target image in the target memory may refer to the related description of the above embodiment, which is not described herein.

Based on the storage mode of the target memory, 2 of the storage groups stored in different pixels in the target memory can be processed ^m And the pixel blocks to be read are read in parallel. In order to reduce redundant data interactions, in pair 2 ^m Before parallel reading is carried out on pixel blocks to be read, the pixel blocks to be read are sent to a target memory to request parallel reading 2 ^m And the first data parallel reading requests of the writing identification and the edge identification corresponding to the pixel blocks to be read.

In step S82, for 2 ^m In the pixel blocks to be readAccording to the writing identification corresponding to the pixel block to be read returned by the target memory, judging whether the pixel block to be read is an effective pixel block or not, and according to the edge identification corresponding to the pixel block to be read returned by the target memory, judging whether the pixel block to be read is at the image edge or not.

Read to 2 from target memory ^m After the writing marks and the edge marks corresponding to the pixel blocks to be read, aiming at 2 ^m Any one of the pixel blocks to be read can judge whether the pixel block to be read is an effective pixel block or not according to the writing identification corresponding to the pixel block to be read, namely whether the pixel block to be read is effectively written into the target memory or not; and judging whether the pixel block to be read is positioned at the image edge or not according to the edge identification corresponding to the pixel block to be read.

For any pixel block to be read, a specific process of how to determine whether the pixel block to be read is an effective pixel block according to the writing identifier corresponding to the pixel block to be read and how to determine whether the pixel block to be read is at an image edge according to the edge identifier corresponding to the pixel block to be read may be referred to the related description of the above embodiments, which is not repeated herein.

In step S83, a second data parallel read request is sent to the target memory, where the second data parallel read request is used to request pair 2 ^m And in the effective pixel blocks to be read, all the sub-pixel points in each pixel point in the effective pixel blocks to be read which are not positioned at the image edge are read in parallel.

After making the above determination, a request for pair 2 may be sent to the target memory ^m And the second data parallel reading request is that all the sub-pixel points in each pixel point in the effective pixel block to be read which is positioned at the image edge are read in parallel. At this time, only 2 is read ^m Effective pixel blocks included in each pixel block to be read without being paired with non-effective pixel blocksAnd the effective pixel block is read, only one sub-pixel point in each pixel point in the effective pixel block which is not positioned at the image edge is read, repeated reading of a plurality of sub-pixel points with the same pixel value is not needed, data redundancy interaction caused by reading of repeated sub-pixel data in an invalid pixel block and a multi-sampling scene is reduced, and data reading efficiency is improved.

In step S84, a target memory return 2 is received ^m In the effective pixel block to be read, one sub-pixel point in each pixel point in the effective pixel block to be read which is not positioned at the image edge, and all sub-pixel points in each pixel point in the effective pixel block to be read which is positioned at the image edge.

Parallel reading 2 from the target memory based on the second data parallel read request ^m One sub-pixel point in each pixel point in the effective pixel block to be read which is not positioned at the image edge in the pixel block to be read, and all sub-pixel points in each pixel point in the effective pixel block to be read which is positioned at the image edge.

According to an embodiment of the present disclosure, 2 stored in the target memory is based on ^m Writing identification and edge identification corresponding to each pixel block can realize that only 2 is read in parallel ^m The effective pixel blocks included in the pixel blocks are not read, only one sub-pixel point in each pixel point in the effective pixel blocks which are not positioned at the image edge is read, repeated reading of a plurality of sub-pixel points with the same pixel value in a multi-sampling scene is not needed, data redundancy interaction caused by reading of the ineffective pixel blocks and repeated sub-pixel data is reduced, and data reading efficiency is improved.

The sending of the first data parallel reading request and the second data parallel reading request may be a pixel processing module, where the pixel processing module is configured to perform a subsequent image processing operation on the plurality of pixel blocks to be read that are read in parallel. The pixel processing module may be a hardware module or a software program, which is not specifically limited in this disclosure.

In a possible implementation manner, for any one of the read pixel blocks to be read, when the writing identifier corresponding to the pixel block to be read includes both an effective writing identifier and an ineffective writing identifier, the pixel value of the sub-pixel point in the pixel point corresponding to the ineffective writing identifier in the read pixel block to be read is replaced with a preset background pixel value, and the specific process may refer to the related description of the above embodiment and is not repeated herein.

It will be appreciated that the above-mentioned method embodiments of the present disclosure may be combined with each other to form a combined embodiment without departing from the principle logic, and are limited to the description of the present disclosure. It will be appreciated by those skilled in the art that in the above-described methods of the embodiments, the particular order of execution of the steps should be determined by their function and possible inherent logic.

In addition, the disclosure further provides an image processing apparatus, an electronic device, a computer readable storage medium, and a program for multiple sampling, where any of the foregoing may be used to implement any of the image processing methods for multiple sampling provided in the disclosure, and corresponding technical schemes and descriptions and corresponding descriptions referring to method parts are not repeated.

Fig. 9 shows a block diagram of an image processing apparatus for multiple sampling according to an embodiment of the present disclosure. As shown in fig. 9, the apparatus 90 includes:

the identifier reading module 91 is configured to send a first data reading request to the target memory, where the first data reading request is used to request to read a write identifier and an edge identifier corresponding to a pixel block to be read stored in the target memory, where each pixel point in the pixel block to be read includes multiple sub-pixel points;

the judging module 92 is configured to judge whether the pixel block to be read is an effective pixel block according to a write-in identifier corresponding to the pixel block to be read returned by the target memory, and judge whether the pixel block to be read is at an image edge according to an edge identifier corresponding to the pixel block to be read returned by the target memory;

a pixel reading module 93, configured to send a second data reading request to the target memory when it is determined that the pixel block to be read is an effective pixel block and is not at an image edge, where the second data reading request is used to request to read one sub-pixel point in each pixel point in the pixel block to be read;

the receiving module 94 is configured to receive a sub-pixel point in each pixel point in the pixel block to be read returned by the target memory.

In a possible implementation manner, the pixel reading module 93 is configured to send a third data reading request to the target memory when it is determined that the pixel block to be read is a valid pixel block and is at an image edge, where the third data reading request is used to request to read all sub-pixel points in each pixel point in the pixel block to be read;

the receiving module 94 is configured to receive all sub-pixel points in each pixel point in the pixel block to be read returned by the target memory.

In one possible implementation manner, the writing identifier corresponding to the pixel block to be read includes a writing identifier corresponding to each pixel point in the pixel block to be read;

a judging module 92, configured to:

under the condition that at least one effective writing identifier exists in the writing identifiers corresponding to the pixel blocks to be read, determining the pixel blocks to be read as effective pixel blocks, wherein the pixel points corresponding to the effective writing identifiers are effective pixel data in the pixel blocks to be read; or alternatively, the first and second heat exchangers may be,

and under the condition that the writing identification corresponding to each pixel point in the writing identifications corresponding to the pixel blocks to be read is an invalid writing identification, determining that the pixel blocks to be read are not valid pixel blocks.

In one possible implementation, the apparatus 90 further includes:

And the optimizing module is used for replacing the pixel value of the sub-pixel point in the pixel point corresponding to the invalid writing mark in the read pixel block to be read with the preset background pixel value under the condition that the writing mark corresponding to the pixel block to be read comprises the valid writing mark and the invalid writing mark.

Fig. 10 shows a block diagram of an image processing apparatus for multiple sampling according to an embodiment of the present disclosure. The device is applied to a target memory, and the target memory is divided into N pixel storage groups, wherein N is a positive integer greater than or equal to 2. As shown in fig. 10, the apparatus 100 includes:

a pixel writing module 101 for receiving a data parallel writing request for requesting 2 in the target image ^m Writing the pixel blocks into a target memory in parallel, wherein 2 ^m Is a positive integer of 2 or more and N or less;

a storage packet selection module 102 for determining 2 ^m A pixel storage group identifier corresponding to each pixel block in the pixel blocks, wherein 2 ^m Adjacent pixel blocks in the pixel blocks correspond to different pixel storage group identifications;

an identification generation module 103 for generating identification according to 2 ^m Storing group identifiers corresponding to each pixel block in the pixel blocks, and adding 2 ^m Writing the blocks of pixels in parallel to the target memory and determining 2 ^m And writing identification and edge identification corresponding to each pixel block in the pixel blocks.

In one possible implementation, each pixel storage group includes M pixel storage rows, where M is a positive integer greater than or equal to 2, and the target memory includes an identification storage unit with a size of mxn;

an identification generation module 103 for:

for 2 ^m And determining a writing identifier in the ith column and the jth row in the identifier storage unit according to whether each pixel point in the pixel block is successfully written into the jth pixel storage row in the ith pixel storage group or not by any pixel block in the pixel blocks, wherein the writing identifier in the ith column and the jth row comprises the writing identifier corresponding to each pixel point in the pixel block.

In one possible implementation, the identifier generation module 103 is configured to:

for any pixel point in the pixel block, determining a writing identifier corresponding to the pixel point as an effective writing identifier under the condition that the pixel point is successfully written into a jth pixel storage row in an ith pixel storage group; or alternatively, the first and second heat exchangers may be,

and under the condition that the pixel point is not successfully written into the j-th pixel storage row in the i-th pixel storage group, determining the writing identification corresponding to the pixel point as an invalid writing identification.

In one possible implementation, each pixel includes a plurality of sub-pixels;

an identification generation module 103 for:

determining an edge identifier in the j-th row of the ith column in the identification storage unit as a valid edge identifier for writing into a pixel block in the j-th pixel storage row in the ith pixel storage group under the condition that at least one edge pixel point exists in the pixel block, wherein the valid edge identifier is used for indicating that the pixel block is at an image edge; or alternatively, the first and second heat exchangers may be,

and determining an edge mark in the ith column and the jth row in the mark storage unit as an invalid edge mark under the condition that all pixel points in the pixel block are non-edge pixel points, wherein the invalid edge mark is used for indicating that the pixel block is not at the image edge.

Fig. 11 shows a block diagram of an image processing apparatus for multiple sampling according to an embodiment of the present disclosure. As shown in fig. 11, the apparatus 110 includes:

an identifier reading module 111, configured to send a first data parallel reading request to the target memory, where the first data parallel reading request is used to request to read 2 stored in the target memory in parallel ^m Writing identification and edge identification corresponding to pixel blocks to be read, wherein the target memory is divided into N pixel storage groups, 2 ^m The pixel blocks to be read are stored in different pixel storage groups, N is a positive integer greater than or equal to 2, 2 ^m Is a positive integer of 2 or more and N or less;

a judging module 112 for aiming at 2 ^m Any one of the pixel blocks to be read is judged according to the writing identification corresponding to the pixel block to be read returned by the target memory, whether the pixel block to be read is an effective pixel block is judged, and whether the pixel block to be read is positioned at the image edge is judged according to the edge identification corresponding to the pixel block to be read returned by the target memory;

a pixel read module 113 for sending a second data parallel read request to the target memory, wherein the second data parallel read request is for requesting pair 2 ^m In the pixel blocks to be read, the pixel blocks are not in the pictureOne sub-pixel point in each pixel point in the effective pixel block to be read of the image edge and all sub-pixel points in each pixel point in the effective pixel block to be read of the image edge are read in parallel;

a receiving module 114 for receiving the returned 2 of the target memory ^m In the effective pixel block to be read, one sub-pixel point in each pixel point in the effective pixel block to be read which is not positioned at the image edge, and all sub-pixel points in each pixel point in the effective pixel block to be read which is positioned at the image edge.

The method has specific technical association with the internal structure of the computer system, and can solve the technical problems of improving the hardware operation efficiency or the execution effect (including reducing the data storage amount, reducing the data transmission amount, improving the hardware processing speed and the like), thereby obtaining the technical effect of improving the internal performance of the computer system which accords with the natural law.

In some embodiments, functions or modules included in an apparatus provided by the embodiments of the present disclosure may be used to perform a method described in the foregoing method embodiments, and specific implementations thereof may refer to descriptions of the foregoing method embodiments, which are not repeated herein for brevity.

The disclosed embodiments also provide a computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the above-described method. The computer readable storage medium may be a volatile or nonvolatile computer readable storage medium.

The embodiment of the disclosure also provides an electronic device, which comprises: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to invoke the instructions stored in the memory to perform the above method.

Embodiments of the present disclosure also provide a computer program product comprising computer readable code, or a non-transitory computer readable storage medium carrying computer readable code, which when run in a processor of an electronic device, performs the above method.

The electronic device may be provided as a terminal, server or other form of device.

Fig. 12 shows a block diagram of an electronic device, according to an embodiment of the disclosure. Referring to fig. 12, an electronic device 1900 may be provided as a server or terminal device. Referring to fig. 12, electronic device 1900 includes a processing component 1922 that further includes one or more processors and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by processing component 1922. The application programs stored in memory 1932 may include one or more modules each corresponding to a set of instructions. Further, processing component 1922 is configured to execute instructions to perform the methods described above.

The electronic device 1900 may also include a power component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input/output interface 1958. Electronic device 1900 may operate an operating system based on memory 1932, such as the Microsoft Server operating system (Windows Server) ^TM ) Apple Inc. developed graphical user interface based operating System (Mac OS X ^TM ) Multi-user multi-process computer operating system (Unix) ^TM ) Unix-like operating system (Linux) of free and open source code ^TM ) Unix-like operating system (FreeBSD) with open source code ^TM ) Or the like.

In an exemplary embodiment, a non-transitory computer readable storage medium is also provided, such as memory 1932, including computer program instructions executable by processing component 1922 of electronic device 1900 to perform the methods described above.

The present disclosure may be a system, method, and/or computer program product. The computer program product may include a computer readable storage medium having computer readable program instructions embodied thereon for causing a processor to implement aspects of the present disclosure.

The computer readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: portable computer disks, hard disks, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static Random Access Memory (SRAM), portable compact disk read-only memory (CD-ROM), digital Versatile Disks (DVD), memory sticks, floppy disks, mechanical coding devices, punch cards or in-groove structures such as punch cards or grooves having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media, as used herein, are not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses through fiber optic cables), or electrical signals transmitted through wires.

The computer readable program instructions described herein may be downloaded from a computer readable storage medium to a respective computing/processing device or to an external computer or external storage device over a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers and/or edge servers. The network interface card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium in the respective computing/processing device.

Computer program instructions for performing the operations of the present disclosure can be assembly instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, c++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, aspects of the present disclosure are implemented by personalizing electronic circuitry, such as programmable logic circuitry, field Programmable Gate Arrays (FPGAs), or Programmable Logic Arrays (PLAs), with state information of computer readable program instructions, which can execute the computer readable program instructions.

Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable medium having the instructions stored therein includes an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The computer program product may be realized in particular by means of hardware, software or a combination thereof. In an alternative embodiment, the computer program product is embodied as a computer storage medium, and in another alternative embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK), or the like.

The foregoing description of various embodiments is intended to highlight differences between the various embodiments, which may be the same or similar to each other by reference, and is not repeated herein for the sake of brevity.

It will be appreciated by those skilled in the art that in the above-described method of the specific embodiments, the written order of steps is not meant to imply a strict order of execution but rather should be construed according to the function and possibly inherent logic of the steps.

If the technical scheme of the application relates to personal information, the product applying the technical scheme of the application clearly informs the personal information processing rule before processing the personal information, and obtains independent consent of the individual. If the technical scheme of the application relates to sensitive personal information, the product applying the technical scheme of the application obtains individual consent before processing the sensitive personal information, and simultaneously meets the requirement of 'explicit consent'. For example, a clear and remarkable mark is set at a personal information acquisition device such as a camera to inform that the personal information acquisition range is entered, personal information is acquired, and if the personal voluntarily enters the acquisition range, the personal information is considered as consent to be acquired; or on the device for processing the personal information, under the condition that obvious identification/information is utilized to inform the personal information processing rule, personal authorization is obtained by popup information or a person is requested to upload personal information and the like; the personal information processing rule may include information such as a personal information processor, a personal information processing purpose, a processing mode, and a type of personal information to be processed.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. An image processing method for multiple sampling, comprising:

a first data reading request is sent to a target memory, wherein the first data reading request is used for requesting to read a writing identifier and an edge identifier corresponding to a pixel block to be read stored in the target memory, and each pixel point in the pixel block to be read comprises a plurality of sub-pixel points;

judging whether the pixel block to be read is an effective pixel block according to the writing identification corresponding to the pixel block to be read returned by the target memory, and judging whether the pixel block to be read is at the image edge according to the edge identification corresponding to the pixel block to be read returned by the target memory;

Sending a second data reading request to the target memory under the condition that the pixel block to be read is an effective pixel block and is not at the image edge, wherein the second data reading request is used for requesting to read one sub-pixel point in each pixel point in the pixel block to be read;

and receiving one sub-pixel point in each pixel point in the pixel block to be read returned by the target memory.

2. The method according to claim 1, wherein the method further comprises:

transmitting a third data reading request to the target memory under the condition that the pixel block to be read is an effective pixel block and is positioned at the image edge, wherein the third data reading request is used for requesting to read all sub-pixel points in each pixel point in the pixel block to be read;

and receiving all sub-pixel points in each pixel point in the pixel block to be read returned by the target memory.

3. The method according to claim 1 or 2, wherein the write-in identifier corresponding to the pixel block to be read includes a write-in identifier corresponding to each pixel point in the pixel block to be read;

the step of judging whether the pixel block to be read is an effective pixel block according to the writing identification corresponding to the pixel block to be read returned by the target memory, includes:

Determining the pixel block to be read as an effective pixel block under the condition that at least one effective writing identifier exists in the writing identifiers corresponding to the pixel block to be read, wherein the pixel point corresponding to the effective writing identifier is effective pixel data in the pixel block to be read; or alternatively, the first and second heat exchangers may be,

and determining that the pixel block to be read is not an effective pixel block under the condition that the writing identification corresponding to each pixel point in the writing identification corresponding to the pixel block to be read is an invalid writing identification.

4. A method according to claim 3, wherein in case that the write identifier corresponding to the pixel block to be read includes both a valid write identifier and an invalid write identifier, the method further includes:

and replacing the pixel value of the sub-pixel point in the pixel point corresponding to the invalid writing mark in the read pixel block to be read with a preset background pixel value.

5. An image processing method for multisampling, the method being applied to a target memory, the target memory being divided into N pixel storage groups, wherein N is a positive integer greater than or equal to 2, the method comprising:

receiving a data parallel write request, wherein the data parallel write request is used for requesting 2 in a target image ^m Writing the pixel blocks into the target memory in parallel, wherein 2 ^m Is a positive integer of 2 or more and N or less;

determining said 2 ^m A pixel storage group identifier corresponding to each pixel block in the pixel blocks, wherein the pixel storage group identifier is 2 ^m Adjacent pixel blocks in the pixel blocks correspond to different pixel storage group identifications;

according to said 2 ^m Storing group identifiers corresponding to each pixel block in the pixel blocks, and carrying out the process of 2 ^m Writing blocks of pixels in parallel to the target memory, and determining the 2 ^m And writing identification and edge identification corresponding to each pixel block in the pixel blocks.

6. The method of claim 5, wherein each pixel storage group comprises M pixel storage rows, wherein M is a positive integer greater than or equal to 2, and wherein the target memory comprises M x N size identification storage units;

said determining said 2 ^m The writing identification corresponding to each pixel block in the pixel blocks comprises the following steps:

for said 2 ^m And determining a writing identification in the ith column and the jth row in the identification storage unit according to whether each pixel point in the pixel block is successfully written into the jth pixel storage row in the ith pixel storage group or not by any pixel block in the pixel blocks, wherein the writing identification in the ith column and the jth row comprises the writing identification corresponding to each pixel point in the pixel block.

7. The method of claim 6, wherein the target is 2 ^m Any one pixel block in the pixel blocks, determining the writing identification in the ith column and the jth row in the identification storage unit according to whether each pixel point in the pixel block is successfully written into the jth pixel storage row in the ith pixel storage group, wherein the writing identification comprises the following steps:

for any pixel point in the pixel block, determining a writing identifier corresponding to the pixel point as an effective writing identifier when the pixel point is successfully written into the j-th pixel storage row in the i-th pixel storage group; or alternatively, the first and second heat exchangers may be,

and under the condition that the pixel point is not successfully written into the j-th pixel storage row in the i-th pixel storage group, determining a writing identification corresponding to the pixel point as an invalid writing identification.

8. The method of claim 7, wherein each pixel comprises a plurality of sub-pixels therein;

said determining said 2 ^m The edge identifier corresponding to each pixel block in the pixel blocks comprises:

for a pixel block written into the jth pixel storage row in the ith pixel storage group, determining an edge identifier in the ith column and the jth row in the identifier storage unit as a valid edge identifier in the case that at least one edge pixel point exists in the pixel block, wherein the valid edge identifier is used for indicating that the pixel block is at an image edge; or alternatively, the first and second heat exchangers may be,

And under the condition that all pixel points in the pixel block are non-edge pixel points, determining an edge mark in an ith column and a jth row in the mark storage unit as an invalid edge mark, wherein the invalid edge mark is used for indicating that the pixel block is not positioned at the edge of the image.

9. An image processing method for multiple sampling, comprising:

sending a first data parallel reading request to a target memory, wherein the first data parallel reading request is used for requesting to read 2 stored in the target memory in parallel ^m Writing identification and edge identification corresponding to pixel blocks to be read, wherein the target memory is divided into N pixel storage groups, and the target memory is divided into 2 pixel storage groups ^m The pixel blocks to be read are stored in different pixel storage groups, N is a positive integer greater than or equal to 2, 2 ^m Is a positive integer of 2 or more and N or less;

for said 2 ^m Any one of the pixel blocks to be read is judged whether to be an effective pixel block according to a writing identification corresponding to the pixel block to be read returned by the target memory, and whether the pixel block to be read is positioned at an image edge or not is judged according to an edge identification corresponding to the pixel block to be read returned by the target memory;

Sending a second data parallel read request to the target memory, wherein the second data parallel read request is used for requesting the data of the data storage device 2 ^m One sub-pixel point in each pixel point in the effective pixel block to be read which is not positioned at the image edge in the pixel blocks to be read, and one sub-pixel point in each pixel point in the effective pixel block to be read which is positioned at the image edgeAll sub-pixel points are read in parallel;

receiving the 2 returned by the target memory ^m In the effective pixel block to be read, one sub-pixel point in each pixel point in the effective pixel block to be read which is not positioned at the image edge, and all sub-pixel points in each pixel point in the effective pixel block to be read which is positioned at the image edge.

10. An image processing apparatus for multiple sampling, comprising:

the device comprises an identification reading module, a target memory, a storage module and a storage module, wherein the identification reading module is used for sending a first data reading request to the target memory, the first data reading request is used for requesting to read a writing identification and an edge identification corresponding to a pixel block to be read stored in the target memory, and each pixel point in the pixel block to be read comprises a plurality of sub-pixel points;

the judging module is used for judging whether the pixel block to be read is an effective pixel block according to the writing identification corresponding to the pixel block to be read returned by the target memory, and judging whether the pixel block to be read is at the image edge according to the edge identification corresponding to the pixel block to be read returned by the target memory;

The pixel reading module is used for sending a second data reading request to the target memory under the condition that the pixel block to be read is determined to be an effective pixel block and is not positioned at the image edge, wherein the second data reading request is used for requesting to read one sub-pixel point in each pixel point in the pixel block to be read;

and the receiving module is used for receiving one sub-pixel point in each pixel point in the pixel block to be read returned by the target memory.

11. An image processing apparatus for multisampling, the apparatus being applied to a target memory, the target memory being divided into N pixel storage groups, wherein N is a positive integer greater than or equal to 2, the apparatus comprising:

a pixel writing module for receiving data parallel writing requestSolving, wherein the data parallel write request is used for requesting 2 in the target image ^m Writing the pixel blocks into the target memory in parallel, wherein 2 ^m Is a positive integer of 2 or more and N or less;

a storage packet selection module for determining said 2 ^m A pixel storage group identifier corresponding to each pixel block in the pixel blocks, wherein the pixel storage group identifier is 2 ^m Adjacent pixel blocks in the pixel blocks correspond to different pixel storage group identifications;

An identification generation module for generating identification information according to the method 2 ^m Storing group identifiers corresponding to each pixel block in the pixel blocks, and carrying out the process of 2 ^m Writing blocks of pixels in parallel to the target memory, and determining the 2 ^m And writing identification and edge identification corresponding to each pixel block in the pixel blocks.

12. An image processing apparatus for multiple sampling, comprising:

an identifier reading module, configured to send a first data parallel reading request to a target memory, where the first data parallel reading request is used to request parallel reading of 2 stored in the target memory ^m Writing identification and edge identification corresponding to pixel blocks to be read, wherein the target memory is divided into N pixel storage groups, and the target memory is divided into 2 pixel storage groups ^m The pixel blocks to be read are stored in different pixel storage groups, N is a positive integer greater than or equal to 2, 2 ^m Is a positive integer of 2 or more and N or less;

a judging module for aiming at the 2 ^m Any one of the pixel blocks to be read is judged whether to be an effective pixel block according to a writing identification corresponding to the pixel block to be read returned by the target memory, and whether the pixel block to be read is positioned at an image edge or not is judged according to an edge identification corresponding to the pixel block to be read returned by the target memory;

A pixel reading module, configured to send a second data parallel reading request to the target memory, where the second data parallel reading request is used forOn request for said 2 ^m In the effective pixel blocks to be read, one sub-pixel point in each pixel point in the effective pixel blocks to be read which are not positioned at the image edge and all sub-pixel points in each pixel point in the effective pixel blocks to be read which are positioned at the image edge are read in parallel;

a receiving module, configured to receive the 2 returned by the target memory ^m In the effective pixel block to be read, one sub-pixel point in each pixel point in the effective pixel block to be read which is not positioned at the image edge, and all sub-pixel points in each pixel point in the effective pixel block to be read which is positioned at the image edge.

13. An electronic device, comprising:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to invoke the instructions stored in the memory to perform the method of any of claims 1 to 9.

14. A computer readable storage medium having stored thereon computer program instructions, which when executed by a processor, implement the method of any of claims 1 to 9.