CN116032846A - MAC IP core device supporting frame preemption, data frame transmitting method and receiving method supporting frame preemption - Google Patents
MAC IP core device supporting frame preemption, data frame transmitting method and receiving method supporting frame preemption Download PDFInfo
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Abstract
The invention relates to the unmanned field, in particular to a MAC IP core device supporting frame preemption, a data frame sending method and a data frame receiving method supporting frame preemption, wherein the device comprises the following steps: the first-level data receiving and transmitting module is used for forming a first mPcket frame; the second level data receiving and transmitting module is used for forming a second mPcket frame, and the priority of the first level data is higher than that of the second level data; the frame preemption verification module is used for carrying out preemption verification according to a sending strategy or a receiving strategy; the transmission control module is used for transmitting the first mPcket frame and the second mPcket frame to the PHY chip according to the transmission strategy determined by the frame preemption verification module; the receiving control module is used for receiving the mPcket data frames from the PHY chip, and finishing the classification and the recombination of the mPcket data frames according to the parameters and the receiving strategy of the mPcket data frames so as to determine that the mPcket data frames are stored in the first-level data receiving and transmitting module or the second-level data receiving and transmitting module, so that the data frames are read. By reducing the data delay, the data transmission efficiency is improved.
Description
Technical Field
The invention relates to the unmanned field, in particular to a MAC IP core device supporting frame preemption, a data frame sending method and a data frame receiving method supporting frame preemption.
Background
As is well known, the universal ethernet works in an unsynchronized manner, any device in the network can send data at any time, and therefore, the transmission time of the data is neither accurate nor definite; meanwhile, the transmission of large-scale data such as broadcast data or video can also cause delay and even paralysis of communication due to the increase of network load.
In the running process of the unmanned vehicle, the requirements on data transmission and processing are extremely high, when the data is transmitted, the MAC IP core adds control information to the data, and then the data and the control information are transmitted to the coordination layer in a specified format; when receiving data, the MAC IP core firstly checks whether the received data frame is wrong, if the data is correct, the control information is removed, the data with the control information removed is sent to the logic link control LLC layer, if the data is wrong, the data frame is directly discarded, the data receiving and the data sending are realized, the vehicles can timely send the received data and timely control the received data, and the safety of the unmanned vehicles is ensured.
However, there is still a delay in the large-scale data transmission process in the prior art, and thus the sensitivity of the unmanned vehicle is greatly reduced.
Disclosure of Invention
Therefore, the invention provides a MAC IP core device supporting frame preemption, a data frame sending method and a data frame receiving method supporting frame preemption, which can solve the problem of data delay in the prior art.
To achieve the above object, an aspect of the present invention provides a MAC IP core apparatus supporting frame preemption, the apparatus comprising:
the first-level data receiving and transmitting module is used for receiving or transmitting first-level data and performing bit width conversion to form a first mPcket frame;
the second level data receiving and transmitting module is used for receiving or transmitting second level data and performing bit width conversion to form a second mPcket frame, and the priority of the first level data is higher than that of the second level data;
the frame preemption verification module determines a sending strategy or a receiving strategy of the first mPcket frame and the second mPcket frame according to the functional data frame;
the transmission control module is used for transmitting the first mPcket frame and the second mPcket frame to the PHY chip according to the transmission strategy determined by the frame preemption verification module;
The receiving control module is used for receiving the mPcket data frames from the PHY chip, and finishing the classification and recombination of the mPcket data frames according to the parameters of the mPcket data frames and the receiving strategy so as to determine that the mPcket data frames are stored in the first-level data receiving and transmitting module or the second-level data receiving and transmitting module, so that the data frames are read.
Further, the first level data transceiver module includes:
a receiving channel control module and a first buffer module, wherein
The receiving channel control module is connected with the receiving control module and used for receiving the mPcket data frame stored in the first-level data receiving and transmitting module;
the first buffer module is connected with the receiving channel control module and used for buffering the mPcket data frame into the first buffer module.
Further, the first level data sending module further includes:
a sending channel control module, a second buffer module and a check data generation module, wherein,
the sending channel control module is used for receiving first data, and forming a first mPacket data frame by the first data according to check data and sending the first mPacket data frame to the sending control module;
the second buffer module is connected with the sending channel control module and used for buffering the first data into the second buffer module;
The check data generation module is used for forming the check data according to the first data and sending the check data to the sending channel control module.
Further, the functional data frame includes a verification frame and a response frame.
Further, the frame preemption verification module is used for completing the frame preemption function verification, and when the first and second mPacket frames are not transmitted by the current transmission control module; skipping to the SEND_VERIFY state, otherwise, maintaining an idle state for transmitting the verification frame;
send_verify: the method comprises the steps of sending a verification frame state, firstly waiting 12 clocks under the current state to meet the minimum frame interval requirement, then sending the verification frame to a physical link layer, and after the verification frame is sent, jumping to a WAIT_RESPOND state;
wait_response: waiting for a response frame state, returning to a SEND_VERIFY state when no response frame is received and no response frame is currently transmitted in a timing period, retransmitting a verification frame, waiting until the response frame is transmitted completely when the current frame is transmitted, retransmitting the verification frame, and jumping to the SEND_VERIFY state when the number of times the verification frame is transmitted reaches a set threshold value and the response frame is not received yet, otherwise jumping to the VERIFY_FAIL state;
Verify_fail: a verification failure state, wherein the current physical link of the verification frame does not support frame preemption;
VERIFIED: verifying a successful state, verifying that the current physical link supports frame preemption, and jumping to an idle state for transmitting a verification frame;
response_idle: an idle state of transmitting a response frame, when receiving the verification frame transmitted on the physical link, and when the first mPacket frame and the second mPacket frame are not transmitted on the current physical link, jumping to a SEND_RESPOND state, otherwise, keeping the current state;
send_response: and sending a response frame state, namely waiting 12 clocks to meet the requirement of the minimum frame interval, sending a response frame to the physical link, and jumping to a response_IDLE state after sending the response frame.
Further, the transmission control module comprises a state identification unit and a transmission unit;
the state identification unit is used for identifying and displaying the real-time state of the transmission control module;
the sending unit is connected with the state identification unit and used for determining the executed function and state jump according to the real-time state, wherein,
if the real-time state is a transmit data frame idle state,
when a first mPcket frame is received, jumping to a SEND_RT state, forwarding the received first mPcket frame to a physical link through an MII interface, and jumping to a data frame transmission idle state;
When a second mPcket frame is received, jumping to a SEND_NRT state, forwarding the received second mPcket frame to a physical link through an MII interface, and jumping to a data frame transmission idle state;
when the verification frame is received, jumping to a SEND_VER state, and after the received verification frame is forwarded to a physical link through an MII interface, jumping to a data frame transmission idle state;
and when the response frame is received, jumping to a SEND_RES state, and after the received response frame is forwarded to a physical link through an MII interface, jumping to a data frame transmission idle state.
Further, the receiving control module comprises a receiving control module, a CRC check module, a data buffer FIFO, an information buffer FIFO, a data distribution module and a frame reorganization module;
the receiving control module receives a mPcket data frame from a PHY interface receiving side, determines that the mPcket data frame is a first mPcket frame or a second mPcket frame according to a frame delimiting field and a fragment counting field of the mPcket data frame, sends a data field and a frame checking sequence to a CRC checking module for CRC checking, sends the mPcket data frame to a data cache FIFO, and sends type information corresponding to the data frame and a CRC checking result to an information cache FIFO;
The data splitting module splits the first mPacket frame to a first level data receiving and transmitting module, and splits the second mPack frame to a second level data receiving and transmitting module after being recombined by the frame recombination module.
Further, the state identification process and the jump process of the receiving control module are as follows:
IDLE: when the Rx_dv signal of the receiving side of the PHY interface side is pulled high, the state machine jumps to the READ_HEAD, otherwise, the current state is maintained;
read_head: reading the state of a DATA frame header, wherein the header comprises a preamble, frame delimitation and fragment counting, the total length is 8 bytes, and when the counting of the 8 bytes is finished, jumping to a READ_DATA state, otherwise, keeping the current state;
read_data: reading the data domain state of the data frame, writing the data domain of the received data frame into a data cache FIFO in the current state, simultaneously sending the received data to a CRC check module for CRC check, and jumping to an INFO_WR state when all the data of the data frame are read, otherwise, keeping the current state;
read_fcs: reading the FCS domain state of the data frame, sending the FCS domain to a CRC check module, receiving a check result, and jumping to an INFO_WR state after the FCS domain state is read, otherwise, keeping the current state;
Info_wr: and an information writing state, wherein the information of the current data frame is written into the information buffer FIFO, the state is maintained for a clock, and then the state is jumped to an IDLE state.
On the other hand, the invention also provides a data frame transmission method for supporting frame preemption based on the MAC IP core device supporting frame preemption, which comprises the following steps:
transmitting first-level data and performing bit width conversion to form a first mPcket frame;
transmitting second-level data and performing bit width conversion to form a second mPcket frame, wherein the priority of the first-level data is higher than that of the second-level data;
determining a sending strategy of the first mPcket frame and the second mPcket frame according to the functional data frame;
and transmitting the first mPcket frame and the second mPcket frame to a PHY chip according to the transmission strategy.
In a third aspect, the present invention also provides a data frame receiving method for supporting frame preemption based on the MAC IP core device supporting frame preemption as described above, where the method includes:
receiving a mPcket data frame from the PHY chip, and completing classification and recombination of the mPcket data frame according to parameters of the mPcket data frame and the receiving strategy to determine that the mPcket data frame is stored in a first-level data receiving and transmitting module or a second-level data receiving and transmitting module;
Determining a receiving strategy of the first level data receiving and transmitting module or the second level data receiving and transmitting module according to the functional data frame;
and storing the first mPcket data frame subjected to classification to a first level data receiving and transmitting module according to the receiving strategy, and storing the second mPcket data frame subjected to classification and recombination to a second level data receiving and transmitting module.
Compared with the prior art, the invention has the beneficial effects that by ensuring the independence of the data streams corresponding to the first mPcket frame and the second mPcket frame, the seamless transmission of the first mPcket frame and the second mPcket frame is reasonably realized, the data delay is greatly reduced, and the data transmission efficiency is improved.
Drawings
Fig. 1 is a schematic structural diagram of a MAC IP core device supporting frame preemption according to an embodiment of the present invention;
fig. 2 is a schematic diagram of the overall design of a MAC IP core supporting frame preemption according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an eMAC architecture in an embodiment of the invention;
fig. 4 is a schematic diagram of a receiving channel receiving control logic state transition according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a transmission control logic in a receiving channel control according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a data cache for transmission channel control according to an embodiment of the present invention;
Fig. 7 is a schematic diagram of state transition of a transmission control module according to an embodiment of the present invention;
fig. 8 is a schematic diagram illustrating state transition of a receiving control module according to an embodiment of the present invention;
FIG. 9 is a schematic diagram illustrating a state transition of a frame preemption verification module according to an embodiment of the present invention;
fig. 10 is a schematic diagram of a vehicle-mounted ethernet whole vehicle network architecture according to an embodiment of the present invention.
Detailed Description
In order that the objects and advantages of the invention will become more apparent, the invention will be further described with reference to the following examples; it should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood by those skilled in the art that these embodiments are merely for explaining the technical principles of the present invention, and are not intended to limit the scope of the present invention.
It should be noted that, in the description of the present invention, terms such as "upper," "lower," "left," "right," "inner," "outer," and the like indicate directions or positional relationships based on the directions or positional relationships shown in the drawings, which are merely for convenience of description, and do not indicate or imply that the apparatus or elements must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Furthermore, it should be noted that, in the description of the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention can be understood by those skilled in the art according to the specific circumstances.
Referring to fig. 1, a MAC IP core device supporting frame preemption provided in an embodiment of the present invention includes:
the first level data transceiver module 10 is configured to receive or transmit first level data and perform bit width conversion to form a first mPacket frame;
the second level data transceiver module 20 is configured to receive or send second level data and perform bit width conversion to form a second mPacket frame, where the priority of the first level data is higher than that of the second level data;
the frame preemption verification module 30 determines a sending policy or a receiving policy of the first mPacket frame and the second mPacket frame according to the functional data frame;
A transmission control module 40, configured to transmit the first mPacket frame and the second mPacket frame to a PHY chip according to the transmission policy determined by the frame preemption verification module;
the receiving control module 50 is configured to receive a mPacket data frame from the PHY chip, and complete classification and reassembly of the mPacket data frame according to parameters of the mPacket data frame and the receiving policy, so as to determine that the mPacket data frame is stored in the first-level data transceiver module or the second-level data transceiver module, so as to read the data frame.
Specifically, the first level data transceiver module may be an eMAC, and the second level data transceiver module may be a pMAC, where the eMAC is responsible for sending and receiving fast packets, and the pMAC is responsible for sending and receiving preemptible packets, and in the frame preemption mechanism, the fast packets and the preemptible packets are collected to the same PHY chip interface. The eMAC receives 32-bit quick packet data from an upper layer from an eMAC interface side, processes the 32-bit quick packet data into 8-bit quick packet data through bit width conversion and clock domain crossing, and then forms a mPcket frame to be sent to a sending control module to finish sending of the quick packet. The eMAC receives 8-bit fast packet data from the receiving control module, then the fast packet data is processed into 32-bit fast packet data through bit width conversion and clock domain crossing, and then the 32-bit fast packet data is sent to an upper layer through an eMAC interface, so that the fast packet receiving is completed. The pMAC receives 32-bit preemptive packet data from an upper layer from a pMAC interface side, then processes the preemptive packet data into 8-bit preemptive packet data through bit width conversion and cross-clock domain processing, and then forms a mPcket frame to send to a sending control module to finish the sending of the preemptive packet. The pMAC receives 8-bit preemptive packet data from the receiving control module, then the preemptive packet data is processed into 32-bit preemptive packet data through bit width conversion and clock domain crossing, and then the preemptive packet data is sent to an upper layer through a pMAC interface to finish the receiving of the preemptive packet.
Specifically, according to the embodiment of the invention, by ensuring the independence of the data streams corresponding to the first mPcket frame and the second mPcket frame, the seamless transmission of the first mPcket frame and the second mPcket frame is reasonably realized, the data delay is greatly reduced, and the data transmission efficiency is improved.
Specifically, the first level data transceiver module includes:
a receiving channel control module and a first buffer module, wherein
The receiving channel control module is connected with the receiving control module and used for receiving the mPcket data frame stored in the first-level data receiving and transmitting module;
the first buffer module is connected with the receiving channel control module and used for buffering the mPcket data frame into the first buffer module.
According to the embodiment of the invention, through the receiving channel control module and the first buffer module in the first-level data receiving and transmitting module, the mPcket data frame of the receiving control module is realized and stored, the receiving function in the receiving and transmitting module is realized, and the bidirectionality and the high efficiency of data transmission are ensured.
The first level data transmitting module further includes:
a sending channel control module, a second buffer module and a check data generation module, wherein,
the sending channel control module is used for receiving first data, and forming a first mPacket data frame by the first data according to check data and sending the first mPacket data frame to the sending control module;
The second buffer module is connected with the sending channel control module and used for buffering the first data into the second buffer module;
the check data generation module is used for forming the check data according to the first data and sending the check data to the sending channel control module.
According to the embodiment of the invention, the verification data generated according to the first mPcket data frame is communicated with the data to be transmitted through the set verification data generation module, so that the data security in the transmission process is ensured, and the data transmission security and transmission efficiency are greatly improved.
The first-level data transmission module and the second-level data transmission module in the embodiment of the present invention have substantially the same structure, and therefore, the second-level data transmission module will not be described again, and reference may be made to the structure of the first-level data transmission module. In practical applications, the functional requirements of emacs and pmacs are almost identical, and thus their design is almost identical.
The functional data frames include a verification frame and a response frame.
The frame preemption verification module is used for verifying the frame preemption function when the frame preemption function is not completed, and the first mPcket frame and the second mPcket frame which are not transmitted by the current transmission control module are transmitted; skipping to the SEND_VERIFY state, otherwise, maintaining an idle state for transmitting the verification frame;
Send_verify: the method comprises the steps of sending a verification frame state, firstly waiting 12 clocks under the current state to meet the minimum frame interval requirement, then sending the verification frame to a physical link layer, and after the verification frame is sent, jumping to a WAIT_RESPOND state;
wait_response: waiting for a response frame state, returning to a SEND_VERIFY state when no response frame is received and no response frame is currently transmitted in a timing period, retransmitting a verification frame, waiting until the response frame is transmitted completely when the current frame is transmitted, retransmitting the verification frame, and jumping to the SEND_VERIFY state when the number of times the verification frame is transmitted reaches a set threshold value and the response frame is not received yet, otherwise jumping to the VERIFY_FAIL state;
verify_fail: a verification failure state, wherein the current physical link of the verification frame does not support frame preemption;
VERIFIED: verifying a successful state, verifying that the current physical link supports frame preemption, and jumping to an idle state for transmitting a verification frame;
response_idle: an idle state of transmitting a response frame, when receiving the verification frame transmitted on the physical link, and when the first mPacket frame and the second mPacket frame are not transmitted on the current physical link, jumping to a SEND_RESPOND state, otherwise, keeping the current state;
Send_response: and sending a response frame state, namely waiting 12 clocks to meet the requirement of the minimum frame interval, sending a response frame to the physical link, and jumping to a response_IDLE state after sending the response frame.
In particular, through verification of the frame preemption function of the frame preemption verification module, the network node may determine the state of the physical link in order to select an appropriate link for path planning of the data flow.
Specifically, the transmission control module comprises a state identification unit and a transmission unit;
the state identification unit is used for identifying and displaying the real-time state of the transmission control module;
the sending unit is connected with the state identification unit and used for determining the executed function and state jump according to the real-time state, wherein,
if the real-time state is a transmit data frame idle state,
when a first mPcket frame is received, jumping to a SEND_RT state, forwarding the received first mPcket frame to a physical link through an MII interface, and jumping to a data frame transmission idle state;
when a second mPcket frame is received, jumping to a SEND_NRT state, forwarding the received second mPcket frame to a physical link through an MII interface, and jumping to a data frame transmission idle state;
When the verification frame is received, jumping to a SEND_VER state, and after the received verification frame is forwarded to a physical link through an MII interface, jumping to a data frame transmission idle state;
and when the response frame is received, jumping to a SEND_RES state, and after the received response frame is forwarded to a physical link through an MII interface, jumping to a data frame transmission idle state.
Specifically, the transmission control module is a module for directly transmitting data between the MAC sublayer and the physical layer, and the data is transmitted to the physical layer for processing by the transmission control module.
The receiving control module comprises a receiving control module, a CRC check module, a data buffer FIFO, an information buffer FIFO, a data distribution module and a frame reorganization module;
the receiving control module receives a mPcket data frame from a PHY interface receiving side, determines that the mPcket data frame is a first mPcket frame or a second mPcket frame according to a frame delimiting field and a fragment counting field of the mPcket data frame, sends a data field and a frame checking sequence to a CRC checking module for CRC checking, sends the mPcket data frame to a data cache FIFO, and sends type information corresponding to the data frame and a CRC checking result to an information cache FIFO;
the data splitting module splits the first mPacket frame to a first level data receiving and transmitting module, and splits the second mPack frame to a second level data receiving and transmitting module after being recombined by the frame recombination module.
The state identification process and the jump process of the receiving control module are as follows:
IDLE: when the Rx_dv signal of the receiving side of the PHY interface side is pulled high, the state machine jumps to the READ_HEAD, otherwise, the current state is maintained;
read_head: reading the state of a DATA frame header, wherein the header comprises a preamble, frame delimitation and fragment counting, the total length is 8 bytes, and when the counting of the 8 bytes is finished, jumping to a READ_DATA state, otherwise, keeping the current state;
read_data: reading the data domain state of the data frame, writing the data domain of the received data frame into a data cache FIFO in the current state, simultaneously sending the received data to a CRC check module for CRC check, and jumping to an INFO_WR state when all the data of the data frame are read, otherwise, keeping the current state;
read_fcs: reading the FCS domain state of the data frame, sending the FCS domain to a CRC check module, receiving a check result, and jumping to an INFO_WR state after the FCS domain state is read, otherwise, keeping the current state;
info_wr: and an information writing state, wherein the information of the current data frame is written into the information buffer FIFO, the state is maintained for a clock, and then the state is jumped to an IDLE state.
Specifically, through the states, the receiving control module completes the receiving and checking functions of the mPcket frame, and simultaneously extracts key information such as a frame delimiter, a fragment count, a tail frame identifier and the like of the mPcket frame, so that the subsequent module can conveniently classify and reorganize the data frame.
The embodiment of the invention also provides a data frame sending method supporting frame preemption, which comprises the following steps:
transmitting first-level data and performing bit width conversion to form a first mPcket frame;
transmitting second-level data and performing bit width conversion to form a second mPcket frame, wherein the priority of the first-level data is higher than that of the second-level data;
determining a sending strategy of the first mPcket frame and the second mPcket frame according to the functional data frame;
and transmitting the first mPcket frame and the second mPcket frame to a PHY chip according to the transmission strategy.
The embodiment of the invention also provides a data frame receiving method supporting frame preemption, which comprises the following steps:
receiving a mPcket data frame from the PHY chip, and completing classification and recombination of the mPcket data frame according to parameters of the mPcket data frame and the receiving strategy to determine that the mPcket data frame is stored in a first-level data receiving and transmitting module or a second-level data receiving and transmitting module;
Determining a receiving strategy of the first level data receiving and transmitting module or the second level data receiving and transmitting module according to the functional data frame;
and storing the first mPcket data frame subjected to classification to a first level data receiving and transmitting module according to the receiving strategy, and storing the second mPcket data frame subjected to classification and recombination to a second level data receiving and transmitting module.
In the following, the MAC IP core device supporting frame preemption in the embodiment of the present invention will be further described with reference to practical application, as shown in fig. 2, the overall design schematic diagram of the MAC IP core supporting frame preemption in the embodiment of the present invention, as shown in the drawing, the MAC IP core device mainly includes an eMAC, a pMAC, a transmission control module, a receiving control module, and a frame preemption verification module.
The emacs are responsible for the transmission and reception of fast packets. The eMAC receives 32-bit quick packet data from an upper layer from an eMAC interface side, processes the 32-bit quick packet data into 8-bit quick packet data through bit width conversion and clock domain crossing, and then forms a mPcket frame to be sent to a sending control module to finish sending of the quick packet. The eMAC receives 8-bit fast packet data from the receiving control module, then the fast packet data is processed into 32-bit fast packet data through bit width conversion and clock domain crossing, and then the 32-bit fast packet data is sent to an upper layer through an eMAC interface, so that the fast packet receiving is completed.
The pMAC is responsible for the transmission and reception of preemptible packets. The pMAC receives 32-bit preemptive packet data from an upper layer from a pMAC interface side, then processes the preemptive packet data into 8-bit preemptive packet data through bit width conversion and cross-clock domain processing, and then forms a mPcket frame to send to a sending control module to finish the sending of the preemptive packet.
The pMAC receives 8-bit preemptive packet data from the receiving control module, then the preemptive packet data is processed into 32-bit preemptive packet data through bit width conversion and clock domain crossing, and then the preemptive packet data is sent to an upper layer through a pMAC interface to finish the receiving of the preemptive packet.
The frame preemption verification module is responsible for responding to the transceiving of the frame and the verification frame and verifying whether two network nodes connected on the current physical link support the frame preemption function or not.
The sending control module is responsible for sending various mPcket frames to the PHY interface to finish sending the mPcket frames.
The receiving control module is responsible for receiving, checking, classifying and reorganizing the mPcket frames. The receiving control module receives the data frame from the PHY interface receiving side, then carries out frame check on the data frame, discards the data frame with frame check errors, determines the type of the mPcket frame according to each field of the data frame, and splices the mPcket frame of the preemptible packet into a complete preemptible frame packet.
As shown in fig. 3, fig. 3 is a schematic view of an eMAC structure in an embodiment of the present invention, where eMAC and pMAC are core modules of an MAC IP core, and play roles of interaction with upper layer data, temporary storage of data, framing during data transmission, and clock domain crossing processing of data. The functional requirements of emacs and pmacs are almost identical, so their design is almost identical.
As shown in fig. 3, the eMAC is mainly composed of a receive channel control, a buffer FIFO (first input first output first-in first-out queue), a CRC generation module, and a transmit channel control. The receiving channel is controlled to receive the data and the data information sent by the receiving control module and store the data and the data information into the buffer FIFO, and when the upper layer reads the data, the data is taken out from the buffer FIFO and then is provided for the upper layer through the eMAC interface side. The cache FIFO is responsible for data storage and cross-clock domain processing. And the sending channel control receives data from an upper layer through the eMAC interface side, stores the data into a cache FIFO, and when the data is sent, sends the data to a sending control module in a form of a mPcket frame. And the CRC generation module calculates CRC data according to the data sent by the sending channel control, and returns the CRC data to the sending channel control for framing.
In the control of the receiving channel in fig. 3, the receiving control logic and the sending control logic respectively complete the receiving and sending of the data, the receiving control logic and the sending control logic generally adopt two different clock domains, and the data complete the conversion of the clock domains through the buffer FIFO. As shown in fig. 4, fig. 4 is a schematic diagram of a state transition of a receiving channel receiving control logic, and the state transition of the receiving control logic is shown in fig. 4:
State_idle: receiving an idle STATE, jumping to a STATE_BYTE3 STATE when data arrives, otherwise, keeping the current STATE;
state_byy3: the first BYTE of 32-bit data receives the STATE, the data received currently stores the first BYTE of 32-bit data in the cache FIFO, if the data receiving is finished, the state_BY1 STATE is skipped, otherwise, the state_BYTE2 STATE is skipped;
state_byy2: a second BYTE of 32-bit data receiving STATE, wherein the currently received data is stored in the second BYTE of 32-bit data in the cache FIFO, if the data receiving is finished, the state_BY2 STATE is skipped, and if not, the state_BYTE1 STATE is skipped;
state_byy1: a third BYTE of 32-bit data receiving STATE, wherein the currently received data is stored in the third BYTE of 32-bit data in the cache FIFO, if the data receiving is finished, the state_B3 STATE is skipped, otherwise, the state_BYTE0 STATE is skipped;
state_byy0: a fourth BYTE receiving STATE of 32-bit data, wherein the currently received data is stored in a fourth BYTE of 32-bit data in a cache FIFO, if the data receiving is finished, the state_B0 STATE is skipped, and if not, the state_BYTE3 STATE is skipped;
State_be3: a data receiving end state 3, in which only the first byte has data in the 32-bit input data of the buffer FIFO;
state_be2: the data receiving end state 2 is that the first two bytes have data in 32-bit input data in the buffer FIFO;
state_be1: the data receiving end state 1 is that the first three bytes have data in 32-bit input data of the buffer FIFO;
state_be0: the data reception state ends 0, when the 32-bit input data of the buffer FIFO is valid.
Fig. 5 is a schematic diagram of transmission control logic in reception channel control, as shown in fig. 5, wherein:
sys_idle: an idle state is sent, when the eMAC interface side is ready to receive data and the buffer FIFO stores at least one complete frame of data, the state is jumped to a SYS_READ state, otherwise, the current state is maintained;
sys_read: the data output state is that in the current state, the data is moved out of the buffer memory FIFO and then sent to an upper layer application through the eMAC interface side, when the next highest order of the data read out of the buffer memory FIFO is 1, the data of a complete frame is indicated to be read completely, and the data jumps to the SYS_END state, otherwise, the current state is maintained;
sys_end: the output state ends, and since there is a clock delay from reading data from the buffer FIFO to outputting the data to the eMAC interface, the last 32bits of the full frame data is output to the eMAC interface in this state, and then jumps to the sys_idle state.
Through receiving channel control, the eMAC and the pMAC can receive data from a receiving interface, and transmit the data to an upper layer application after performing cross-clock domain processing and cross-bit width processing.
The sending channel control is responsible for receiving upper layer data, framing the data into a mPcket frame and then sending the mPcket frame to the sending control module. The transmission channel control consists of data buffer logic and framing transmission logic. The data caching logic of eMAC and pMAC are identical, but the framing-transmission logic is slightly different. As shown in fig. 6, fig. 6 is a logic diagram of a data buffer for transmission channel control, wherein,
sys_idle: the data buffer space state, when the buffer FIFO is in a non-full state and the eMAC interface side sends data, the data buffer space state jumps to a SYS_SOP state, otherwise, the current state is kept;
sys_sop: receiving a first 32bits data state, storing the first 32bits data into a buffer FIFO, and jumping to a SYS_MOP state;
sys_mop: receiving the residual data state, if the Almost_full signal of the cache FIFO is pulled high and Tx_mac_ EOP of the data is low, the residual data cannot be written into the cache FIFO, jumping to the SYS_EOP_DROP state, if the Almost_full signal is low and Tx_mac_ EOP is low, receiving all the residual data, jumping to the SYS_EOP_OK state, keeping the current state under the residual state, and continuing to accept the data;
Sys_eop_drop: the state of discarding the residual data, namely callback the write address of the cache FIFO to the position of caching the first 32bits of data, discarding the whole data, and then jumping to the SYS_IDLE state;
sys_eop_ok: and a data reception completion state, generating a data reception completion signal, and then jumping to a sys_idle state.
In the process of transmitting data, the occurrence of frame preemption is random, so that the eMAC transmits data to the pMAC to transmit a data transmission request, the pMAC responds to the data transmission request of the eMAC to avoid the data transmission request of the data to the pMAC, and the pMAC responds to the data transmission request of the eMAC to avoid the transmission conflict of the data frame. Before the eMAC sends, it is necessary to send the tx_apply signal to the pMAC and wait for the pMAC to reply to the tx_reply signal, and when the tx_reply signal is pulled up, the eMAC can send the real-time service packet, and when the eMAC sends the packet, the emac_send signal is pulled up. When the eMAC_send signal is low, the eMAC is in an idle state, the pMAC starts to send data, when the Tx_apply signal is high, the eMAC needs to send data, at the moment, if the frame preemption condition is met, the pMAC pauses data sending, finishes sending the current mPcket frame, and then pulls the Tx_reply signal high, and gives up a sending channel to the eMAC.
Through the control of a transmission channel, the eMAC and the pMAC receive the fast packet data and the preemptive packet data from an upper layer, and form a mPaget frame to be transmitted to a transmission control module seamlessly after the clock domain crossing processing and the bit width crossing processing. The signal tx_apply and the signal tx_reply ensure the real-time performance of the preemption process.
Specifically, the sending control module in the embodiment of the invention is mainly responsible for converging four types of data frames, namely a fast packet mPcket frame, a preemptible packet mPcket frame, a verification frame and a response frame, on the same physical link for sending. Because the response frame and the verification frame are only transmitted and received in the initial time of system startup, and the transmission of the fast packet mPcket frame and the preemptive packet mPcket frame cannot conflict, the conflict avoidance judgment is not needed.
As shown in fig. 7, fig. 7 is a state transition diagram of the transmission control module, wherein,
send_idle: transmitting a data frame idle state, jumping to a SEND_RT state when a fast packet mPcket frame is received, jumping to a SEND_NRT state when a preemptible packet mPcket frame is received, jumping to a SEND_VER state when a verification frame is received, and jumping to a SEND_RES state when a response frame is received;
Send_rt: transmitting a fast packet state, forwarding a received fast packet mPcket frame to a physical link layer through an MII interface, and jumping to a SEND_IDLE state after the transmission is completed;
send_nrt: transmitting a preemptive packet state, forwarding a received preemptive packet mPcket frame to a physical link through an MII interface, and jumping to a SEND_IDLE state after the transmission is completed;
send_ver: transmitting a verification frame state, forwarding the received verification frame to a physical link through an MII interface, and jumping to a SEND_IDLE state after the transmission is completed;
send_res: and transmitting a response frame state, forwarding the received response frame to a physical link through an MII interface, and jumping to a SEND_IDLE state after the transmission is completed.
The sending control module is a module for directly sending data between the MAC sub-layer and the physical layer, and the data is sent to the physical layer for processing through the sending control module.
Specifically, the receiving control module is connected with the physical layer through the PHY interface, so that the correctness of the data frame needs to be checked, and due to the complexity of the mPacket frames, different mPacket frames need to be classified and split, and the complete preemptive frame packets may need to be recombined for the mPacket frames forming the preemptive packets, so that the functions cross each other. The receiving control module consists of a receiving control module, a CRC check module, a data buffer FIFO, an information buffer FIFO, a data distribution module and a frame reorganization module.
The receiving control module receives a data frame from the PHY interface receiving side, determines the type of the data frame according to a frame delimitation field and a fragment count field of the data frame, sends a data field and a frame check sequence to the CRC check module for CRC check, then sends the data frame to the data cache FIFO, and sends data frame type information and a CRC check result to the information cache FIFO.
As shown in fig. 8, fig. 8 is a state transition diagram of the receiving control module, wherein,
IDLE: when the Rx_dv signal of the receiving side of the PHY interface side is pulled high, the state machine jumps to the READ_HEAD, otherwise, the current state is maintained;
read_head: reading the state of a DATA frame header, wherein the header comprises a preamble, frame delimitation and fragment counting, the total length is 8 bytes, and when the counting of the 8 bytes is finished, jumping to a READ_DATA state, otherwise, keeping the current state;
read_data: reading the data domain state of the data frame, writing the data domain of the received data frame into a data cache FIFO in the current state, simultaneously sending the received data to a CRC check module for CRC check, and jumping to an INFO_WR state when all the data of the data frame are read, otherwise, keeping the current state;
Read_fcs: reading the FCS domain state of the data frame, sending the FCS domain to a CRC check module, receiving a check result, and jumping to an INFO_WR state after the FCS is read, otherwise, keeping the current state;
info_wr: and an information writing state, wherein the information of the current data frame is written into the information buffer FIFO, the state is maintained for a clock, and then the state is jumped to an IDLE state.
Through the states, the receiving control module completes the receiving and checking functions of the mPcket frame, and simultaneously extracts key information such as a frame delimiter, a fragment count, a tail frame identification and the like of the mPcket frame, so that the subsequent module can conveniently classify and reorganize the data frame.
The frame preemption verification module needs to verify whether a receiving node and a transmitting node on a data link support frame preemption, the states of which are shown in fig. 9, and fig. 9 is a state transition diagram of the frame preemption verification module:
verify_idle: an IDLE state of transmitting a verification frame, when the system is not completely verified by a frame preemption function, and a fast packet and a preemptive packet which are not transmitted by a current transmission control module are transmitted, jumping to a SEND_VERIFY state, otherwise, maintaining the VERIFY_IDLE state;
send_verify: the method comprises the steps of sending a verification frame state, firstly waiting 12 clocks under the current state to meet the minimum frame interval requirement, then sending the verification frame to a physical link layer, and jumping to a WAIT_RESPOND state after the verification frame is sent;
Wait_response: waiting for a response frame state, returning to a SEND_VERIFY state when no response frame is received and no response frame is currently transmitted in a timing period, retransmitting a verification frame, waiting until the response frame is transmitted completely when the current frame is transmitted, retransmitting the verification frame, and jumping to the SEND_VERIFY state when the number of times the verification frame is transmitted reaches a set threshold value and the response frame is not received yet, otherwise jumping to the VERIFY_FAIL state;
verify_fail: a verification failure state, wherein the current physical link of the verification frame does not support frame preemption;
VERIFIED: verifying a successful state, verifying that the current physical link supports frame preemption, and jumping to a VERIFY_IDLE state;
response_idle: an idle state of transmitting a response frame, when receiving a verification frame transmitted on a physical link, and when a fast packet frame and a preemptive packet frame are not transmitted on a current physical link, jumping to a SEND_RESPOND state, otherwise, maintaining the current state;
send_response: and sending a response frame state, namely waiting 12 clocks to meet the requirement of the minimum frame interval, sending a response frame to the physical link, and jumping to a response_IDLE state after sending the response frame.
Through the verification of the frame preemption function of the frame preemption verification module, the network node can determine the state of the physical link so as to select an appropriate link to route the data flow.
And integrating the MAC IP core design supporting the frame preemption, decomposing the process into each functional module by the MAC IP core device based on the complex sending and receiving processes of the mPcket frame to finish the support of the frame preemption mechanism in the form of a pipeline.
In practical application, the frame preemption technique is particularly important in the whole vehicle network. In the intelligent cabin, the audio and video can be watched more smoothly, and the experience sense is improved. In the automatic driving domain, important data streams can be smoothly transmitted under the condition of low delay, and a reliable platform is provided for future unmanned technologies. As shown in fig. 10, fig. 10 is a schematic diagram of an overall vehicle network architecture using a vehicle-mounted ethernet, where a vehicle domain network is respectively connected with a vehicle body control, a power assembly, a chassis control, an infotainment and an ADA through the vehicle-mounted ethernet.
Thus far, the technical solution of the present invention has been described in connection with the preferred embodiments shown in the drawings, but it is easily understood by those skilled in the art that the scope of protection of the present invention is not limited to these specific embodiments. Equivalent modifications and substitutions for related technical features may be made by those skilled in the art without departing from the principles of the present invention, and such modifications and substitutions will be within the scope of the present invention.
The foregoing description is only of the preferred embodiments of the invention and is not intended to limit the invention; various modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A MAC IP core apparatus supporting frame preemption, comprising:
the first-level data receiving and transmitting module is used for receiving or transmitting first-level data and performing bit width conversion to form a first mPcket frame;
the second level data receiving and transmitting module is used for receiving or transmitting second level data and performing bit width conversion to form a second mPcket frame, and the priority of the first level data is higher than that of the second level data;
the frame preemption verification module determines a sending strategy or a receiving strategy of the first mPcket frame and the second mPcket frame according to the functional data frame;
the transmission control module is used for transmitting the first mPcket frame and the second mPcket frame to the PHY chip according to the transmission strategy determined by the frame preemption verification module;
the receiving control module is used for receiving the mPcket data frames from the PHY chip, and finishing the classification and recombination of the mPcket data frames according to the parameters of the mPcket data frames and the receiving strategy so as to determine that the mPcket data frames are stored in the first-level data receiving and transmitting module or the second-level data receiving and transmitting module, so that the data frames are read.
2. The MAC IP core device supporting frame preemption of claim 1,
the first level data transceiver module includes:
a receiving channel control module and a first buffer module, wherein
The receiving channel control module is connected with the receiving control module and used for receiving the mPcket data frame stored in the first-level data receiving and transmitting module;
the first buffer module is connected with the receiving channel control module and used for buffering the mPcket data frame into the first buffer module.
3. The MAC IP core device supporting frame preemption of claim 2,
the first level data transmitting module further includes:
a sending channel control module, a second buffer module and a check data generation module, wherein,
the sending channel control module is used for receiving first data, and forming a first mPacket data frame by the first data according to check data and sending the first mPacket data frame to the sending control module;
the second buffer module is connected with the sending channel control module and used for buffering the first data into the second buffer module;
the check data generation module is used for forming the check data according to the first data and sending the check data to the sending channel control module.
4. A MAC IP core device supporting frame preemption as in claim 3, wherein the functional data frames comprise an authentication frame and a response frame.
5. The MAC IP core device supporting frame preemption of claim 4,
the frame preemption verification module is used for verifying the frame preemption function when the frame preemption function is not completed, and the first mPcket frame and the second mPcket frame which are not transmitted by the current transmission control module are transmitted; skipping to the SEND_VERIFY state, otherwise, maintaining an idle state for transmitting the verification frame;
send_verify: the method comprises the steps of sending a verification frame state, firstly waiting 12 clocks under the current state to meet the minimum frame interval requirement, then sending the verification frame to a physical link layer, and after the verification frame is sent, jumping to a WAIT_RESPOND state;
wait_response: waiting for a response frame state, returning to a SEND_VERIFY state when no response frame is received and no response frame is currently transmitted in a timing period, retransmitting a verification frame, waiting until the response frame is transmitted completely when the current frame is transmitted, retransmitting the verification frame, and jumping to the SEND_VERIFY state when the number of times the verification frame is transmitted reaches a set threshold value and the response frame is not received yet, otherwise jumping to the VERIFY_FAIL state;
Verify_fail: a verification failure state, wherein the current physical link of the verification frame does not support frame preemption;
VERIFIED: verifying a successful state, verifying that the current physical link supports frame preemption, and jumping to an idle state for transmitting a verification frame;
response_idle: an idle state of transmitting a response frame, when receiving the verification frame transmitted on the physical link, and when the first mPacket frame and the second mPacket frame are not transmitted on the current physical link, jumping to a SEND_RESPOND state, otherwise, keeping the current state;
send_response: and sending a response frame state, namely waiting 12 clocks to meet the requirement of the minimum frame interval, sending a response frame to the physical link, and jumping to a response_IDLE state after sending the response frame.
6. The MAC IP core device supporting frame preemption of claim 5,
the transmission control module comprises a state identification unit and a transmission unit;
the state identification unit is used for identifying and displaying the real-time state of the transmission control module;
the sending unit is connected with the state identification unit and used for determining the executed function and state jump according to the real-time state, wherein,
if the real-time state is a transmit data frame idle state,
When a first mPcket frame is received, jumping to a SEND_RT state, forwarding the received first mPcket frame to a physical link through an MII interface, and jumping to a data frame transmission idle state;
when a second mPcket frame is received, jumping to a SEND_NRT state, forwarding the received second mPcket frame to a physical link through an MII interface, and jumping to a data frame transmission idle state;
when the verification frame is received, jumping to a SEND_VER state, and after the received verification frame is forwarded to a physical link through an MII interface, jumping to a data frame transmission idle state;
and when the response frame is received, jumping to a SEND_RES state, and after the received response frame is forwarded to a physical link through an MII interface, jumping to a data frame transmission idle state.
7. The MAC IP core device supporting frame preemption of claim 6,
the receiving control module comprises a receiving control module, a CRC check module, a data buffer FIFO, an information buffer FIFO, a data distribution module and a frame reorganization module;
the receiving control module receives a mPcket data frame from a PHY interface receiving side, determines that the mPcket data frame is a first mPcket frame or a second mPcket frame according to a frame delimiting field and a fragment counting field of the mPcket data frame, sends a data field and a frame checking sequence to a CRC checking module for CRC checking, sends the mPcket data frame to a data cache FIFO, and sends type information corresponding to the data frame and a CRC checking result to an information cache FIFO;
The data splitting module splits the first mPacket frame to a first level data receiving and transmitting module, and splits the second mPack frame to a second level data receiving and transmitting module after being recombined by the frame recombination module.
8. The MAC IP core device supporting frame preemption of claim 7,
the state identification process and the jump process of the receiving control module are as follows:
IDLE: when the Rx_dv signal of the receiving side of the PHY interface side is pulled high, the state machine jumps to the READ_HEAD, otherwise, the current state is maintained;
read_head: reading the state of a DATA frame header, wherein the header comprises a preamble, frame delimitation and fragment counting, the total length is 8 bytes, and when the counting of the 8 bytes is finished, jumping to a READ_DATA state, otherwise, keeping the current state;
read_data: reading the data domain state of the data frame, writing the data domain of the received data frame into a data cache FIFO in the current state, simultaneously sending the received data to a CRC check module for CRC check, and jumping to an INFO_WR state when all the data of the data frame are read, otherwise, keeping the current state;
Read_fcs: reading the FCS domain state of the data frame, sending the FCS domain to a CRC check module, receiving a check result, and jumping to an INFO_WR state after the FCS domain state is read, otherwise, keeping the current state;
info_wr: and an information writing state, wherein the information of the current data frame is written into the information buffer FIFO, the state is maintained for a clock, and then the state is jumped to an IDLE state.
9. A data frame transmission method supporting frame preemption based on a MAC IP core device supporting frame preemption as in any of claims 1-8, comprising:
transmitting first-level data and performing bit width conversion to form a first mPcket frame;
transmitting second-level data and performing bit width conversion to form a second mPcket frame, wherein the priority of the first-level data is higher than that of the second-level data;
determining a sending strategy of the first mPcket frame and the second mPcket frame according to the functional data frame;
and transmitting the first mPcket frame and the second mPcket frame to a PHY chip according to the transmission strategy.
10. A data frame reception method supporting frame preemption based on a MAC IP core device supporting frame preemption as in any of claims 1-8, comprising:
Receiving a mPcket data frame from the PHY chip, and completing classification and recombination of the mPcket data frame according to parameters of the mPcket data frame and the receiving strategy to determine that the mPcket data frame is stored in a first-level data receiving and transmitting module or a second-level data receiving and transmitting module;
determining a receiving strategy of the first level data receiving and transmitting module or the second level data receiving and transmitting module according to the functional data frame;
and storing the first mPcket data frame subjected to classification to a first level data receiving and transmitting module according to the receiving strategy, and storing the second mPcket data frame subjected to classification and recombination to a second level data receiving and transmitting module.
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