CN116032307A - Integrated chip for high-voltage isolation, high-voltage isolator and high-voltage isolation method - Google Patents
Integrated chip for high-voltage isolation, high-voltage isolator and high-voltage isolation method Download PDFInfo
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Abstract
The embodiment of the invention relates to the technical field of isolation circuits, in particular to an integrated chip for high-voltage isolation, a high-voltage isolator and a high-voltage isolation method. Wherein, integrated chip includes: the device comprises two isolation capacitors, a signal modulation unit and a signal demodulation unit; the signal modulation unit and the signal demodulation unit are connected in parallel to form a parallel circuit, and the parallel circuit is connected in series between the two isolation capacitors; when the input end of the parallel circuit is connected with an external current source to receive an input signal, the signal modulation unit generates differential radio frequency signals at two ends of the parallel circuit based on the input signal; the signal demodulation unit is used for demodulating the differential radio frequency signals at two ends of the parallel circuit to obtain a restored input signal. Therefore, the integrated chip of the scheme comprises the signal modulation unit and the signal demodulation unit, and can be used as a transmitting end of the differential radio frequency signal and a receiving end of the differential radio frequency signal, so that the problem of low transmission efficiency of the radio frequency signal in the traditional high-voltage isolator is solved.
Description
Technical Field
The embodiment of the invention relates to the technical field of isolation circuits, in particular to an integrated chip for high-voltage isolation, a high-voltage isolator and a high-voltage isolation method.
Background
A high voltage isolator is a chip that transmits digital data between different voltage domains while avoiding the passage of excessive dc voltages or uncontrolled transient voltages between the two. Currently, most high-voltage isolators adopt a capacitive isolation method.
As shown in fig. 1, which is an embodiment of a conventional capacitive isolator based on-off keying, in the drawing, a modulation module integrated on a chip 1 is used for generating a radio frequency signal, and a demodulation module integrated on a chip 2 demodulates a received radio frequency signal to complete data transmission between two chips with a high-voltage isolation function. However, due to the different circuit structures of the modulation module and the demodulation module, that is, the resonance frequencies of the transmitting end and the receiving end of the radio frequency signal are different, the transmission efficiency of the radio frequency signal is low.
Thus, a new integrated chip for high voltage isolation is needed.
Disclosure of Invention
In order to solve the problem of low transmission efficiency of radio frequency signals in a traditional high-voltage isolator, the embodiment of the invention provides an integrated chip for high-voltage isolation, the high-voltage isolator and a high-voltage isolation method.
In a first aspect, an embodiment of the present invention provides an integrated chip for high voltage isolation, including: the device comprises two isolation capacitors, a signal modulation unit and a signal demodulation unit; the signal modulation unit and the signal demodulation unit are connected in parallel to form a parallel circuit, and the parallel circuit is connected in series between the two isolation capacitors;
when the input end of the parallel circuit is connected with an external current source to receive an input signal, the signal modulation unit generates differential radio frequency signals at two ends of the parallel circuit based on the input signal;
the signal demodulation unit is used for demodulating the differential radio frequency signals at two ends of the parallel circuit to obtain a restored input signal.
In one possible design, the signal modulation unit includes: the negative resistance module and the LC resonant circuit are connected in parallel with the negative resistance module; the LC resonant circuit comprises a capacitor C1, an inductor L1 and an inductor L2;
the inductor L1 and the inductor L2 are connected in series, and the capacitor C1 is connected in parallel to both ends of the inductor L1 and the inductor L2 connected in series.
In one possible design, the negative resistance module includes: a PMOS tube M1 and a PMOS tube M2;
the grid electrodes of the PMOS tube M1 and the PMOS tube M2 are respectively connected to two ends of the LC resonance loop;
the source electrode of the PMOS tube M1 is connected to the source electrode of the PMOS tube M2, and the drain electrode of the PMOS tube M2 is connected to a connecting line of the grid electrode of the PMOS tube M2 and the LC resonant circuit;
the drain electrode of the PMOS tube M2 is connected to the connection line of the grid electrode of the PMOS tube M1 and the LC resonant circuit.
In one possible design, the center taps of the inductor L1 and the inductor L2 are grounded.
In one possible design, the signal demodulation unit includes: the receiving module, the coupling capacitor C4 and the coupling capacitor C5; the coupling capacitor C4 and the coupling capacitor C5 are used for coupling differential radio frequency signals at two ends of the parallel circuit to the receiving module;
one end of the coupling capacitor C4 is connected to one output end of the signal modulation unit, and the other end of the coupling capacitor C4 is connected to the receiving module;
and one end of the coupling capacitor C5 is connected to the other output end of the signal modulation unit, and the other end of the coupling capacitor C5 is connected to the receiving module.
In one possible design, the receiving module includes: NMOS tube M3 and NMOS tube M4;
the grid electrode of the NMOS tube M3 is connected to the connecting line of the coupling capacitor C4 and the bias potential, the source electrode of the NMOS tube M3 is connected to the connecting line of the coupling capacitor C5 and the signal modulation unit, and the drain electrode of the NMOS tube M4 is connected with the drain electrode of the NMOS tube;
the gate of the NMOS tube M4 is connected to the connection line of the coupling capacitor C5 and the bias potential, and the source of the NMOS tube M4 is connected to the connection line of the coupling capacitor C4 and the signal modulation unit.
In a second aspect, an embodiment of the present invention further provides a high voltage isolator, including: a first integrated chip and a second integrated chip identical to the first integrated chip; wherein the first integrated chip and the second integrated chip are the integrated chips described in any embodiment of the present disclosure;
a parallel circuit formed by connecting a signal modulation unit and a signal demodulation unit in the first integrated chip in parallel is connected between two isolation capacitors in series to form a first series circuit; a parallel circuit formed by connecting the signal modulation unit and the signal demodulation unit in parallel in the second integrated chip is connected in series between the two isolation capacitors to form a second series circuit; the first end of the first series circuit is connected with the second end of the second series circuit, and the second end of the first series circuit is connected with the first end of the second series circuit.
In one possible design, when the first integrated chip is connected to an external current source to receive an input signal, the signal demodulation unit of the second integrated chip is connected to an output end to output a restored input signal;
when the second integrated chip is connected to an external current source to receive an input signal, the signal demodulation unit of the first integrated chip is connected with the output end to output a restored input signal.
In a third aspect, an embodiment of the present invention further provides a high voltage isolation method based on the high voltage isolator according to any one of the embodiments of the present specification, including:
determining an integrated chip serving as a transmitting end and an integrated chip serving as a receiving end in the first integrated chip and the second integrated chip;
transmitting an input signal to an integrated chip serving as a transmitting end by using an external current source, and generating differential radio frequency signals at two ends of the parallel circuit in the integrated chip serving as the transmitting end according to the input signal by using a signal modulation unit in the integrated chip serving as the transmitting end;
transmitting the differential radio frequency signals to an integrated chip serving as a receiving end by using two isolation capacitors connected in series at two ends of the parallel circuit;
and demodulating the differential radio frequency signal by using a signal demodulation unit in an integrated chip serving as a receiving end to obtain a restored input signal.
In one possible design, the demodulating the differential radio frequency signal with the signal demodulating unit in the integrated chip as the receiving end includes:
when the signal demodulation unit in the integrated chip serving as the receiving end does not receive the differential radio frequency signal, the signal demodulation unit outputs a high level;
when the signal demodulation unit in the integrated chip as the receiving end receives the differential radio frequency signal, the signal demodulation unit outputs a low level.
The embodiment of the invention provides an integrated chip for high-voltage isolation, which comprises two isolation capacitors, a signal modulation unit and a signal demodulation unit, wherein the signal modulation unit and the signal demodulation unit are connected in parallel to form a parallel circuit, and the parallel circuit is connected in series between the two isolation capacitors. When the input end of the parallel circuit is connected with an external current source to receive an input signal, the signal modulation unit generates differential radio frequency signals at two ends of the parallel circuit based on the input signal; and the signal demodulation unit is used for demodulating the differential radio frequency signals at two ends of the parallel circuit to obtain a restored input signal. Therefore, the integrated chip for high-voltage isolation provided by the scheme comprises the signal modulation unit and the signal demodulation unit, and can be used as a transmitting end of the differential radio frequency signal and a receiving end of the differential radio frequency signal, so that the problem of low transmission efficiency of the radio frequency signal in the traditional high-voltage isolator is solved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a conventional capacitive isolator according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of an integrated chip for high voltage isolation according to one embodiment of the present invention;
FIG. 3 is a circuit diagram of another integrated chip for high voltage isolation according to an embodiment of the present invention;
FIG. 4 is a schematic circuit diagram of a high voltage isolator according to an embodiment of the present invention;
FIG. 5 is a signal waveform diagram of a high voltage isolator for communication according to an embodiment of the present invention;
fig. 6 is a flowchart of a high voltage isolation method according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments, and all other embodiments obtained by those skilled in the art without making any inventive effort based on the embodiments of the present invention are within the scope of protection of the present invention.
As described above, the conventional capacitive isolator based on-off keying includes two integrated chips, one of which includes a modulation module for generating a radio frequency signal, and the other of which includes a demodulation module for demodulating a received radio frequency signal to accomplish data transmission between the two integrated chips having a high voltage isolation function. However, due to the different circuit structures of the modulation module and the demodulation module, that is, the different resonant frequencies of the transmitting end and the receiving end of the radio frequency signal, the transmission efficiency of the radio frequency signal is low.
The traditional solutions mainly comprise two methods, namely, under the condition that the sensitivity of a receiving end is certain, the power of a radio frequency signal is increased, so that the power consumption is increased; the other is to add an extra resonant frequency matching circuit at the transmitting end and the receiving end, but the chip area is increased, and meanwhile, the matching circuit is difficult to ensure that the matching is good under the conditions of temperature, process and the like, and the reliability and the stability of the chip are difficult to ensure.
In order to solve the above technical problems, the inventor can consider that the modulation module and the demodulation module are integrated on a single integrated chip, so that both the two integrated chips can be used as a transmitting end of the radio frequency signal and a receiving end of the radio frequency signal, and the resonant frequencies of the transmitting end and the receiving end of the radio frequency signal are identical due to the circuit structures of the integrated chips on the two sides, so that the transmission efficiency of the radio frequency signal is ensured.
Specific implementations of the above concepts are described below.
Referring to fig. 2, an embodiment of the present invention provides an integrated chip for high voltage isolation, including: the device comprises two isolation capacitors, a signal modulation unit and a signal demodulation unit; the signal modulation unit and the signal demodulation unit are connected in parallel to form a parallel circuit, and the parallel circuit is connected in series between the two isolation capacitors;
when the input end of the parallel circuit is connected with an external current source to receive an input signal, the signal modulation unit generates differential radio frequency signals at two ends of the parallel circuit based on the input signal;
the signal demodulation unit is used for demodulating the differential radio frequency signals at two ends of the parallel circuit to obtain a restored input signal.
In the embodiment of the invention, the integrated chip comprises two isolation capacitors, a signal modulation unit and a signal demodulation unit, wherein the signal modulation unit and the signal demodulation unit are connected in parallel to form a parallel circuit, and the parallel circuit is connected in series between the two isolation capacitors. When the input end of the parallel circuit is connected with an external current source to receive an input signal, the signal modulation unit generates differential radio frequency signals at two ends of the parallel circuit based on the input signal; and the signal demodulation unit is used for demodulating the differential radio frequency signals at two ends of the parallel circuit to obtain a restored input signal. Therefore, the integrated chip for high-voltage isolation provided by the scheme comprises the signal modulation unit and the signal demodulation unit, and can be used as a transmitting end of the differential radio frequency signal and a receiving end of the differential radio frequency signal, so that the problem of low transmission efficiency of the radio frequency signal in the traditional high-voltage isolator is solved.
The following description is made with reference to the circuit diagram shown in fig. 2.
In an embodiment of the present invention, a signal modulation unit includes: the LC resonant circuit is connected with the negative resistance module in parallel; the LC resonant circuit comprises a capacitor C1, an inductor L1 and an inductor L2;
the inductor L1 and the inductor L2 are connected in series, and the capacitor C1 is connected in parallel to both ends of the series-connected inductor L1 and inductor L2.
In this embodiment, -Gm is a negative resistance module, where the negative resistance module and the LC tank form an oscillator, i.e. a signal modulation unit, and when an external current source controlled by an input signal is connected to an input terminal of the signal modulation unit, the on-off of the current source is controlled according to the input signal. When the current source has current, the signal modulation unit generates differential radio frequency signals and outputs the differential radio frequency signals at the P1 and P2 ends, and when the current source is closed, -Gm stops vibrating with an LC resonant circuit connected in parallel with the Gm, so that OOK signals modulated by input signals are generated at the P1 and P2 ends.
It should be noted that, the capacitor C1 is a parasitic capacitor and an actively added capacitor device of all devices (such as an isolation capacitor, an inductor, a negative resistance module, and a load of the same structure connected by a binding wire and facing the integrated chip) seen from the negative resistance module. The isolation capacitor C2 and the isolation capacitor C3 are both composed of top and sub-top metals and a silicon dioxide layer therebetween, wherein the thickness of silicon dioxide determines the withstand voltage performance of the high voltage isolation device.
In the embodiment of the invention, the center taps of the inductor L1 and the inductor L2 are grounded.
In this embodiment, since the differential rf signal is a high-frequency signal, the common-mode transient noise is a low-frequency noise, and the internal resistance of the inductor is proportional to the frequency of the signal passing through the differential rf signal, so that the common-mode transient noise preferentially passes through the inductor L1 and the inductor L2, and the center taps of the inductor L1 and the inductor L2 are grounded, so that the common-mode transient noise can be greatly attenuated, and the common-mode transient immunity (CMTI) can be significantly improved.
Referring to fig. 3, in an embodiment of the present invention, the negative resistance module includes: a PMOS tube M1 and a PMOS tube M2;
the grid electrodes of the PMOS tube M1 and the PMOS tube M2 are respectively connected to two ends of the LC resonance loop;
the source electrode of the PMOS tube M1 is connected to the source electrode of the PMOS tube M2, and the drain electrode of the PMOS tube M2 is connected to a connecting line of the grid electrode of the PMOS tube M2 and the LC resonant circuit;
the drain electrode of the PMOS tube M2 is connected to the connection line of the grid electrode of the PMOS tube M1 and the LC resonant circuit.
It will be appreciated that this embodiment is one implementation of a negative resistance module, and other implementations of the negative resistance module are possible. For example, NMOS tube is used to replace PMOS tube, and the connection mode is changed correspondingly.
Referring to fig. 2, in an embodiment of the present invention, a signal demodulation unit includes: the receiving module, the coupling capacitor C4 and the coupling capacitor C5; the coupling capacitor C4 and the coupling capacitor C5 are used for coupling differential radio frequency signals at two ends of the parallel circuit to the receiving module;
one end of the coupling capacitor C4 is connected to one output end of the signal modulation unit, and the other end of the coupling capacitor C4 is connected to the receiving module;
and one end of the coupling capacitor C5 is connected to the other output end of the signal modulation unit, and the other end of the coupling capacitor C is connected to the receiving module.
In this embodiment, rx is a receiving module, and the coupling capacitor C4 and the coupling capacitor C5 are used to couple differential radio frequency signals at two ends (i.e. the point P1 and the point P2) of the parallel circuit to the receiving module. The receiving module demodulates the differential radio frequency signals to obtain restored input signals.
Referring to fig. 3, in an embodiment of the present invention, a receiving module includes: NMOS tube M3 and NMOS tube M4;
the grid electrode of the NMOS tube M3 is connected to the connecting line of the coupling capacitor C4 and the bias potential, the source electrode of the NMOS tube M3 is connected to the connecting line of the coupling capacitor C5 and the signal modulation unit, and the drain electrode of the NMOS tube M4 is connected with the drain electrode of the NMOS tube;
the gate of the NMOS tube M4 is connected to the connection line of the coupling capacitor C5 and the bias potential, and the source is connected to the connection line of the coupling capacitor C4 and the signal modulation unit.
In this embodiment, when the points P1 and P2 have no differential radio frequency signal, the gates of the NMOS transistor M3 and the NMOS transistor M4 are at a bias potential, the bias potential is smaller than the threshold voltages of the NMOS transistor M3 and the NMOS transistor M4, and at this time, the NMOS transistor M3 and the NMOS transistor M4 are not turned on, so that the OUT port of the signal demodulation unit outputs a high potential; when the differential radio frequency signals are provided at the points P1 and P2 and the amplitude is enough, the differential radio frequency signals at the points P1 and P2 are alternately beyond the threshold voltages of the NMOS transistor M3 and the NMOS transistor M4, and at the moment, the NMOS transistor M3 and the NMOS transistor M4 are alternately turned on in a time-sharing manner, and then the OUT port of the signal demodulation unit outputs a low potential.
It should be noted that, not only in the embodiment, when the P1 and P2 points do not have the differential radio frequency signal, the OUT port of the signal demodulation unit outputs a high level; when the P1 and P2 points have differential radio frequency signals, the OUT port outputs a low level. It can be understood that the OUT port of the signal demodulation unit outputs a high level when the P1 and P2 points do not have differential radio frequency signals, by changing circuit devices or connection modes; when the P1 and P2 points have differential radio frequency signals, the OUT port outputs a low level. As long as the signal demodulation unit can restore the input signal by the differential radio frequency signal generated by the signal modulation unit.
Referring to fig. 4, the present embodiment also provides a high voltage isolator, including: a first integrated chip and a second integrated chip identical to the first integrated chip; wherein, the first integrated chip and the second integrated chip are the integrated chips of any embodiment in the specification;
a parallel circuit formed by connecting a signal modulation unit and a signal demodulation unit in parallel in a first integrated chip is connected in series between two isolation capacitors to form a first series circuit; a parallel circuit formed by connecting a signal modulation unit and a signal demodulation unit in the second integrated chip in parallel is connected between two isolation capacitors in series to form a second series circuit; the first end of the first series circuit is connected to the second end of the second series circuit, and the second end of the first series circuit is connected to the first end of the second series circuit.
In the embodiment of the present invention, as shown in fig. 4, the first integrated chip (chip 1) and the second integrated chip (chip 2) are symmetrically placed, and the first integrated chip and the second integrated chip are identical. The isolation capacitor C2 of the first integrated chip is connected with the isolation capacitor C3 of the second integrated chip through a binding wire, and the isolation capacitor C3 of the first integrated chip is connected with the isolation capacitor C2 of the second integrated chip through a binding wire.
In the embodiment of the invention, when the first integrated chip is connected with an external current source to receive an input signal, the signal demodulation unit of the second integrated chip is connected with the output end to output a restored input signal; when the second integrated chip is connected to an external current source to receive an input signal, the signal demodulation unit of the first integrated chip is connected with the output end to output a restored input signal.
In this embodiment, when any one of the integrated chips is connected to an external current source to receive an input signal, the integrated chip that receives the input signal is used as a transmitting end of a radio frequency signal, a signal modulation unit in the integrated chip generates a differential radio frequency signal based on the input signal, and the differential radio frequency signal is coupled to T1 and T2 through an isolation capacitor C2 and an isolation capacitor C3 and then transmitted to ports T1 and T2 of the integrated chip that is used as a receiving end through a binding wire 1 and a binding wire 2. And demodulating the differential radio frequency signal by a signal demodulation unit in the integrated chip serving as the receiving end to obtain a restored input signal.
It should be noted that, if the first integrated chip is a transmitting end, the signal modulation unit of the first integrated chip generates a differential radio frequency signal at the P1 point and the P2 point of the first integrated chip, at this time, the signal demodulation unit of the first integrated chip demodulates the differential radio frequency signal, and meanwhile, the differential radio frequency signal is transmitted to the P1 point and the P2 point of the second integrated chip through the binding wire, and then the signal demodulation unit of the second integrated chip demodulates the differential radio frequency signal. The output level of the signal demodulation unit of the first integrated chip does not need to be processed, and the output end of the signal demodulation unit of the second integrated chip serving as the receiving end is connected with a processing device such as an inverter, so that a restored input signal can be obtained. The same applies when the second integrated chip is a transmitting end.
As shown in fig. 5, a signal waveform diagram of the high voltage isolator communication is shown.
Because the differential radio frequency signal needs to be transmitted from the integrated chip of the transmitting end to the integrated chip of the receiving end, a certain time delay exists between the waveform of the output signal and the waveform of the input signal, and the waveform of the input signal restored by the signal demodulation unit in the integrated chip of the transmitting end is basically the same as the waveform of the original input signal.
Therefore, the embodiment of the invention has at least the following beneficial effects:
(1) The inductance tap in the LC tank is grounded, which can significantly improve Common Mode Transient Immunity (CMTI).
(2) The differential radio frequency signal generating unit and the receiving unit are of an integrated structure, and the integrated chips on two sides are mutually resonant loads of the oscillator. The full-symmetrical structure can realize the consistency of the resonant frequencies of the integrated chips at two sides. After the signal modulation unit of one side of the integrated chip is driven, the other side of the integrated chip can be used as a resonant load to receive stable and reliable oscillation signals so as to realize signal transmission. The integrated chips at two sides can be used as a transmitting end or a receiving end of radio frequency signals to realize the duplex function.
(3) The differential radio frequency signal generating unit and the receiving unit are of an integrated structure, only one integrated chip is required to be produced, and the production cost caused by the fact that two chips of a transmitting end and a receiving end are required to be produced respectively is reduced.
As shown in fig. 6, the present embodiment further provides a high-voltage isolation method based on the high-voltage isolator of the present specification, the method including:
step 600, determining an integrated chip serving as a transmitting end and an integrated chip serving as a receiving end in the first integrated chip and the second integrated chip;
in step 606, the differential radio frequency signal is demodulated by using a signal demodulation unit in the integrated chip as the receiving end, so as to obtain a restored input signal.
In the embodiment of the present invention, the step of demodulating the differential radio frequency signal by using a signal demodulation unit in an integrated chip as a receiving end includes:
when the signal demodulation unit in the integrated chip serving as the receiving end does not receive the differential radio frequency signal, the signal demodulation unit outputs a high level;
when the signal demodulation unit in the integrated chip as the receiving end receives the differential radio frequency signal, the signal demodulation unit outputs a low level.
In this embodiment, when any one of the integrated chips is connected to an external current source to receive an input signal, the integrated chip that receives the input signal is used as a transmitting end of a radio frequency signal, a signal modulation unit in the integrated chip generates a differential radio frequency signal based on the input signal, and the differential radio frequency signal is coupled to T1 and T2 through an isolation capacitor C2 and an isolation capacitor C3 and then transmitted to ports T1 and T2 of the integrated chip that is used as a receiving end through a binding wire 1 and a binding wire 2. And demodulating the differential radio frequency signal by a signal demodulation unit in the integrated chip serving as the receiving end to obtain a restored input signal.
It should be noted that, not only in the embodiment, when the signal demodulation unit in the integrated chip as the receiving end does not receive the differential radio frequency signal, the signal demodulation unit outputs a high level; when the signal demodulation unit in the integrated chip as the receiving end receives the differential radio frequency signal, the signal demodulation unit outputs a low level. It is understood that the signal demodulation unit in the integrated chip serving as the receiving end may be configured to output a low level when the signal demodulation unit does not receive the differential radio frequency signal; when the signal demodulation unit in the integrated chip as the receiving end receives the differential radio frequency signal, the signal demodulation unit outputs a high level. As long as the signal demodulation unit can restore the input signal by the differential radio frequency signal generated by the signal modulation unit of the transmitting end.
It is noted that relational terms such as first and second, and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one …" does not exclude the presence of additional identical elements in a process, method, article or apparatus that comprises the element.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. An integrated chip for high voltage isolation, comprising: the device comprises two isolation capacitors, a signal modulation unit and a signal demodulation unit; the signal modulation unit and the signal demodulation unit are connected in parallel to form a parallel circuit, and the parallel circuit is connected in series between the two isolation capacitors;
when the input end of the parallel circuit is connected with an external current source to receive an input signal, the signal modulation unit generates differential radio frequency signals at two ends of the parallel circuit based on the input signal;
the signal demodulation unit is used for demodulating the differential radio frequency signals at two ends of the parallel circuit to obtain a restored input signal.
2. The integrated chip of claim 1, wherein the signal modulation unit comprises: the negative resistance module and the LC resonant circuit are connected in parallel with the negative resistance module; the LC resonant circuit comprises a capacitor C1, an inductor L1 and an inductor L2;
the inductor L1 and the inductor L2 are connected in series, and the capacitor C1 is connected in parallel to both ends of the inductor L1 and the inductor L2 connected in series.
3. The integrated chip of claim 2, wherein the negative resistance module comprises: a PMOS tube M1 and a PMOS tube M2;
the grid electrodes of the PMOS tube M1 and the PMOS tube M2 are respectively connected to two ends of the LC resonance loop;
the source electrode of the PMOS tube M1 is connected to the source electrode of the PMOS tube M2, and the drain electrode of the PMOS tube M2 is connected to a connecting line of the grid electrode of the PMOS tube M2 and the LC resonant circuit;
the drain electrode of the PMOS tube M2 is connected to the connection line of the grid electrode of the PMOS tube M1 and the LC resonant circuit.
4. The integrated chip of claim 2 or 3, wherein center taps of the inductor L1 and the inductor L2 are grounded.
5. The integrated chip of claim 1, wherein the signal demodulation unit comprises: the receiving module, the coupling capacitor C4 and the coupling capacitor C5; the coupling capacitor C4 and the coupling capacitor C5 are used for coupling differential radio frequency signals at two ends of the parallel circuit to the receiving module;
one end of the coupling capacitor C4 is connected to one output end of the signal modulation unit, and the other end of the coupling capacitor C4 is connected to the receiving module;
and one end of the coupling capacitor C5 is connected to the other output end of the signal modulation unit, and the other end of the coupling capacitor C5 is connected to the receiving module.
6. The integrated chip of claim 5, wherein the receiving module comprises: NMOS tube M3 and NMOS tube M4;
the grid electrode of the NMOS tube M3 is connected to the connecting line of the coupling capacitor C4 and the bias potential, the source electrode of the NMOS tube M3 is connected to the connecting line of the coupling capacitor C5 and the signal modulation unit, and the drain electrode of the NMOS tube M4 is connected with the drain electrode of the NMOS tube;
the gate of the NMOS tube M4 is connected to the connection line of the coupling capacitor C5 and the bias potential, and the source of the NMOS tube M4 is connected to the connection line of the coupling capacitor C4 and the signal modulation unit.
7. A high voltage isolator comprising: a first integrated chip and a second integrated chip identical to the first integrated chip; wherein the first and second integrated chips are the integrated chips of any one of claims 1-6;
a parallel circuit formed by connecting a signal modulation unit and a signal demodulation unit in the first integrated chip in parallel is connected between two isolation capacitors in series to form a first series circuit; a parallel circuit formed by connecting the signal modulation unit and the signal demodulation unit in parallel in the second integrated chip is connected in series between the two isolation capacitors to form a second series circuit; the first end of the first series circuit is connected with the second end of the second series circuit, and the second end of the first series circuit is connected with the first end of the second series circuit.
8. The high voltage isolator of claim 7, wherein,
when the first integrated chip is connected with an external current source to receive an input signal, the signal demodulation unit of the second integrated chip is connected with an output end to output a restored input signal;
when the second integrated chip is connected to an external current source to receive an input signal, the signal demodulation unit of the first integrated chip is connected with the output end to output a restored input signal.
9. A high-voltage isolation method based on the high-voltage isolator according to claim 7 or 8, comprising:
determining an integrated chip serving as a transmitting end and an integrated chip serving as a receiving end in the first integrated chip and the second integrated chip;
transmitting an input signal to an integrated chip serving as a transmitting end by using an external current source, and generating differential radio frequency signals at two ends of the parallel circuit in the integrated chip serving as the transmitting end according to the input signal by using a signal modulation unit in the integrated chip serving as the transmitting end;
transmitting the differential radio frequency signals to an integrated chip serving as a receiving end by using two isolation capacitors connected in series at two ends of the parallel circuit;
and demodulating the differential radio frequency signal by using a signal demodulation unit in an integrated chip serving as a receiving end to obtain a restored input signal.
10. The high voltage isolation method according to claim 9, wherein demodulating the differential radio frequency signal using a signal demodulation unit in an integrated chip as a receiving end, comprises:
when the signal demodulation unit in the integrated chip serving as the receiving end does not receive the differential radio frequency signal, the signal demodulation unit outputs a high level;
when the signal demodulation unit in the integrated chip as the receiving end receives the differential radio frequency signal, the signal demodulation unit outputs a low level.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211297302.0A CN116032307A (en) | 2022-10-21 | 2022-10-21 | Integrated chip for high-voltage isolation, high-voltage isolator and high-voltage isolation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211297302.0A CN116032307A (en) | 2022-10-21 | 2022-10-21 | Integrated chip for high-voltage isolation, high-voltage isolator and high-voltage isolation method |
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| Publication Number | Publication Date |
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| CN116032307A true CN116032307A (en) | 2023-04-28 |
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| CN202211297302.0A Pending CN116032307A (en) | 2022-10-21 | 2022-10-21 | Integrated chip for high-voltage isolation, high-voltage isolator and high-voltage isolation method |
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| Country | Link |
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| CN (1) | CN116032307A (en) |
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- 2022-10-21 CN CN202211297302.0A patent/CN116032307A/en active Pending
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