CN116028283A - Processor test system, method and device and readable storage medium - Google Patents
Processor test system, method and device and readable storage medium Download PDFInfo
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- CN116028283A CN116028283A CN202111239547.3A CN202111239547A CN116028283A CN 116028283 A CN116028283 A CN 116028283A CN 202111239547 A CN202111239547 A CN 202111239547A CN 116028283 A CN116028283 A CN 116028283A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention provides a processor test system, a method, a device and a readable storage medium, relating to the technical field of testing, wherein the processor test system comprises: the system comprises an upper computer, a plurality of main control boards and a plurality of core boards; the plurality of main control boards and the plurality of core boards are respectively connected with the upper computer network; each main control board is provided with a plurality of core boards; each core board is provided with a processor chip to be tested; the main control board is used for controlling the power supply of the core board and resetting, reading and displaying the in-place state and the working state of the core board and debugging the processor chip to be tested to remove faults according to the control command of the upper computer. The scheme of the invention can realize automatic testing of the mass processor and improve the resource utilization rate and the testing efficiency.
Description
Technical Field
The present invention relates to the field of testing technologies, and in particular, to a processor testing system, a processor testing method, a processor testing device, and a readable storage medium.
Background
In the prior art, the execution and verification of a test task of a processor chip carrying an operating system of the internet of things are basically finished by means of manual operation, and the process is based on a certain series of processor chips of a certain brand, development or testing personnel issue related specific commands to a development board carrying the processor chips through a computer connection serial port, and execute related test cases. However, the manual test operation and data statistics have low resource utilization rate, and the functional test and iterative optimization cannot be completed quickly, so that the number and the number of the support processors are limited even in the automatic test, and the test efficiency is greatly reduced.
Disclosure of Invention
An object of an embodiment of the present invention is to provide a processor test system, method, apparatus and readable storage medium, so as to solve the problem of low efficiency of an artificial test processor in the prior art.
To achieve the above object, an embodiment of the present invention provides a processor test system, including:
the system comprises an upper computer, a plurality of main control boards and a plurality of core boards;
the plurality of main control boards and the plurality of core boards are respectively connected with the upper computer network;
each main control board is provided with a plurality of core boards;
each core board is provided with a processor chip to be tested;
the main control board is used for controlling the power supply of the core board and resetting, reading and displaying the in-place state and the working state of the core board and debugging the processor chip to be tested to remove faults according to the control command of the upper computer.
Optionally, the system further comprises:
and the upper computer is connected with the plurality of main control boards and the plurality of core boards through the repeater in a network mode respectively.
Optionally, the main control board includes:
the device comprises a first circuit board, a switch chip, an Ethernet interface chip, a control chip and a power supply circuit, wherein the switch chip, the Ethernet interface chip, the control chip and the power supply circuit are arranged on the first circuit board;
The repeater is connected with the switch chip through the Ethernet interface chip in a network manner;
the power supply circuit is respectively connected with the switch chip and the control chip and is used for supplying power to the switch chip and the control chip;
the power supply circuit is also connected with the core board and is used for receiving a power supply control signal of the control chip and controlling the power supply and the reset of the core board.
Optionally, the main control board further includes:
the first network serial port transparent transmission chip is connected with the switch chip and the core board respectively;
the second network serial port transparent transmission chip is respectively connected with the switch chip and the control chip;
the power supply circuit is also connected with the first network serial port transparent transmission chip and the second network serial port transparent transmission chip and is used for supplying power to the first network serial port transparent transmission chip and the second network serial port transparent transmission chip.
Optionally, the main control board further includes:
and the indicating lamp circuit is respectively connected with the control chip and the core board and is used for indicating the power supply state and the working state of the control chip and the in-place state and the working state of the core board.
Optionally, the power supply circuit includes:
a first DC converter, a first power supply circuit and a second power supply circuit connected in parallel;
the first direct current converter is respectively connected with the first power supply circuit and the second power supply circuit and is used for converting input voltage into first voltage to supply power for the first power supply circuit and the second power supply circuit;
the first power supply circuit is used for converting the first voltage into a first preset voltage to supply power for the switch chip;
the first power supply circuit is used for converting the first voltage into a second voltage and supplying power to the control chip and the plurality of core boards.
Optionally, the power supply circuit further includes:
and the third power supply circuit is connected with the first direct current converter and is used for converting the first voltage into a second preset voltage to supply power for the first network serial port transparent transmission chip and the second network serial port transparent transmission chip.
Optionally, the first power supply circuit includes:
the second direct current converter, the first low-dropout linear voltage regulator and the third direct current converter are connected in parallel;
the second direct current converter, the first low dropout linear voltage regulator and the third direct current converter are respectively connected with the first direct current converter;
The second direct current converter is used for converting the first voltage into the second voltage and supplying power for the switch chip;
the first low dropout linear regulator is used for converting the first voltage into a third voltage to supply power for the switch chip;
the third direct current converter is used for converting the first voltage into a fourth voltage to supply power for the switch chip;
the voltage values of the first voltage, the second voltage, the third voltage and the fourth voltage are sequentially reduced.
Optionally, the second power supply circuit includes:
a plurality of second low dropout linear regulators connected to the first dc converter;
and the plurality of second low dropout linear regulators are connected in parallel and are used for converting the first voltage into the second voltage to supply power for the control chip and the core board.
Optionally, the third power supply circuit includes:
the second direct current converter and the fourth direct current converter are connected in parallel;
the second direct current converter and the fourth direct current converter are respectively connected with the first direct current converter;
the second direct current converter is used for converting the first voltage into the second voltage and supplying power to the first network serial port transparent transmission chip and the second network serial port transparent transmission chip;
The fourth direct current converter is used for converting the first voltage into a fifth voltage and supplying power to the first network serial port transparent transmission chip and the second network serial port transparent transmission chip.
Optionally, the main control board further includes:
the dial switch is arranged on the first circuit board and used for indicating the number of the main control board.
Optionally, the core board includes:
the memory comprises a second circuit board, a memory chip and a processing circuit;
the processor chip to be tested, the memory chip and the processing circuit are respectively arranged on the second circuit board;
and a plurality of target pins of the processor chip to be tested are connected with the processing circuit.
Optionally, the core board further comprises:
the general input/output port is arranged on the first circuit board and used for indicating the slot position number of the core board and is in circuit connection with the indication lamp of the main control board.
The embodiment of the invention also provides a processor testing method which is applied to the core board and comprises the following steps:
after receiving a serial port connection command sent by an upper computer, carrying out initialization setting;
after receiving a control command sent by the upper computer through the main control board, matching in preset control command information to obtain a target control command;
According to the target control command, controlling the processor chip to be tested to test;
the preset control command information includes: inquiring information of the main control board, inquiring upper state and working state, reading, writing and erasing at least one control command of a product serial number, powering up, powering down and resetting of the processor chip to be tested.
Optionally, after the testing according to the target control command, the method further includes:
and returning a test result to the upper computer.
Optionally, the method further comprises:
when any data input is acquired within a preset time length under the condition that the target control command is powered on or reset, entering an upgrading application command mode;
under the condition of entering the upgrade application command mode, matching is carried out in preset upgrade command information according to the received upgrade command, and a target upgrade command is obtained;
controlling the processor chip to be tested to execute the target upgrading command;
the preset upgrade order information includes: entering an application program mode, acquiring type information of a processor chip to be tested, acquiring description information of a command, resetting software, upgrading software, acquiring an upgrading application program software version number and acquiring at least one upgrading command of a core board number.
Optionally, in the case that the target upgrade command is upgrade software, the method further includes:
transmitting the upgrade file to an application program backup partition of the processor chip to be tested through a preset protocol;
judging whether the upgrade file is completely transmitted or not, and obtaining a judging result;
and acquiring prompt information of the upgrading result according to the judging result.
Optionally, when the judging result is that the upgrade file is completely transferred, the method further includes:
copying the upgrade file of the application program backup partition to the application program partition of the processor chip to be tested.
Optionally, according to the judging result, obtaining upgrade result prompt information includes:
when the judgment result is that the upgrade file is completely transmitted, the upgrade result prompt information is that the upgrade is successful;
and when the judgment result is that the upgrade file is not completely transmitted, the upgrade result prompt information is upgrade failure, and the old application program partition is restored.
Optionally, after obtaining the upgrade result prompt information according to the judgment result, the method further includes:
and returning to the upgrading application command mode.
The embodiment of the invention also provides a processor testing device, which comprises:
The setting module is used for carrying out initialization setting after receiving a serial port connection command sent by the upper computer;
the matching module is used for matching in preset control command information after receiving the control command sent by the upper computer through the main control board, so as to obtain a target control command;
the test module is used for controlling the processor chip to be tested to test according to the target control command;
the preset control command information includes: inquiring information of the main control board, inquiring upper state and working state, reading, writing and erasing at least one control command of a product serial number, powering up, powering down and resetting of the processor chip to be tested.
Optionally, the apparatus further comprises:
and the first return module is used for returning the test result to the upper computer.
Optionally, the apparatus further comprises:
the entry module is used for entering an upgrade application command mode when any data input is acquired within a preset duration under the condition that the target control command is power-on or reset;
the obtaining module is used for matching in preset upgrade command information according to the received upgrade command under the condition of entering the upgrade application command mode to obtain a target upgrade command;
The control module is used for controlling the processor chip to be tested to execute the target upgrading command;
the preset upgrade order information includes: entering an application program mode, acquiring type information of a processor chip to be tested, acquiring description information of a command, resetting software, upgrading software, acquiring an upgrading application program software version number and acquiring at least one upgrading command of a core board number.
Optionally, in the case that the target upgrade command is upgrade software, the apparatus further includes:
the transmission module is used for transmitting the upgrade file to the application program backup partition of the processor chip to be tested through a preset protocol;
the judging module is used for judging whether the upgrade file is completely transmitted or not and obtaining a judging result;
and the acquisition module is used for acquiring the upgrade result prompt information according to the judgment result.
Optionally, when the judging result is that the upgrade file is completely transmitted, the device further includes:
and the copying module is used for copying the upgrade file of the application program backup partition to the application program partition of the processor chip to be tested.
Optionally, the acquiring module is specifically configured to:
When the judgment result is that the upgrade file is completely transmitted, the upgrade result prompt information is that the upgrade is successful;
and when the judgment result is that the upgrade file is not completely transmitted, the upgrade result prompt information is upgrade failure, and the old application program partition is restored.
Optionally, the apparatus further comprises:
and the second return module is used for returning the upgrade application command mode.
The embodiment of the invention also provides a readable storage medium, wherein the readable storage medium stores a program, and the program realizes the processor testing method when being executed by a processor.
The technical scheme of the invention has at least the following beneficial effects:
in the above scheme, the processor test system includes: the system comprises an upper computer, a plurality of main control boards and a plurality of core boards; the plurality of main control boards and the plurality of core boards are respectively connected with the upper computer network; each main control board is provided with a plurality of core boards; each core board is provided with a processor chip to be tested; the main control board is used for controlling the power supply of the core board and resetting, reading and displaying the in-place state and the working state of the core board and debugging the processor chip to be tested to remove faults according to the control command of the upper computer, can rapidly complete the functional test and iterative optimization work of the processor, replaces manual test operation and data statistics, realizes the automatic test of the mass processor, and improves the resource utilization rate and the test efficiency.
Drawings
FIG. 1 is a schematic circuit diagram of a processor test system according to an embodiment of the invention;
fig. 2 is a schematic circuit diagram of a main control board according to an embodiment of the invention;
FIG. 3 is a topology diagram of a UART-over-Internet protocol of a processor test system according to an embodiment of the present invention;
FIG. 4 is a power topology of a power supply circuit according to an embodiment of the present invention;
FIG. 5 is a topology of power and reset of a core board according to an embodiment of the present invention;
fig. 6 is a software architecture diagram of a main control board according to an embodiment of the present invention;
FIG. 7 is a flow chart of a processor test method according to an embodiment of the invention;
FIG. 8 is a flowchart of a main control board according to an embodiment of the present invention;
FIG. 9 is a flowchart of an upgrade of a core board according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of a processor test apparatus according to an embodiment of the invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages to be solved more apparent, the following detailed description will be given with reference to the accompanying drawings and specific embodiments.
The embodiment of the invention provides a processor test system, a processor test method, a processor test device and a readable storage medium, aiming at the problem of low efficiency of manual test processors in the prior art.
As shown in fig. 1, an embodiment of the present invention provides a processor test system, including:
The system comprises an upper computer, a plurality of main control boards and a plurality of core boards; the main control board can be called a bottom board;
the plurality of main control boards and the plurality of core boards are respectively connected with the upper computer through an Ethernet network;
each main control board is provided with a plurality of core boards;
each core board is provided with a processor chip to be tested;
the main control board is used for controlling the power supply and the reset of the core board, reading and displaying the in-place state and the working state of the core board and debugging the processor chip to be tested to remove faults according to the control command of the upper computer.
The processor test system of the embodiment of the invention comprises: the system comprises an upper computer, a plurality of main control boards and a plurality of core boards; the plurality of main control boards and the plurality of core boards are respectively connected with an upper computer network; each main control board is provided with a plurality of core boards; each core board is provided with a processor chip to be tested; the main control board is used for controlling the power supply and the reset of the core board, reading and displaying the in-place state and the working state of the core board and debugging the processor chip to be tested to remove faults according to the control command of the upper computer, can rapidly complete the functional test and iterative optimization work of the processor, replaces manual test operation and data statistics, realizes the automatic test of the mass processor, and improves the resource utilization rate and the test efficiency.
It should be noted that, the processor test system of the embodiment of the invention may include 50 core boards, and each core board is provided with 20 processor chips to be tested, so that one set of processor test system may implement automatic test of 1000 processors, so as to integrate multiple sets of processor test system to implement mass processor test. And the core board can be compatible with different types of mass processor chips to be tested of different brands and different series, and realizes functions of power supply, serial port communication, reset and GPIO (General-purpose input/output) control.
The main control board controls the power supply, reset and display in-place state and working state of the core board, and realizes the related communication function of the upper computer and the core board.
It should be noted that the upper computer supports one-to-many simultaneous communication. It should be noted that, the platform end can also be adopted to replace an upper computer, a control command is sent at the platform end, the control command is transmitted to the core board in a wired or wireless mode, and relevant test cases and development iteration verification are executed; and the adaptation information of different processors is acquired at the platform end in real time, so that whether the operating system (for example, oneOS operating system) operates normally or not is rapidly judged, and the problem positioning and solving are facilitated.
In addition, considering the final application scenario and actual requirements of the processor test system according to the embodiment of the present invention, the design specification needs to meet the industrial level standard, so the design temperature range that the above device needs to meet is-40 ℃ to 85 ℃. The core board is connected with the main control board by PCIE (high-speed serial computer expansion bus standard) interface design, and related slots are required to meet fool-proof design and certain times of plugging.
Optionally, the method further comprises:
and the upper computer is respectively connected with the plurality of main control boards and the plurality of core boards in a network manner through the repeater.
It should be noted that, the repeater includes a router and a switch, and because the types of the processor chips to be tested are different, the communication concurrency between the upper computer and the core board needs to be satisfied, so that the upper computer realizes the UART port communication with the core board through the network port by adopting the repeater mode and the mode of converting the network port into UART (universal asynchronous receiver transmitter).
It should be noted that the IP address is designed in such a way that DHCP (dynamic host configuration protocol) is used to automatically allocate the IP address. The upper computer program of the upper computer or the platform end needs to modify the operation of the serial port into the operation of the IP address, and design and realize maintenance of the corresponding relation between the IP address and the core board.
Optionally, as shown in fig. 2, the main control board includes:
the first circuit board, and a switch chip, an Ethernet interface chip, a control chip (i.e. MCU) and a power supply circuit which are arranged on the first circuit board;
the repeater is connected with the switch chip through an Ethernet network through an Ethernet interface chip;
the power supply circuit is respectively connected with the switch chip and the control chip and is used for supplying power to the switch chip and the control chip; wherein, the operation voltage of the switch chip is 3.3V, 2.5V and 1.1V; the operating voltage of the control chip was 3.3V.
The power supply circuit is also connected with the core board and is used for receiving a power supply control signal of the control chip and controlling the power-on, power-off and reset of the core board. Wherein the operating voltage of the core plate is 3.3V.
Here, the first circuit board is made of a PCB (printed circuit board). The embodiment of the invention can adopt a switch chip with the model number of RTL8326B-CG and an Ethernet interface chip with the model number of RTL 8208L.
It should be noted that, the main control board is powered by a 12V dc power supply, and is powered by a dc power supply socket in fig. 2, and is connected to the ethernet network through a network connection socket with the model RJ 45.
Optionally, the main control board further includes:
The first network serial port transparent transmission chip is connected with the switch chip and the core board respectively;
the second network serial port transparent transmission chip is respectively connected with the switch chip and the control chip;
the power supply circuit is also connected with the first network serial port transparent transmission chip and the second network serial port transparent transmission chip and is used for providing power for the first network serial port transparent transmission chip and the second network serial port transparent transmission chip. Here, the operation voltages of the first network serial port transparent transmission chip and the second network serial port transparent transmission chip are 3.3V and 1.8V.
It should be noted that, in the embodiment of the present invention, the first network serial port transparent transmission chip and the second network serial port transparent transmission chip may both adopt a network serial port transparent transmission chip with a model number of CH9121, and convert multiple network ports of the switch into UART ports, and communicate with the core board.
Specifically, as shown in fig. 3, which is a topology diagram of converting a network port of the processor test system of the embodiment of the present invention into a UART, the switch chip is an ethernet switch chip, and an ethernet switch is designed to convert a plurality of network ports into UARTs, and communicate with a core board, so that a platform end is guaranteed to have enough ports and resources when connected with the processor test system of the embodiment of the present invention.
Optionally, the main control board further includes:
And the indicator lamp circuit is respectively connected with the control chip and the core board and used for indicating the power supply state and the working state of the control chip and the in-place state and the working state of the core board.
Specifically, the indicator light circuit includes: the main control board indicator lamp circuit is used for indicating the power state and the working state of the control chip, the core device is a main control board indicator lamp, an LED (light emitting diode) is adopted, the main control board indicator lamp circuit is a red-green double-color lamp, the red lamp indicates the power state of the control chip, and the green lamp indicates the working state of the control chip. The specific function is defined as follows:
the red light goes out: indicating the power state of the control chip as abnormal power;
the red light is normally on: indicating the power state of the control chip to be normal;
the green lamp is extinguished: indicating that the working state of the control chip is abnormal;
the green lamp blinks to indicate that the working state of the control chip is normal.
Further, the indicator light circuit further includes: the core board indicator lamp circuit is used for indicating the in-place state and the working state of the core board, the core device is a core board indicator lamp, an LED is adopted, the in-place state of the core board is indicated by a red lamp and a green lamp, and the working state of the core board is indicated by the green lamp. The specific function is defined as follows:
The red light goes out: indicating that the in-place status of the core plate is out of place;
the red light is normally on: indicating that the power state of the core plate is in place;
the green lamp does not flash: indicating that the working state of the core plate is abnormal;
the green light blinks to indicate that the working state of the core plate is normal.
Alternatively, as shown in fig. 4, the power supply circuit includes:
a first DC converter, a first power supply circuit and a second power supply circuit connected in parallel;
the first direct current converter is respectively connected with the first power supply circuit and the second power supply circuit and is used for converting the input voltage into a first voltage to supply power for the first power supply circuit and the second power supply circuit; the first power supply circuit is used for converting the first voltage into a first preset voltage to supply power for the switch chip;
the first power supply circuit is used for converting the first voltage into the second voltage and supplying power to the control chip and the plurality of core boards.
It should be noted that the power supply circuit supports 12V dc power input, i.e., the input voltage is 12V. In consideration of factors such as power consumption, efficiency and power stability, the 12V input voltage is converted into the 5V first voltage through the first direct current converter, and then the first voltage is subjected to voltage reduction through the first power supply circuit and the second power supply circuit to supply power to the switch chip, the control chip and the core board.
Wherein the first voltage is 5V and the second voltage is 3.3V.
Optionally, the power supply circuit further includes:
the third power supply circuit is connected with the first direct current converter and used for converting the first voltage into a second preset voltage and supplying power to the first network serial port transparent transmission chip and the second network serial port transparent transmission chip.
Here, the second preset voltage is 3.3V and 1.8V.
Optionally, the first power supply circuit includes:
the second direct current converter, the first low-dropout linear voltage regulator and the third direct current converter are connected in parallel;
the second direct current converter, the first low-dropout linear voltage regulator and the third direct current converter are respectively connected with the first direct current converter;
the second direct current converter is used for converting the first voltage into a second voltage and supplying power for the switch chip;
the first low dropout linear regulator is used for converting the first voltage into a third voltage to supply power for the switch chip;
the third direct current converter is used for converting the first voltage into a fourth voltage and supplying power for the switch chip;
the voltage values of the first voltage, the second voltage, the third voltage and the fourth voltage are sequentially reduced.
Here, the third voltage is 2.5V and the fourth voltage is 1.1V.
It should be noted that, the first voltage of 5V is reduced to the second voltage of 3.3V by the second dc converter to supply power to the switch chip; the first voltage of 5V is reduced to a third voltage of 2.5V by a first low dropout linear voltage regulator to be a switch chip; the first voltage of 5V is reduced to a fourth voltage of 1.1V through a third DC converter to supply power for the switch chip.
Optionally, the second power supply circuit includes:
a plurality of second low dropout linear regulators connected to the first dc converter;
the plurality of second low dropout linear regulators are connected in parallel and are used for converting the first voltage into the second voltage to supply power for the control chip and the core board.
It should be noted that, the number of the second low dropout linear regulators is equal to the sum of the number of the core boards and the number of the main control boards. The first voltage of 5V is reduced to the second voltage of 3.3V through the second low dropout linear voltage regulator to supply power for the core plate and the control chip.
Optionally, the third power supply circuit includes:
the second direct current converter and the fourth direct current converter are connected in parallel;
the second direct current converter and the fourth direct current converter are respectively connected with the first direct current converter;
the second direct current converter is used for converting the first voltage into the second voltage and supplying power to the first network serial port transparent transmission chip and the second network serial port transparent transmission chip;
the fourth direct current converter is used for converting the first voltage into a fifth voltage and supplying power for the first network serial port transparent transmission chip and the second network serial port transparent transmission chip.
Here, the fifth voltage is 1.8V.
It should be noted that, the first voltage of 5V is reduced to the second voltage of 3.3V by the second dc converter, and the second voltage is supplied to the first network serial port transparent transmission chip and the second network serial port transparent transmission chip; and the first voltage of 5V is reduced to a fifth voltage of 1.8V through a fourth direct current converter, and the fifth voltage is used for supplying power for the first network serial port transparent transmission chip and the second network serial port transparent transmission chip.
It should be noted that, as shown in fig. 5, the main control board may implement hard reset for each core board that is mounted, and may independently control the power supply of each core board.
Specifically, the reset pin of each core board is operated through the control chip of the main control board, so that the hard reset function of the core board is realized; and the power-on and power-off operation is realized on the power supply of each core board through the control chip of the main control board.
Optionally, the main control board further includes:
and the dial switch is arranged on the first circuit board and used for indicating the number of the main control board.
In order to effectively distinguish and manage different main control boards, an eight-bit dial switch is designed on the first main control board and used for identifying the number of the main control board. Wherein, the dial switch bit 1:0, identifying a 1 st set of processor test systems; the 1 st bit of the dial switch: 1, identifying a set 2 processor system; the numbers of the main control boards are distinguished by adopting binary numbers in the 2 nd to 8 th bits of the dial switch, and the number ranges are as follows: [ 0000001:010010 ],0000001 represents a No. 1 main control board, 0110010 represents a No. 50 main control board, and the corresponding information of the specific main control board numbers and dial switches is as follows in Table 1:
| dialing switch serial number | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
| No. 1 main control board of 1 set of system | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| … | … | … | … | … | … | … | … | … |
| No. 1 system 50 board | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 |
| System No. 1 plate of 2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| … | … | … | … | … | … | … | … | … |
| No. 2 system 50 plate | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 |
TABLE 1
Optionally, the core board comprises:
the memory comprises a second circuit board, a memory chip and a processing circuit;
the processor chip to be tested, the memory chip and the processing circuit are respectively arranged on the second circuit board;
the plurality of target pins of the processor chip to be tested are connected with the processing circuit.
Here, the second circuit board is made of a PCB. The storage chip is a nor flash (nonvolatile flash memory), so that enough resources are ensured to meet the execution requirements of serial port upgrading and test cases.
And according to the pin definition, jumping to target pins required by the test item, and connecting the target pins with a processing circuit.
It should be noted that, because the number of the types of the processor chips to be tested is more than 1000, the design of the processing circuit of the core board needs to make compatible designs for the processor chips to be tested packaged by the same brand, so that one processing circuit design is ensured to be compatible with multiple types of processors to be tested, and according to the pin definitions of the processor chips to be tested of different types, the schematic diagram of one core board and the design of the second circuit board are ensured to be compatible with the processor chips to be tested of multiple types by skipping and selecting the peripheral circuit design, thereby reducing the cost and improving the development efficiency.
Optionally, the core board further comprises:
and a general purpose input/output (GPIO) arranged on the first circuit board and used for indicating the slot position number of the core board and being in circuit connection with the indication lamp of the main control board.
Because 20 core boards can be tested simultaneously on one main control board, in order to effectively distinguish and manage different core boards, distinguishing and identifying are carried out through binary slot position numbers, the slot position numbers are controlled by five-bit GPIOs, and the relation of the slot position numbers of the core boards corresponding to the GPIOs is shown in the following table 2:
| GPIO name | GPIO0 | GPIO1 | GPIO5 | GPIO6 | GPIO7 |
| No. 1 slot | 0 | 0 | 0 | 0 | 1 |
| No. 2 slot | 0 | 0 | 0 | 1 | 0 |
| … | … | … | … | … | … |
| No. 20 slot | 1 | 0 | 1 | 0 | 0 |
TABLE 2
In summary, the processor test system of the embodiment of the invention can load the main control board and the core board in the chassis, and load a plurality of sets of processor test systems in one cabinet, and the power supply adopts an external power supply to supply power. The power supply and the reset pin of each core board are operated through communication with the upper computer or the platform end, the working state of each core board is simultaneously reported to the upper computer or the platform end, and the upper computer or the platform end can be directly communicated with the core board, upgrade the core board and the like. The main control board mainly controls the power supply and reset of the core board, reads and displays the working state of the core board, the number of the main control board and the slot number of the core board, and independently communicates with an upper computer or a platform end to debug the functions of debugging the processor chip to be tested, removing faults and the like.
As shown in fig. 6, a software architecture diagram of a main control board according to an embodiment of the present invention is shown, where the main control board software includes an upgrade application program and an application program, and is divided into an application layer, a bootloader (upgrade application) program, a driver layer, and an SDK (software development kit), where the application layer is used for information storage, hardware operation, status acquisition/reporting, and command storage/parsing; the bootloader program is used for upgrading the components, recovering the firmware and storing/analyzing the commands; the upgrade component is specifically used for firmware burning, analyzing firmware through a Ymodem (file transfer protocol) protocol and erasing the firmware; the driver layer includes FLASH driver, UART driver, TIME driver, and I/O driver.
As shown in fig. 7, an embodiment of the present invention further provides a processor testing method, including:
here, the processor test method of the embodiment of the present invention is applied to a core board, wherein the initialization setting includes timer initialization and I/O initialization.
Before receiving the control command, if any character input is obtained, the serial port is cached, and the control command is ready to be executed.
the preset control command information comprises: inquiring information of a main control board, inquiring upper state and working state, reading, writing and erasing at least one control command of a product Serial Number (SN), powering on, powering off and resetting of a processor chip to be tested.
Specifically, the preset control command information is shown in the following table 3:
TABLE 3 Table 3
Note that, the commands in table 3 above all use "\r\n" as the ending symbol, and the return format line feed is also "\r\n".
According to the embodiment of the invention, after the serial port connection command sent by the upper computer is received, initialization setting is carried out; after receiving a control command sent by the upper computer through the main control board, matching in preset control command information to obtain a target control command; and controlling the processor chip to be tested to test according to the target control command, realizing the automatic test of the processor and improving the development efficiency.
It should be noted that, the upgrading application program of the main control board and the workflow of the application program are similar to those of the core board, and here, the workflow of the main control board shown in fig. 8 is described as follows:
After starting, the serial port, the I/O and the timer are initialized;
judging whether a control command is input or not;
if a control command is input, matching a preset control command table (table 3), and judging whether a target control command is inquired;
if no control command is input, re-judging until the control command is input;
if the target control command is inquired, executing the control command task in the table 3;
if the target control command is the read SN, executing the read application program parameter partition product serial number;
if the target control command is the erasure SN, executing unlocking flash and erasing the serial number of the flash product; judging whether the flash is successfully erased, judging whether data is written when judging that the flash is successfully erased, writing data when judging that the data is written, and locking the flash when the data is judged that the data is successfully written; when flash erasing is unsuccessful or no data writing is judged, printing information;
if the target control command is reset, power-on and power-off, the corresponding core board is controlled to execute reset, power-on and power-off;
after executing the target control command task, printing information, wherein the information is a test result;
If the target control command is not queried, judging whether the search of the preset control command table is finished;
if the search is finished, the serial port cache is emptied, the control command is deleted, and the information is printed;
and if the search is not completed, re-matching the preset control command table.
Optionally, after the testing according to the target control command, the method further comprises:
and returning a test result to the upper computer.
Here, the test results are in the return format shown in table 3, for example, the control command function is to reset the core boards, the test results are the core board numbers (20 core boards are mounted on one main control board) and the corresponding reset results, "success" indicates successful reset, and "failed" indicates failed reset.
Optionally, the method further comprises:
under the condition that the target control command is power-on or reset, entering an upgrade application command mode when any data input is acquired within a preset duration;
under the condition of entering an upgrade application command mode, matching is carried out in preset upgrade command information according to a received upgrade command, and a target upgrade command is obtained;
controlling the processor chip to be tested to execute the target upgrading command;
the preset upgrade order information includes: entering an application program mode, acquiring type information of a processor chip to be tested, acquiring description information of a command, resetting software, upgrading software, acquiring an upgrading application program software version number and acquiring at least one upgrading command of a core board number.
Specifically, the preset upgrade order information is shown in the following table 4:
TABLE 4 Table 4
After the core board software is reset or powered on again, the default is started from the bootloader program, when any data input is obtained within the end of the countdown 6 seconds, the upgrading application command mode is entered, and if the App program exists, the App program is automatically entered; and returning to the bootloader program command mode if the App program does not exist.
Here, the upgrading process of the core board as shown in fig. 9 is explained as follows:
after starting, the serial port, the I/O and the timer are initialized;
judging whether any data is input within the end of the countdown 6 seconds;
if any data is input within the end of the countdown for 6 seconds, the serial port cache is emptied, and the execution command is prepared;
if no arbitrary data is input within the end of the countdown 6 seconds, judging whether an App program partition exists or not;
if the App program partition is judged to exist, the App program is jumped to;
if the App program partition is judged not to exist, the serial port cache is emptied, and an execution command is prepared;
after the serial port cache is emptied and the execution command is prepared, if an upgrade command is input, matching a preset upgrade command table (table 4) and judging whether a target upgrade command is queried;
If the target upgrading command is inquired, executing the upgrading command task in the table 4;
if the target upgrading command is upgrading software, requesting next frame data, and judging whether the data is legal or not when judging that the acquired data; further judging the first frame data, acquiring the due program name and size, and judging the last frame data; when the last frame of data is judged, the data is stored in a flash memory, and whether the data is successfully stored is judged;
if the target upgrade command is an enter App program command, the App program is executed when it is determined that the App program partition exists.
Executing an upgrade command task, and printing information, wherein the information is a test result;
if the target upgrading command is not queried, judging whether the preset upgrading command list is searched, and if so, clearing the serial port cache and deleting the upgrading command and printing information; if the searching is not finished, the preset upgrading command list is matched again.
Optionally, in the case that the target upgrade command is upgrade software, the method further includes:
transmitting the upgrade file to an application program backup partition of the processor chip to be tested through a preset protocol;
judging whether the upgrade file is completely transmitted or not, and obtaining a judging result;
And acquiring prompt information of the upgrading result according to the judging result.
It should be noted that, the preset protocol is a file transfer protocol, and here, a yomem protocol is adopted, which includes a start frame, a data frame and an end frame.
Wherein the start frame comprises: the frame header is denoted SOH, soh=0x01 indicates that 128 bytes of data are contained in this data frame; the data frame number is denoted as 0x00; the data frame reverse sequence number is denoted as 0xFF; the file name is denoted as filename, is the file name to be transmitted, and is added with 00 after the file name to indicate the end of the file name; the file size is denoted filesize, and the end is indicated by the last 00. An invalid value (null) is indicated as 0x00, i.e., 128 bytes of data are filled with 0x00 except for the file name and the remaining bytes occupied by the file size; the start frame also includes a 16-bit CRC (cyclic redundancy check) check code.
The data frame includes: the frame header is denoted as STX, stx=0x02 denotes that the frame of data is followed by a data portion containing 1024 bytes; the data frame number is 0x01/0x02 …, the data frame sequence number is 0xFE/0xFD,0x01 indicates the frame sequence number, 0xFE is the inverse thereof, the next frame data is 0x02,0xFD is the inverse thereof, and so on; the data is data [1024] representing file data storing 1024 bytes; the data frame also includes a 16-bit CRC check code.
Note that if the last remaining data of the file data is before 128 to 1024 bytes, 1024 bytes transmission using STX is also used, but the remaining space is entirely filled with 0x 1A.
If the file size is less than or equal to 128 bytes or the last remaining data of the file data is less than 128 bytes, the ymodem protocol selects the SOH data frame to transmit the data in 128 bytes, if the data does not satisfy 128 bytes, the remaining data is padded with 0x1A, and the structure of the data frame is:
the file size is less than 128 bytes: SOH 01FE data [ ]1 A..1A CRCH CRCL;
the last remaining data of the file is less than 128 bytes: SOH 01FE data [ ]1 A.1A CRCH CRCL.
The end frame includes: the frame header is denoted SOH, soh=0x01; the frame number is expressed as 0x01, and the frame number sequence number is 0xFE; the invalid value (null) 128 bytes are all padded with 0x 00.
It should be further noted that the overall situation of the processor chip to be tested (i.e., the MCU) is as follows:
external device address range: 0xA0000FFF-0xA0000000;
external RAM (external random access memory) address range: 0xA0000000-0x60000000;
peripheral address range: 0x60000000-0x40000000;
Reserved address range: 0x40000000-0x20018000;
SRAM (static random access memory) address range: 0x20018000-0x20000000;
wherein Reserved and SRAM are used as SRAM;
reserved address range: 0x20000000-0x1FFFF810;
option Bytes address range: 0x1FFFF810-0x1FFFF800;
bootloader address range: 0x1FFFF800-0x1FFF8000;
reserved address range: 0x1FFF8000-0x08300000;
main Flash (Main Flash) address range: 0x08300000-0x08000000;
reserved address range: 0x08000000-0x00300000;
main Flash or Bootloader (primary flash or upgrade application) address range: 0x00300000-0x00000000;
among them, reserved, option Bytes, bootloader, reserved, main Flash, reserved, and Main Flash or Bootloader are used as codes.
The user partition of the processor chip to be tested comprises:
app program parameters partition, address range: 0x08040000-0x0803F000, size 4k;
app procedure backup partition, address range: 0x0803F000-0x08023800, size 110k;
app program partition;
repositioning interrupt vector table and bootloader program parameter partition, size 110k;
bootloader program partition and interrupt vector table, size 30k;
bootloader program parameter partition, bootloader program partition, and address range of interrupt vector table: 0x08007800-0x08000000.
According to the setting parameters, the bootloader program occupies the first 32k positions of the Main Flash area.
The core board is powered on again or reset every time, the program starts from the Main Flash area, namely, the address of 0x08000000, and the program of the address is a bootloader program partition, so that the reset of the backseat after being powered on again every time can be ensured, and the program starts from the bootloader program partition.
Optionally, when the judging result is that the upgrade file is completely transmitted, the method further includes:
copying the upgrade file of the App program backup partition to the App program partition of the processor chip to be tested.
It should be noted that, when a user or a developer starts an upgrade process, that is, inputs an update command, the bootloader program waits for the transmission of an upgrade file (bin file); writing all the received bin file data packets into an App program backup partition; and when the bin file is judged to be completely transmitted, namely the bin file is completely transmitted to the local, copying the bin file of the App program backup partition to the App program partition.
And when the upgrade file transmission is incomplete as a judgment result, the upgrade file of the App program backup partition is not copied to the App program partition of the processor chip to be tested, the upgrade failure is dealt with, the old application program is ensured not to be covered, and the program can be ensured to normally run when the upgrade failure occurs.
It should be further noted that, during the upgrade process, if the upgrade is cancelled halfway (Q/Q is input, case is not distinguished) or the transmission process is abnormal, a failure may be caused, in which case, the program reports an error, which indicates that the upgrade fails, that is, the upgrade file is not completely transmitted.
Optionally, acquiring the upgrade result prompt information according to the judgment result includes:
when the judgment result is that the transmission of the upgrade file is complete, the upgrade result prompt information is that the upgrade is successful;
and when the judgment result is that the upgrade file is not transmitted completely, the upgrade result prompt information is that the upgrade fails, and the old application program partition is restored.
Optionally, after obtaining the upgrade result prompt information according to the judgment result, the method further includes:
and returning to the upgrading application command mode.
When the upgrade is successful or fails, the program returns to the upgrade application command mode to wait for the next control command.
As shown in fig. 10, an embodiment of the present invention further provides a processor testing apparatus, including:
the setting module 1001 is configured to perform initialization setting after receiving a serial port connection command sent by the upper computer;
the matching module 1002 is configured to match the control command information to obtain a target control command after receiving a control command sent by the host computer through the main control board;
The test module 1003 is configured to control the processor chip to be tested to perform a test according to the target control command;
the preset control command information comprises: inquiring information of the main control board, inquiring upper state and working state, reading, writing and erasing at least one control command of a product serial number, powering up, powering down and resetting of the processor chip to be tested.
According to the embodiment of the invention, after the serial port connection command sent by the upper computer is received, initialization setting is carried out; after receiving a control command sent by the upper computer through the main control board, matching in preset control command information to obtain a target control command; and controlling the processor chip to be tested to test according to the target control command, realizing the automatic test of the processor and improving the development efficiency.
Optionally, the apparatus further comprises:
the first return module is used for returning the test result to the upper computer.
Optionally, the apparatus further comprises:
the entry module is used for entering an upgrade application command mode when any data input is acquired within a preset duration under the condition that a target control command is powered on or reset;
the obtaining module is used for matching in preset upgrade command information according to the received upgrade command under the condition of entering an upgrade application command mode to obtain a target upgrade command;
The control module is used for controlling the processor chip to be tested to execute the target upgrading command;
the preset upgrade order information includes: entering an application program mode, acquiring type information of a processor chip to be tested, acquiring description information of a command, resetting software, upgrading software, acquiring an upgrading application program software version number and acquiring at least one upgrading command of a core board number.
Optionally, in the case that the target upgrade command is upgrade software, the apparatus further includes:
the transmission module is used for transmitting the upgrade file to the application program backup partition of the processor chip to be tested through a preset protocol;
the judging module is used for judging whether the upgrade file is completely transmitted or not and acquiring a judging result;
and the acquisition module is used for acquiring the prompt information of the upgrading result according to the judging result.
Optionally, when the judging result is that the upgrade file is completely transmitted, the device further includes:
and the copying module is used for copying the upgrade file of the application program backup partition to the application program partition of the processor chip to be tested.
Optionally, the obtaining module is specifically configured to:
when the judgment result is that the transmission of the upgrade file is complete, the upgrade result prompt information is that the upgrade is successful;
And when the judgment result is that the upgrade file is not transmitted completely, the upgrade result prompt information is that the upgrade fails, and the old application program partition is restored.
Optionally, the apparatus further comprises:
and the second return module is used for returning to the upgrade application command mode.
It should be noted that, the processor test device provided in the embodiment of the present invention is a device capable of executing the above-mentioned processor test method, and all embodiments of the above-mentioned processor test method are applicable to the device, and can achieve the same or similar technical effects.
The embodiment of the invention also provides a readable storage medium, wherein the readable storage medium stores a program, and the program realizes the processor testing method when being executed by a processor.
The readable storage medium includes a computer readable storage medium, such as a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk or an optical disk.
The exemplary embodiments described above are described with reference to the drawings, many different forms and embodiments are possible without departing from the spirit and teachings of the present invention, and therefore, the present invention should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the invention to those skilled in the art. In the drawings, the size of the elements and relative sizes may be exaggerated for clarity. The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Unless otherwise indicated, a range of values includes the upper and lower limits of the range and any subranges therebetween.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the present invention.
Claims (22)
1. A processor test system, comprising:
the system comprises an upper computer, a plurality of main control boards and a plurality of core boards;
the plurality of main control boards and the plurality of core boards are respectively connected with the upper computer network;
each main control board is provided with a plurality of core boards;
each core board is provided with a processor chip to be tested;
the main control board is used for controlling the power supply of the core board and resetting, reading and displaying the in-place state and the working state of the core board and debugging the processor chip to be tested to remove faults according to the control command of the upper computer.
2. The processor testing system of claim 1, further comprising:
and the upper computer is connected with the plurality of main control boards and the plurality of core boards through the repeater in a network mode respectively.
3. The processor testing system of claim 2, wherein said master control board comprises:
The device comprises a first circuit board, a switch chip, an Ethernet interface chip, a control chip and a power supply circuit, wherein the switch chip, the Ethernet interface chip, the control chip and the power supply circuit are arranged on the first circuit board;
the repeater is connected with the switch chip through the Ethernet interface chip in a network manner;
the power supply circuit is respectively connected with the switch chip and the control chip and is used for supplying power to the switch chip and the control chip;
the power supply circuit is also connected with the core board and is used for receiving a power supply control signal of the control chip and controlling the power supply and the reset of the core board.
4. The processor test system of claim 3, wherein the master control board further comprises:
the first network serial port transparent transmission chip is connected with the switch chip and the core board respectively;
the second network serial port transparent transmission chip is respectively connected with the switch chip and the control chip;
the power supply circuit is also connected with the first network serial port transparent transmission chip and the second network serial port transparent transmission chip and is used for supplying power to the first network serial port transparent transmission chip and the second network serial port transparent transmission chip.
5. The processor test system of claim 3, wherein the master control board further comprises:
And the indicating lamp circuit is respectively connected with the control chip and the core board and is used for indicating the power supply state and the working state of the control chip and the in-place state and the working state of the core board.
6. The processor testing system of claim 3, wherein said power supply circuit comprises:
a first DC converter, a first power supply circuit and a second power supply circuit connected in parallel;
the first direct current converter is respectively connected with the first power supply circuit and the second power supply circuit and is used for converting input voltage into first voltage to supply power for the first power supply circuit and the second power supply circuit;
the first power supply circuit is used for converting the first voltage into a first preset voltage to supply power for the switch chip;
the first power supply circuit is used for converting the first voltage into a second voltage and supplying power to the control chip and the plurality of core boards.
7. The processor testing system of claim 4, wherein said power supply circuit further comprises:
and the third power supply circuit is connected with the first direct current converter and is used for converting the first voltage into a second preset voltage to supply power for the first network serial port transparent transmission chip and the second network serial port transparent transmission chip.
8. The processor testing system of claim 6, wherein said first power supply circuit comprises:
the second direct current converter, the first low-dropout linear voltage regulator and the third direct current converter are connected in parallel;
the second direct current converter, the first low dropout linear voltage regulator and the third direct current converter are respectively connected with the first direct current converter;
the second direct current converter is used for converting the first voltage into the second voltage and supplying power for the switch chip;
the first low dropout linear regulator is used for converting the first voltage into a third voltage to supply power for the switch chip;
the third direct current converter is used for converting the first voltage into a fourth voltage to supply power for the switch chip;
the voltage values of the first voltage, the second voltage, the third voltage and the fourth voltage are sequentially reduced.
9. The processor testing system of claim 6, wherein said second power supply circuit comprises:
a plurality of second low dropout linear regulators connected to the first dc converter;
and the plurality of second low dropout linear regulators are connected in parallel and are used for converting the first voltage into the second voltage to supply power for the control chip and the core board.
10. The processor testing system of claim 7, wherein said third power supply circuit comprises:
the second direct current converter and the fourth direct current converter are connected in parallel;
the second direct current converter and the fourth direct current converter are respectively connected with the first direct current converter;
the second direct current converter is used for converting the first voltage into the second voltage and supplying power to the first network serial port transparent transmission chip and the second network serial port transparent transmission chip;
the fourth direct current converter is used for converting the first voltage into a fifth voltage and supplying power to the first network serial port transparent transmission chip and the second network serial port transparent transmission chip.
11. The processor test system of claim 3, wherein the master control board further comprises:
the dial switch is arranged on the first circuit board and used for indicating the number of the main control board.
12. The processor testing system of claim 1, wherein said core board comprises:
the memory comprises a second circuit board, a memory chip and a processing circuit;
the processor chip to be tested, the memory chip and the processing circuit are respectively arranged on the second circuit board;
And a plurality of target pins of the processor chip to be tested are connected with the processing circuit.
13. The processor testing system of claim 12, wherein said core board further comprises:
the general input/output port is arranged on the first circuit board and used for indicating the slot position number of the core board and is in circuit connection with the indication lamp of the main control board.
14. A method of processor testing, applied to a core board, comprising:
after receiving a serial port connection command sent by an upper computer, carrying out initialization setting;
after receiving a control command sent by the upper computer through the main control board, matching in preset control command information to obtain a target control command;
according to the target control command, controlling the processor chip to be tested to test;
the preset control command information includes: inquiring information of the main control board, inquiring upper state and working state, reading, writing and erasing at least one control command of a product serial number, powering up, powering down and resetting of the processor chip to be tested.
15. The processor test method of claim 14, further comprising, after performing the test according to the target control command:
And returning a test result to the upper computer.
16. The processor testing method of claim 14, further comprising:
when any data input is acquired within a preset time length under the condition that the target control command is powered on or reset, entering an upgrading application command mode;
under the condition of entering the upgrade application command mode, matching is carried out in preset upgrade command information according to the received upgrade command, and a target upgrade command is obtained;
controlling the processor chip to be tested to execute the target upgrading command;
the preset upgrade order information includes: entering an application program mode, acquiring type information of a processor chip to be tested, acquiring description information of a command, resetting software, upgrading software, acquiring an upgrading application program software version number and acquiring at least one upgrading command of a core board number.
17. The processor testing method of claim 16, wherein in the case where said target upgrade command is upgrade software, further comprising:
transmitting the upgrade file to an application program backup partition of the processor chip to be tested through a preset protocol;
judging whether the upgrade file is completely transmitted or not, and obtaining a judging result;
And acquiring prompt information of the upgrading result according to the judging result.
18. The processor testing method of claim 17, further comprising, when the determination is that the upgrade file transmission is complete:
copying the upgrade file of the application program backup partition to the application program partition of the processor chip to be tested.
19. The processor testing method of claim 17, wherein obtaining upgrade result prompt information according to the determination result comprises:
when the judgment result is that the upgrade file is completely transmitted, the upgrade result prompt information is that the upgrade is successful;
and when the judgment result is that the upgrade file is not completely transmitted, the upgrade result prompt information is upgrade failure, and the old application program partition is restored.
20. The processor testing method of claim 17, further comprising, after obtaining the upgrade result prompt message according to the determination result:
and returning to the upgrading application command mode.
21. A processor test apparatus, comprising:
the setting module is used for carrying out initialization setting after receiving a serial port connection command sent by the upper computer;
The matching module is used for matching in preset control command information after receiving the control command sent by the upper computer through the main control board, so as to obtain a target control command;
the test module is used for controlling the processor chip to be tested to test according to the target control command;
the preset control command information includes: inquiring information of the main control board, inquiring upper state and working state, reading, writing and erasing at least one control command of a product serial number, powering up, powering down and resetting of the processor chip to be tested.
22. A readable storage medium, characterized in that the readable storage medium has stored thereon a program, which when executed by a processor, implements the processor test method according to any of claims 14 to 20.
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