CN116027985A

CN116027985A - Method, device, equipment and medium for improving availability of NVMe accelerator

Info

Publication number: CN116027985A
Application number: CN202310110427.6A
Authority: CN
Inventors: 李树青; 王江; 孙华锦
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2023-02-10
Filing date: 2023-02-10
Publication date: 2023-04-28

Abstract

The invention provides a method, a device, equipment and a readable medium for improving availability of an NVMe accelerator, wherein the method comprises the following steps: reserving an unused IO queue for the CPU in the NVMe disk; in response to receiving an instruction for modifying the configuration of the NVMe accelerator, opening up a memory space for an IO queue reserved for the CPU; the method comprises the steps that unprocessed IO commands in an NVMe accelerator are sent to a CPU through a data channel, and the IO commands are sent to a disk for processing through an IO queue reserved for the CPU; in response to the NVMe accelerator configuration modification being completed, the NVMe accelerator is opened and the IO command is sent to the NVMe accelerator or the CPU for processing based on the validation code stored in the NVMe accelerator configuration register. By using the scheme of the invention, the dynamic closing, opening and dynamic resource adjustment of the NVMe accelerator can be realized, the dynamic change of the hardware environment and the user of the server can be adapted, the transmission of the disk IO command can be realized without interruption, and the high availability of the server is ensured.

Description

Method, device, equipment and medium for improving availability of NVMe accelerator

Technical Field

The present invention relates to the field of computers, and more particularly to a method, apparatus, device, and readable medium for improving the availability of NVMe accelerators.

Background

NVMe hard disks are increasingly being used in storage systems such as storage servers due to their excellent performance. Compared with the traditional HDD hard disk with SATA/SAS interfaces, the NVMe hard disk has a plurality of advantages. The NVMe hard disk can enable the storage system to break through the traditional performance bottleneck, so that the storage system is greatly improved, but at the same time, the performance quality is improved greatly, and new challenges are brought to the system design.

Servers generally require high availability, i.e. the service is not allowed to be interrupted. However, in some situations, such as when an error occurs in a disk or an accelerator, and when the number of users dynamically changes or the number of disks dynamically increases or decreases, it is necessary to dynamically adjust the allocation of accelerator resources, etc., it is unavoidable to turn off the hardware accelerator, and then change the configuration and turn on again. Since IO commands are handled by the hardware accelerator, service interruption is unavoidable.

Furthermore, a more serious problem is that hardware systems using NVMe accelerators tend to be complex and the pipeline depth is very deep. This means that after receiving an IO command from the server, the command needs to be disassembled into many steps and then executed in sequence. Thus, when a dynamic adjustment occurs to the hardware accelerator, not only will the new server IO processing during the adjustment period be affected, but also since the server IO that has been disassembled is likely to not be able to adapt to the adjusted hardware accelerator, then the shutdown action of the accelerator needs to wait for the disassembled server IO to be completed, which often requires a longer time, which further increases the time for service interruption.

Disclosure of Invention

In view of this, an object of the embodiments of the present invention is to provide a method, an apparatus, a device, and a readable medium for improving availability of an NVMe accelerator, by using the technical solution of the present invention, dynamic closing, opening, and dynamic resource adjustment of the NVMe accelerator can be implemented, dynamic changes of a server hardware environment and a user can be adapted, transmission of an IO command of a disk can be implemented without interruption, and high availability of the server is ensured.

Based on the above objects, an aspect of an embodiment of the present invention provides a method for improving availability of an NVMe accelerator, comprising the steps of:

reserving an unused IO queue for the CPU in the NVMe disk;

in response to receiving an instruction for modifying the configuration of the NVMe accelerator, opening up a memory space for an IO queue reserved for the CPU;

the method comprises the steps that unprocessed IO commands in an NVMe accelerator are sent to a CPU through a data channel, and the IO commands are sent to a disk for processing through an IO queue reserved for the CPU;

in response to the NVMe accelerator configuration modification being completed, the NVMe accelerator is opened and the IO command is sent to the NVMe accelerator or the CPU for processing based on the validation code stored in the NVMe accelerator configuration register.

According to one embodiment of the invention, reserving unused IO queues for a CPU in an NVMe disk comprises:

Responding to the fact that the maximum queue number of the NVMe magnetic disk is larger than a first preset value, reserving an unused IO queue for each CPU core;

in response to the maximum number of queues of the NVMe disk being smaller than a second preset value, distributing all IO queues to the NVMe accelerator, deleting one IO queue when the configuration of the NVMe accelerator is modified, and re-creating an unused IO queue for the CPU after the deletion is completed;

and in response to the maximum number of queues of the NVMe disk being smaller than the first preset value and larger than the second preset value, reserving an unused IO queue for the CPU.

According to one embodiment of the present invention, further comprising:

the operation state of the NVMe accelerator is classified into a normal operation state, a closing transition state, a closing state, and an opening transition state.

According to one embodiment of the present invention, sending an unprocessed IO command in the NVMe accelerator to the CPU through the data channel, and sending the IO command to the disk through an IO queue reserved for the CPU for processing includes:

switching the operation state of the NVMe accelerator to a closing transition state;

the NVMe accelerator internally records the execution state of each IO command issued to the disk and judges whether all IO commands receive IO responses;

In response to all receiving the IO responses, feeding back completion of IO command processing to the CPU;

suspending unprocessed IO commands in the NVMe accelerator, transferring the IO commands to the CPU through a data channel, recording the transfer reason as closing of the NVMe accelerator, and switching the running state of the NVMe accelerator into a closing state;

and issuing IO commands in the CPU to the disk for processing through an IO queue reserved for the CPU.

According to one embodiment of the present invention, further comprising:

and in response to the NVMe accelerator being in the closed state, forwarding all IO commands received by the NVMe accelerator to the CPU, and recording the reasons as the NVMe accelerator is closed.

According to one embodiment of the invention, in response to the NVMe accelerator configuration modification being completed, opening the NVMe accelerator and sending the IO command into the NVMe accelerator or the CPU for processing based on the validation code stored in the NVMe accelerator configuration register comprises:

switching an operational state of the NVMe accelerator to an open transitional state in response to completion of the NVMe accelerator configuration modification;

responding to the running state of the NVMe accelerator as an open transition state, storing the verification code into an NVMe accelerator configuration register, receiving an IO command issued by a system, and sending an unprocessed IO command in the CPU to the NVMe accelerator;

Responding to the received IO command by the NVMe accelerator, and dismantling the IO command to obtain a verification code of the IO command;

comparing the verification code of the IO command with the verification code in the NVMe accelerator configuration register;

responding to the verification code of the IO command to be the same as the verification code in the NVMe accelerator configuration register, and executing the received IO command;

and responding to the verification code of the IO command is different from the verification code in the NVMe accelerator configuration register, and handing over the IO command to the CPU for processing through the data channel.

According to one embodiment of the present invention, further comprising:

in response to the operational state of the NVMe accelerator being an open transition state, judging whether the configuration modification causes the operational environment to change;

in response to the change of the running environment caused by the configuration modification, reading out the value of the original verification code and adding 1 to form a new verification code, and writing the new verification code into an NVMe accelerator configuration register;

informing the chip system of the value of the new verification code;

in response to the configuration modification not causing a change in the operating environment, the verification code is not updated.

In another aspect of the embodiment of the present invention, there is also provided an apparatus for improving usability of an NVMe accelerator, the apparatus including:

the reservation module is configured to reserve unused IO queues for the CPU in the NVMe disk;

The configuration module is configured to open up a memory space for the IO queue reserved for the CPU in response to receiving an instruction for modifying the configuration of the NVMe accelerator;

the sending module is configured to send unprocessed IO commands in the NVMe accelerator to the CPU through a data channel, and send the IO commands to the disk for processing through an IO queue reserved for the CPU;

and the processing module is configured to open the NVMe accelerator and send IO commands to the NVMe accelerator or the CPU for processing based on the verification code stored in the NVMe accelerator configuration register in response to the completion of the configuration modification of the NVMe accelerator.

In another aspect of the embodiments of the present invention, there is also provided a computer apparatus including:

at least one processor; and

and a memory storing computer instructions executable on the processor, the instructions when executed by the processor performing the steps of any of the methods described above.

In another aspect of the embodiments of the present invention, there is also provided a computer-readable storage medium storing a computer program which, when executed by a processor, implements the steps of any of the methods described above.

The invention has the following beneficial technical effects: according to the method for improving the availability of the NVMe accelerator, the unused IO queues are reserved for the CPU in the NVMe disk; in response to receiving an instruction for modifying the configuration of the NVMe accelerator, opening up a memory space for an IO queue reserved for the CPU; the method comprises the steps that unprocessed IO commands in an NVMe accelerator are sent to a CPU through a data channel, and the IO commands are sent to a disk for processing through an IO queue reserved for the CPU; in response to the completion of configuration modification of the NVMe accelerator, the technical scheme of opening the NVMe accelerator and transmitting IO commands to the NVMe accelerator or the CPU for processing based on the verification code stored in the NVMe accelerator configuration register can realize dynamic closing, opening and dynamic resource adjustment of the NVMe accelerator, adapt to the dynamic changes of the hardware environment of the server and the user, realize uninterrupted transmission of disk IO commands and ensure high availability of the server.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention and that other embodiments may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic flow chart of a method of improving availability of an NVMe accelerator according to one embodiment of the present invention;

FIG. 2 is a schematic diagram of IO queue distribution in accordance with one embodiment of the present invention;

FIG. 3 is a schematic diagram of an operational state of an NVMe accelerator according to one embodiment of the present invention;

FIG. 4 is a schematic diagram of a data path associated with a captcha mechanism according to one embodiment of the present invention;

FIG. 5 is a schematic diagram of a verification code issuing only new IOs to hardware according to one embodiment of the invention;

FIG. 6 is a schematic diagram of an overall frame according to one embodiment of the invention;

FIG. 7 is a schematic diagram of an apparatus for improving availability of NVMe accelerator according to one embodiment of the present invention;

FIG. 8 is a schematic diagram of a computer device according to one embodiment of the invention;

fig. 9 is a schematic diagram of a computer-readable storage medium according to one embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings.

Based on the above object, a first aspect of the embodiments of the present invention proposes an embodiment of a method for improving availability of an NVMe accelerator. Fig. 1 shows a schematic flow chart of the method.

As shown in fig. 1, the method may include the steps of:

s1, reserving an unused IO queue for the CPU in the NVMe disk. If the maximum queue number of the NVMe disk is larger than a first preset value, an unused IO queue is reserved for each CPU core, if the CPU core is a single-core CPU, a plurality of unused IO queues can be reserved, if the maximum queue number of the NVMe disk is smaller than a second preset value, all IO queues are distributed to the NVMe accelerator, one IO queue is deleted when the configuration of the NVMe accelerator is modified, and an unused IO queue is re-created for the CPU after the deletion is completed, if the maximum queue number of the NVMe disk is smaller than the first preset value and larger than the second preset value, no matter whether the CPU core or the CPU core is only reserved for the CPU, the reserved IO queues do not open up memory space, so that the use of memory is saved, and the memory space of the reserved queue is only when needed.

S2, responding to the received instruction for modifying the configuration of the NVMe accelerator, and opening up a memory space for the IO queue reserved for the CPU. The normal working state CPU can not open up memory space for the reserved IO queues so as to save the use of the memory. The CPU only opens up a memory space for an IO command queue managed by the hardware accelerator (the IO response queue is generally in the hardware accelerator, if the IO response queue is placed in a memory, the CPU also needs to open up the memory space, and the CPU belongs to the implementation details of the accelerator, does not influence the implementation of the invention and is not in the discussion scope of the invention), and issues an IO queue creation command to a disk through the management command queue and completes the binding with the memory space.

S3, sending the unprocessed IO command in the NVMe accelerator to the CPU through a data channel, and sending the IO command to the disk for processing through an IO queue reserved for the CPU.

And S4, responding to the completion of the configuration modification of the NVMe accelerator, opening the NVMe accelerator and sending the IO command to the NVMe accelerator or the CPU for processing based on the verification code stored in the configuration register of the NVMe accelerator. The captcha is a binary code of several bits (minimum 1 bit), the bit width being related to the turn-off/turn-on frequency and the system ending time, the greater the bit width required when the frequency is higher or the system ending time is longer. The verification code is stored in two places, one is in a configuration register of the NVMe accelerator, and the other is in an IO command sent to the NVMe accelerator after the system disassembles the IO command from the server. Every time an IO command is received by the NVMe accelerator, the two verification codes need to be compared, if the two verification codes are the same, the NVMe accelerator processes, and if the two verification codes are different, the two verification codes are processed by the CPU.

In the invention, the IO command of the NVMe disk is processed by the NVMe accelerator and the CPU, and the IO command processed by the CPU and the NVMe accelerator belong to the same NVMe disk. When the system works normally, all disk IO commands are processed by the NVMe accelerator so as to achieve the highest disk read-write performance, and when other systems, such as closing/modifying/opening the NVMe accelerator in the condition of needing to modify the hardware configuration of the accelerator, a stage of jointly processing the disk IO commands by the CPU and the NVMe accelerator or independently processing the disk IO commands by the CPU, occurs. The on/off of the NVMe accelerator or the dynamic adjustment of NVMe accelerator resources and other operations can realize uninterrupted issuing of IO commands to the disk.

The verification code mechanism is adopted to realize the rapid execution of the flow without waiting for completion of the IO execution of the disassembled server. The main advantages of the invention compared with the traditional implementation are:

1. a set of hardware and software cooperative mechanism is designed, so that the dynamic closing/opening and dynamic resource adjustment of the NVMe accelerator can be realized, and the dynamic change of a server hardware environment/user and the like can be adapted.

2. In the dynamic adjustment process, the method can realize the uninterrupted sending of the disk IO command and ensure the high availability of the server.

By using the technical scheme of the invention, the dynamic closing, opening and dynamic resource adjustment of the NVMe accelerator can be realized, the dynamic change of the hardware environment and the user of the server can be adapted, the transmission of the disk IO command can be realized without interruption, and the high availability of the server is ensured.

In a preferred embodiment of the present invention, reserving unused IO queues in the NVMe disk for the CPU comprises:

And in response to the maximum number of queues of the NVMe disk being smaller than the first preset value and larger than the second preset value, reserving an unused IO queue for the CPU. And reserving a temporary unused IO queue in the NVMe disk, namely assuming that one NVMe disk supports at most n IO queues, only using n-1 queues for the NVMe accelerator, and leaving the other queue temporarily unused. To achieve this, the CPU may create n-1 IO command queues and IO response queues only for the NVMe disk and inform the NVMe accelerator of only doorbell registers (hereinafter collectively referred to as IO doorbell registers) of the n-1 IO command queues and IO response queues when performing an operation of creating the IO command queues (using the management command queues). Because the accelerator with the cooperation of software and hardware needs to work depending on the configuration information issued by the CPU, the accelerator with the NVMe can only obtain doorbell register addresses of n-1 IO queues under the above operation, so that the accelerator with the cooperation of software and hardware can only operate on the n-1 IO queues, as shown in fig. 2.

Considering the performance of the transition stage, the method can be generalized, that is, under the condition that the maximum number of queues of the NVMe disk is relatively surplus, that is, the number is larger than a first preset value, more IO command queues and IO response queues can be reserved for the CPU. In the case of a multi-core CPU, a method of reserving one queue per CPU core may be generally adopted.

If the maximum number of queues of the NVMe disk is small, that is, the number is smaller than the second preset value, all the IO queues may be allocated to the NVMe accelerator in order to ensure normal IO performance. In the transition stage, the CPU pauses one of the IO queues by performing handshake with the NVMe accelerator, issues an IO queue delete command by managing the command queue, then issues a recreate IO queue create command and directs the queue to a memory space managed by the CPU.

In a preferred embodiment of the present invention, further comprising:

the operation state of the NVMe accelerator is classified into a normal operation state, a closing transition state, a closing state, and an opening transition state. As shown in fig. 3, the operation state of the NVMe accelerator is divided into four states of a normal operation state, a closed transition state, a closed state, and an open transition state. In order to realize dynamic change of the configuration of the NVMe accelerator, after receiving the request, the CPU switches the running state to a closed transition state, in which the ending work of the NVMe accelerator and the ending work of the whole chip system using the accelerator are executed, the running state is switched to the closed state after the ending is completed, the hardware configuration can be modified in the state, in which the running state is switched to an open transition state after the modification is completed, in which a new server IO command is submitted to the NVMe accelerator for processing, the CPU also submits the received but unprocessed IO command to the NVMe accelerator, and the normal working state is entered again after the handover is completed.

In a preferred embodiment of the present invention, sending an unprocessed IO command in the NVMe accelerator to the CPU through the data channel, and sending the IO command to the disk through an IO queue reserved for the CPU for processing includes:

The above steps are the ending work required by the NVMe accelerator, and the closing of the NVMe accelerator usually requires a relatively long time, so the task of ending needs to be processed inside the NVMe accelerator, and the following three main types of ending work need to be processed:

1, an NVMe accelerator is issued to a disk and waits for a command of the disk to return a result;

2. A command that has been issued to the NVMe accelerator, is being processed or has not begun to be processed, and has not been issued to the disk by the NVMe accelerator;

3. the system-on-chip has completed command parsing and has not issued commands to the NVMe accelerator in the pipeline.

For the first problem, the NVMe accelerator needs to increase handshake signals with the CPU. When the NVMe accelerator needs to be turned off, the CPU first sends a turn-off request to the NVMe accelerator. The NVMe accelerator needs to record the execution state of each IO issued to the disk, and after receiving the request, judges whether all IO commands receive IO responses. If all the signals are received, the closing completion is fed back to the CPU.

For the second problem, a data channel needs to be added between the NVMe accelerator and the CPU for the NVMe accelerator to send IO commands to the CPU. When the NVMe accelerator receives the shutdown request, the execution may be stopped for a command that has not been issued to the disk, and then the command is handed over to the CPU through the data channel, and the reason for the handover is recorded as because the NVMe accelerator is shut down. After receiving the command, the CPU issues the command to the disk through an IO command queue managed by the CPU.

For the third problem, after receiving the shutdown request, the NVMe accelerator does not execute for the newly received IO command, but hands over the command to the CPU through the data channel, and records the reason for the handover as because the NVMe accelerator is shutdown. After receiving the command, the CPU issues the command to the disk through an IO command queue managed by the CPU.

After implementing the method, the chip system can still receive new IO commands from the server, the new IO commands are processed by the CPU, the IO commands received from the server before are not affected, and the IO commands are shunted from the NVMe accelerator to the CPU for execution, so that the process is not even perceived to occur from the perspective of the server.

In a preferred embodiment of the present invention, further comprising:

and in response to the NVMe accelerator being in the closed state, forwarding all IO commands received by the NVMe accelerator to the CPU, and recording the reasons as the NVMe accelerator is closed. After a period of time, after the NVMe accelerator has received all IO responses sent by the disk, the CPU is notified of closing completion, and then the running state enters the closing state. In the off state, the NVMe accelerator may continue to receive IO commands from the chip system because entering the off state does not need to wait for the chip system to dispatch all parsed but unassigned tasks to completion, which would greatly extend the time to turn off the transitional state due to the typically very deep pipeline depth of the chip tasks, and often requires more complex detection and judgment logic. Thus, in the closed state of the NVMe accelerator, the open state of the data path from the command input channel to the CPU is maintained and all received IO commands are forwarded to the CPU, the reason being identified as hardware engine shutdown.

In a preferred embodiment of the present invention, in response to the NVMe accelerator configuration modification being completed, opening the NVMe accelerator and sending the IO command into the NVMe accelerator or the CPU for processing based on the validation code stored in the NVMe accelerator configuration register comprises:

Under the closed state, the CPU changes the configuration parameters of the hardware acceleration engine, and after the change is finished, the CPU re-opens the hardware acceleration engine, informs the NVMe accelerator of the chip system that a new IO command can be processed, and switches the running state into an open transition state. It should be noted that, some modifications to the configuration parameters of the hardware acceleration engine will not cause a change in the operating environment, i.e. the modified hardware acceleration engine may still execute the IO command received from the server before modification; some may cause a change in the operating environment, for example, modifying the binding between the hardware acceleration engine and the disk, which may result in the re-opened hardware acceleration engine not being able to execute these "original" IO commands. To address the problem of operational changes, the present invention introduces a "captcha" mechanism. The captcha is a binary code of several bits (minimum 1 bit), the bit width being related to the turn-off/turn-on frequency and the system ending time, the greater the bit width required when the frequency is higher or the system ending time is longer. The verification code is stored in two places, one is in a configuration register of the NVMe accelerator, and the other is in an IO command sent to the NVMe accelerator after the system disassembles the IO command from the server. Every time an NVMe accelerator receives an IO command, the verification code of the IO command and the verification code of the self configuration register need to be compared, if the verification code is the same, the IO command can be executed, and if the verification code is different, the verification code is transferred to the CPU for processing through a data channel with the CPU. As shown in fig. 4, fig. 4 illustrates only the data path related to the captcha mechanism, and does not illustrate all paths of the system.

In a preferred embodiment of the present invention, further comprising:

informing the chip system of the value of the new verification code;

When the CPU switches the running state from the off state to the on transition state, it will be determined that if the configuration modification at this time will cause the running environment to change, the CPU first changes the verification code of the NVMe accelerator, and the simplest rule is to read out the value of the original verification code register, add 1, and then write the value into the verification code register, as shown in fig. 5. Then, the CPU informs the chip system of the environmental parameters of the chip system that need to be synchronized before the new IO command can be processed by the NVMe accelerator of the chip system, and informs the chip system of the value of the aforementioned new verification code. After receiving the new server IO command, the chip system disassembles the IO command according to the new environment parameters, and configures the verification code of the IO command to be issued to the NVMe accelerator after disassembling as a new verification code. If the configuration modification does not cause the change of the running environment, the NVMe accelerator and the chip system can both keep the original verification code.

Considering that an NVMe accelerator generally has better performance, the present invention proposes that the CPU should try to hand over the IO command to the NVMe accelerator for processing after the NVMe accelerator is turned back on. To achieve the handover of the CPU to the NVMe accelerator, a data channel from the CPU to the NVMe accelerator needs to be added, as shown in fig. 6.

When the hardware engine is re-opened, there will be a plurality of IO commands in the system, for example, the chip disassembles the IO commands of the "old" environment to be distributed to the hardware, the IO commands of the "new" environment to be distributed to the hardware, the IO commands of the "old" environment to be distributed to the CPU, the IO commands of the "old" environment to be executed received by the CPU from the chip system, the IO commands received by the CPU from the NVMe accelerator, the IO commands of the hardware which have been handed over but do not reach the CPU, and the like, and the above IO commands need to be properly processed in the opening transition state, so that the process is a very complex and error-prone process.

The invention provides IO processing according to the following principle:

the CPU compares the verification code in the IO command received from the chip system with the new verification of the NVMe accelerator, if the verification code is the same with the new verification of the NVMe accelerator, the verification code is handed over to the NVMe accelerator, and if the verification code is not the same with the new verification of the NVMe accelerator, the verification code is executed by the CPU;

2, the CPU judges the reason of the handover according to the command received from the NVMe accelerator, if the accelerator is in the closing transition or closing state, the verification code of the IO command is judged to be the same as the new verification code, if the verification code is the same as the new verification code, the IO command is handed over to the NVMe accelerator again, and if the verification code is not the same, the IO command is executed by the CPU; if the reason for the handover is because the verification codes do not match, then it is executed by the CPU;

The NVMe accelerator compares the verification codes of the IO commands received from the system, if the IO commands are identical, the IO commands are executed, if the IO commands are not identical, the IO commands are transferred to the CPU, and the transfer reasons are marked as verification codes not identical;

the NVMe accelerator still needs to compare verification codes for IO commands received from the CPU, if the IO commands are identical, the verification codes are executed, if the IO commands are not identical, the transfer is carried out to the CPU, and the transfer reason is marked as the verification codes are not identical.

The end flag of the open transition state is not clear, because the various IO command types in the aforementioned system are very numerous, tracking and counting each type of IO command is a viable way, but the resource cost may be relatively large. Therefore, the invention adopts a simple mode, namely, the CPU can distribute a verification code which is different from that of the first time and the second time after the CPU is opened again after the CPU enters the closed transition state and can also receive the request to enter the closed transition state in the open transition state. Thus, in the new open transition state, it may happen that the CPU hands over to the NVMe accelerator, but the IO command not processed by the NVMe accelerator is the second IO command, i.e. not the same IO command as the current authentication code. This is why the above-mentioned NVMe accelerator still needs to compare when it receives the IO command of the CPU handover. From the time the request for switching to the off transition state is received to the time the system is operating stably in the normal operating state, as it was, there is no clear time boundary. The invention indicates that a very conservative time can be set, which must ensure that the system operates again stably. This time is called the minimum switching time. The CPU then needs to maintain a table, each entry in the table corresponding to a verification code, and record the time at which the verification code was submitted for a shutdown request. After receiving the closing request, the CPU needs to calculate the target verification code first, then take out the time value according to the target verification code, add the minimum switching time to the time value to obtain the earliest switching time, compare the current time with the earliest switching time, if the current time is smaller than the value, wait until the current time is larger than or equal to the value. After the method is implemented, for a system with larger minimum switching time and incapability of directly meeting the opening/closing frequency, the system can be solved by increasing the bit width of the verification code.

It should be noted that, it will be understood by those skilled in the art that all or part of the procedures in implementing the methods of the above embodiments may be implemented by a computer program to instruct related hardware, and the above program may be stored in a computer readable storage medium, and the program may include the procedures of the embodiments of the above methods when executed. Wherein the storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), or the like. The computer program embodiments described above may achieve the same or similar effects as any of the method embodiments described above.

Furthermore, the method disclosed according to the embodiment of the present invention may also be implemented as a computer program executed by a CPU, which may be stored in a computer-readable storage medium. When executed by a CPU, performs the functions defined above in the methods disclosed in the embodiments of the present invention.

In view of the above object, a second aspect of the embodiments of the present invention proposes an apparatus for improving availability of an NVMe accelerator, as shown in fig. 7, the apparatus 200 includes:

Based on the above object, a third aspect of the embodiments of the present invention proposes a computer device. FIG. 8 is a schematic diagram of an embodiment of a computer device provided by the present invention. As shown in fig. 8, an embodiment of the present invention includes the following means: at least one processor 21; and a memory 22, the memory 22 storing computer instructions 23 executable on the processor, the instructions when executed by the processor performing the method of:

Reserving an unused IO queue for the CPU in the NVMe disk;

In a preferred embodiment of the present invention, further comprising:

informing the chip system of the value of the new verification code;

Based on the above object, a fourth aspect of the embodiments of the present invention proposes a computer-readable storage medium. Fig. 9 is a schematic diagram showing an embodiment of a computer-readable storage medium provided by the present invention. As shown in fig. 9, the computer-readable storage medium 31 stores a computer program 32 that, when executed by a processor, performs the following method:

reserving an unused IO queue for the CPU in the NVMe disk;

In a preferred embodiment of the present invention, further comprising:

informing the chip system of the value of the new verification code;

Furthermore, the method disclosed according to the embodiment of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. The above-described functions defined in the methods disclosed in the embodiments of the present invention are performed when the computer program is executed by a processor.

Furthermore, the above-described method steps and system units may also be implemented using a controller and a computer-readable storage medium storing a computer program for causing the controller to implement the above-described steps or unit functions.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general purpose or special purpose computer or general purpose or special purpose processor. Further, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

It should be understood that as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

The foregoing embodiment of the present invention has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, and the program may be stored in a computer readable storage medium, where the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the invention, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the invention, and many other variations of the different aspects of the embodiments of the invention as described above exist, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present invention.

Claims

1. A method for improving the availability of an NVMe accelerator, comprising the steps of:

reserving an unused IO queue for the CPU in the NVMe disk;

2. The method of claim 1, wherein reserving unused IO queues in the NVMe disk for the CPU comprises:

3. The method as recited in claim 1, further comprising:

4. The method of claim 3, wherein sending the unprocessed IO commands in the NVMe accelerator to the CPU through the data channel, and sending the IO commands to the disk for processing through the IO queue reserved for the CPU comprises:

5. The method as recited in claim 4, further comprising:

6. The method of claim 1, wherein in response to completion of the NVMe accelerator configuration modification, opening the NVMe accelerator and sending the IO command into the NVMe accelerator or the CPU for processing based on the validation code stored in the NVMe accelerator configuration register comprises:

7. The method as recited in claim 6, further comprising:

informing the chip system of the value of the new verification code;

8. An apparatus for improving availability of an NVMe accelerator, the apparatus comprising:

and the processing module is configured to open the NVMe accelerator and send IO commands to the NVMe accelerator or the CPU for processing based on the verification code stored in the NVMe accelerator configuration register in response to the completion of the NVMe accelerator configuration modification.

9. A computer device, comprising:

at least one processor; and

a memory storing computer instructions executable on the processor, which when executed by the processor, perform the steps of the method of any one of claims 1-7.

10. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the steps of the method of any one of claims 1-7.