CN116017066A

CN116017066A - Display system and reference monitor

Info

Publication number: CN116017066A
Application number: CN202211551802.2A
Authority: CN
Inventors: 夏建龙; 王伟
Original assignee: Qingdao Xinxin Microelectronics Technology Co Ltd
Current assignee: Qingdao Xinxin Microelectronics Technology Co Ltd
Priority date: 2022-12-05
Filing date: 2022-12-05
Publication date: 2023-04-25

Abstract

The application discloses a display system and a reference monitor, which are used for shortening the starting time of an 8K reference monitor. The system comprises: the signal switching board is used for receiving video data and converting the video data from an SDI signal to an HDMI signal; the first FPGA receives the HDMI video signal and analyzes the HDMI video signal into a digital signal, and sends the digital signal to a display screen for display after image processing is performed on the digital signal; FLASH, store the netlist program of the second FPGA, first netlist that the first FPGA needs to be configured under the functional mode, first FPGA needs to be configured under the second functional mode second netlist; the data size of the first netlist is smaller than the data size of the second netlist; when the computer is started, the first FPGA enters a first functional mode; the second FPGA is used for switching the system into a FLASH starting mode, and entering a working state by loading a netlist program after the system is electrified; in the functional mode, a first netlist is configured for the first FPGA, and in the functional mode II, a second netlist is configured for the first FPGA.

Description

Display system and reference monitor

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display system and a reference monitor.

Background

In order to improve the display effect of images or videos, a reference monitor is gradually proposed in the prior art, and is different from a common display, and the reference monitor has extremely strict requirements on brightness, contrast, color gamut, product reliability and the like, and is the basis for professional people to measure, judge and decide images. Therefore, the reference monitor is also known in the industry as a "Miyuan device" in the field of image quality, and is a single-rod image quality scale. Some of these already exist that support a full screen range of brightness up to 1000 nits, no less than 100000:1, a reference monitor capable of perfectly restoring the content of video signals of 4K and high dynamic range (High Dynamic Range Imaging, HDR).

Disclosure of Invention

The embodiment of the application provides a display system and a reference monitor, which are used for improving the data processing speed through two FPGAs, realizing that the reference monitor rapidly displays complex 8K images, and simultaneously accelerating the starting-up speed through adopting a smaller netlist, thereby shortening the starting-up time of the 8K reference monitor.

In a first aspect, an embodiment of the present application provides a display system, including:

the signal switching board is used for receiving video data sent by the input device, converting the video data from a digital component serial interface SDI signal to a high-definition multimedia interface HDMI signal and then sending the signal to the first FPGA;

The first FPGA is used for receiving the HDMI video signal sent by the signal adapter plate, analyzing the HDMI video signal into a digital signal, performing image processing on the digital signal, and sending the digital signal to a display screen for display;

the FLASH is used for storing a netlist program of the second FPGA, a first netlist required to be configured by the first FPGA in a preset functional mode and a second netlist required to be configured by the first FPGA in a preset functional mode II; wherein the data size of the first netlist is smaller than the data size of the second netlist; when the computer is started, the first FPGA enters the first functional mode;

the second FPGA is used for switching the system to a FLASH starting mode, and entering a working state by loading the netlist program after the system is powered on; and in the functional mode, the first netlist is configured for the first FPGA, and in the functional mode II, the second netlist is configured for the first FPGA.

According to the embodiment of the application, the data processing speed is improved by arranging the two FPGAs, the reference monitor is enabled to rapidly display complex 8K images, and the system is enabled to be started by adopting the smaller first netlist, so that the starting speed is increased, and the starting time of the 8K reference monitor is shortened.

In a second aspect, an embodiment of the present application provides a reference monitor, including the display system.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is an application scenario schematic diagram of a reference monitor provided in an embodiment of the present application;

FIG. 2 is a schematic diagram of a prior art 4K reference monitor;

FIG. 3 is a schematic diagram of an overall frame structure of a display system according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a display system in a functional mode according to an embodiment of the present application;

fig. 5 is a schematic diagram of a display system upgrade process according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a startup process of a display system according to an embodiment of the present disclosure;

fig. 7 is a schematic flow chart of a first FPGA entering a functional mode one in the display system provided in the embodiment of the present application;

FIG. 8 is a schematic diagram of a display system in a second functional mode according to an embodiment of the present disclosure;

Fig. 9 is a schematic flow chart of a first FPGA entering a second functional mode in the display system provided in the embodiment of the present application;

fig. 10 is a schematic diagram of a 2SI format provided in an embodiment of the present application;

fig. 11 is a schematic diagram of an SQD format provided in an embodiment of the present application;

fig. 12 is a schematic diagram of a delay 0 frame of a complete 8K image output composed of 4 HDMI signals according to an embodiment of the present application;

fig. 13 is a schematic diagram of buffering an input 4-way HDMI signal by 0.5 frame and then displaying the buffered signal according to an embodiment of the present application;

fig. 14 is a schematic diagram showing that the relative position of the signal of hdmi_1 is behind hdmi_2 according to the embodiment of the present application;

fig. 15 is a schematic diagram of the maximum delay=0.5 frame+hdmi_1 and hdmi_2 of the hdmi_2 signal provided in the embodiment of the present application;

fig. 16 is a schematic diagram showing that the relative positions of hdmi_1 and hdmi_2 are interchanged according to the embodiment of the present application, so that the relative positions of the display on the screen end are interchanged;

fig. 17 is a block diagram of a dynamic adjustment input delay scheme of an HDMI received data processing module according to an embodiment of the present application;

FIG. 18 is a schematic diagram of a conventional design of stitching of data provided by embodiments of the present application;

FIG. 19 is a schematic diagram of performing different processing in different signal regions according to an embodiment of the present disclosure;

Fig. 20 is a block diagram of a split-region process of an 8K image signal provided in an embodiment of the present application;

FIG. 21 is a flow chart of a conventional zoning processing method according to an embodiment of the present application;

fig. 22 is a schematic general structural diagram of a display system according to an embodiment of the present application.

Detailed Description

The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

The terms first, second and the like in the description and in the claims of the embodiments and in the above-described figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The following examples and embodiments are to be construed as illustrative only. Although the specification may refer to "an", "one", or "some" example or embodiment(s) at several points, this does not mean that each such reference is related to the same example or embodiment, nor that the feature is applicable to only a single example or embodiment. Individual features of different embodiments may also be combined to provide further embodiments. Furthermore, terms such as "comprising" and "including" should be understood not to limit the described embodiments to consist of only those features already mentioned; such examples and embodiments may also include features, structures, units, modules, etc. that are not specifically mentioned.

Various embodiments of the present application are described in detail below with reference to the drawings attached hereto. It should be noted that, the display sequence of the embodiments of the present application only represents the sequence of the embodiments, and does not represent the advantages or disadvantages of the technical solutions provided by the embodiments.

Fig. 1 is a schematic diagram of an application scenario according to some embodiments of the present application, which is intended to illustrate a class of scenarios in which multiple reference monitors are present, including but not limited to devices with data transceiving and processing functions and image display and/or sound output functions, and a server that may communicate with the reference monitors. In the scenario shown in fig. 1, a control device 100, a reference monitor 200, a mobile device 300, and a server 400 are included.

Based on the internet of things technology, communication connection can be established between a plurality of reference monitors in the above scenario, such as communication between the mobile device 300 and the reference monitor 200, so as to project a screen displayed on the mobile device 300 onto the reference monitor 200. The number of similar terminal devices is not limited herein.

In some embodiments, control between different display devices may be achieved by control device 100. As shown in fig. 1, a user can control or operate the reference monitor 200 to switch a display mode, switch a data receiving function, and the like by the control device 100.

In some embodiments, the control device 100 may be a remote control, and the communications between the remote control and the reference monitor 200 may include infrared protocol communications or bluetooth protocol communications, and other short-range communications, and the reference monitor 200 may be controlled by wireless or wired means. The user can control the reference monitor 200 by inputting a user instruction through a key on the remote controller, a voice input, a control panel input, a key on the reference monitor 200, or the like.

In some embodiments, the user may switch the display function of the reference monitor 200 by controlling the apparatus 100, thereby implementing the display of the media data in the display mode corresponding to the display function.

For example, display scenarios include, but are not limited to: movies, sports, news, animation, variety, etc., different display modes are used to display media data in corresponding display scenes. For example, the display mode includes a game mode and a movie mode; the game mode is adapted to game picture display scenes and the movie mode is adapted to movie video picture display scenes. The parameter characteristics of the different display modes are different. And the display mode is switched to display the display picture corresponding to the display scene, so that the display effect is improved.

The parameter characteristics of the display mode are represented by video image quality parameters and audio quality parameters; video quality parameters include, but are not limited to: the higher the resolution, the clearer the picture), the brightness (the display brightness of the display device), the contrast (the clearer the image on the display device, the more vivid and gorgeous the color, the smaller the contrast, the more blurred the image on the display device and the gray-covered display effect), the screen refresh rate (the screen refresh rate is the number of times the display device screen refreshes the picture per second, the higher the screen refresh rate is, the smoother the picture is, the more color gamut is the color range region that the display device can display in the same color space, the higher the color gamut percentage is, and the color range that can be displayed is wider in the same color space).

Audio quality parameters include volume (volume of sound, i.e., intensity and amplitude of audio), pitch (tone of sound, i.e., frequency of audio or number of changes per second), and timbre (timbre of sound, i.e., overtones of audio).

For example, when the display scene is a cartoon, in the corresponding display mode (i.e., the cartoon mode), the screen refresh rate is 144Hz; when the display scene is news, the screen refresh rate is 120Hz in the corresponding display mode (i.e. news mode). In summary, the corresponding display modes are used for displaying according to different display scenes, so that the playing effect of the display picture can be improved. It should be noted that the above-mentioned screen refresh rate is merely an example, and there may be a plurality of different parameter characteristics in any two display modes, which is not specifically limited herein.

The term "remote control" as used in embodiments of the present application refers to a component of an electronic device (such as a reference monitor as disclosed herein) that can be controlled wirelessly, typically over a relatively short range of distances. Typically, the electronic device is connected to the electronic device using infrared and/or Radio Frequency (RF) signals and/or bluetooth, and may also include functional modules such as WiFi, wireless USB, bluetooth, motion sensors, etc. For example: the hand-held touch remote controller replaces most of the physical built-in hard keys in a general remote control device with a touch screen user interface.

The term "gesture" as used in the embodiments of the present application refers to a user behavior that is used to express an expected idea, action, purpose, and/or result by a change in a hand shape or a motion of a hand.

Referring to fig. 2, the 4K reference monitor in the prior art is designed based on an architecture of "FPGA (Field Programmable Gate Array ) +soc (System on Chip) +display screen", where the SOC requires a lot of time to complete loading initialization of a software program to start normal operation, which restricts the starting picture speed of starting up display, and as the data throughput increases, the architecture cannot meet the requirements of an 8K reference monitor display System, and at present, there is no reference monitor capable of receiving 8K signal input and displaying 8K. The embodiment of the application provides an 8K reference monitor display system scheme with simple structure and high starting speed.

The overall display system frame is shown in fig. 3, and the embodiment of the application adopts a system architecture of an SDI-HDMI adapter plate+a dual fpga+a display screen. Video data is transmitted from the input device to the SDI-to-HDMI adapter board (i.e., the SDI-to-HDMI 2.0 module in fig. 3), and SDI (Serial Digital Interface, digital component serial interface) signals are converted into signals in the form of HDMI (High Definition Multimedia Interface ) and transmitted into the first FPGA. In the first FPGA, the HDMI receives the data processing module to analyze the video signal into a digital signal, and sends the digital signal to the data processing function module, and the data processing function module performs image superposition or HDR and other image quality processing on the signal. The signal processed by the data processing functional module is sent to the rear end through the sending module, and finally, the signal is displayed on the display screen. The second FPGA, as an FPGA with an ARM core, mainly plays a role in system control, and includes: netlist configuration, parameter configuration, menu generation, system control and the like of the first FPGA.

A more specific example of a display system provided in an embodiment of the present application is given below.

As shown in fig. 3, in some embodiments, the SDI-to-HDMI adapter, the first FPGA, the second FPGA, the FLASH (FLASH memory), the SD card (Secure Digital Memory Card ), and the DDR (Double Data Rate) collectively form the display system provided in the embodiments of the present application. Wherein:

in some embodiments, the SDI-to-HDMI adapter plate (i.e., signal conversion plate) performs conversion of SDI signals to HDMI signals. The number of input interfaces is increased, and the interior of the adapter plate is composed of 4 SDI-to-HDMI chips, such as SDI2HMI_1, SDI2HMI_2, SDI2HMI_3 and SDI2HMI_4 shown in FIG. 3. Each chip supports at most 4 SDI inputs (e.g., SDI2hmi_1 has 4 sdi_1 inputs), and can support at most 16 SDI signal inputs. The design simplifies the implementation scheme for realizing 8K signal transmission. Because the implementation of the SDI protocol in the FPGA is complex, if the 16-path SDI protocol is implemented, the implementation in the FPGA occupies too much resources. The SDI interface is an interface commonly used by professional recording and playback devices. SDI signaling has a rich transmission protocol, such as: the 4K video data may be transmitted through one 12G SDI signal, and may be transmitted through 2 6G SDI signals, or 4 3G SDI signals.

In the embodiment of the application, 4 SDI-to-HDMI chips are used, and each chip has 4 SDI signal interfaces. The playing device for receiving the single-channel, double-channel and four-channel SDI signals can be compatible, so that the technical scheme provided by the embodiment of the application is stronger in general applicability and applicable to more client devices. The interfaces of the same type can be directly displayed through key switching. Avoiding the trouble caused by frequent manual replacement of the interface. For example, a single chip has 4 SDI signals. Then 4 SDI signal lines may connect to the playback devices of the 4 single-pass SDI. The four single-channel SDI playing devices can be switched and displayed in real time. Similarly, in the embodiment of the present application, 16 SDI signals may be connected to four playback devices with 4 SDIs. The output signals of the four playback devices of the 4-way SDI can be displayed at the screen end at the same time or individually.

In conclusion, through the signal transfer mode, interface resources are enriched, application scenes are increased, and resource consumption in the FPGA is saved. The SDI is converted into a single HDMI signal by virtue of the SDI-to-HDMI adapter plate. The FPGA only needs to analyze out 4 paths of single HDMI signals, and a complicated 16 paths of SDI protocols are not needed to be considered, so that compared with the prior art, the embodiment of the application saves about 75% of the resource consumption of the input interface on the premise of realizing the same function. Therefore, the beneficial effects of simplifying the internal design architecture of the FPGA and reducing the product cost are achieved.

In some embodiments, the first FPGA is reserved with an HDMI 2.1 interface, which facilitates access of professional playback devices, where the HDMI 2.1 interface may transmit a data amount of 8k@60hz, and the HDMI 2.0 interface may transmit a data amount of 4k@60hz at most. The maximum resolution of each output HDMI 2.0 signal can be supported to 4K. Then 4-way HDMI can transmit 8K of image data.

The first FPGA is a system core chip and is responsible for analysis of input images, transmission of image data output to a display screen, processing of image quality, image superposition and the like.

The second FPGA is an FPGA with ARM core, and mainly plays a role in system control and provides a system auxiliary function.

The chip in the second FPGA is divided into two parts:

PL portion, programmable Logic, logic function portion.

The PS part, processing System, the processor system part, contains the ARM core.

FLASH: and storing the netlist required by the first FPGA, the netlist program required by the second FPGA, configuration parameters, boot pictures and other data.

SD card: and reserving, for upgrading the system version and storing the data required by the system upgrade.

DDR: the buffer is used for buffering data and improves the efficiency of data transmission.

With respect to the first FPGA and the second FPGA described above, further examples are given below:

HDMI received data processing module: serial-parallel conversion of HDMI data is carried out, serial data of front-end equipment, such as HDMI_1, HDMI_2, HDMI_3 and HDMI_4 shown in fig. 3, are converted into parallel digital signals, and the 4 paths of 4K HDMI signals are spliced into one path of 8K signals, for example, the data are arranged and combined according to a transmission protocol; alternatively, the single HDMI signal is amplified to an 8K signal, and for example, the image is amplified from 4K to 8K using a scaling algorithm.

And the data processing functional module is as follows: the images are subjected to different processing such as superimposition of data, selection, and processing of image quality, thereby displaying different effects, for example, effects such as HDR (High-Dynamic Range) 10, hlg (Hybrid Log Gamma), SDR (Standard Dynamic Range ), and the like. And a sending module: and carrying out parallel-serial conversion on the data, converting the parallel digital signals into serial signals, and sending the serial signals to a display screen at the rear end for display.

Parameter configuration module: and receiving externally configured parameter data and configuring the parameters into the data processing functional module. The parameter data are for example: select parameters showing different effects, when to select an HDR effect, or parameter information of an HLG effect, or look-up table (LUT) parameters needed inside the HDR, HLG.

In some embodiments, the data processing function module, for example: an image quality processing module (including an HDR functional module, an HLG functional module and the like), a data superposition module, a data selection module and the like. Each module corresponds to its own respective parameter. For example: the HDR module needs to configure resolution parameters, look-up table parameters, etc. The parameters can be sent to the corresponding functional modules through the parameter configuration module, so that parameter configuration is realized. The FPGA internal functional module is a configurable module. For example, 1080P, 4K or 8K image data may be processed by merely changing the resolution parameters.

In some embodiments, the second FPGA comprises:

PL portion: and carrying out quick data carrying processing.

PS part: drawing of menus, control of the system, etc.

In some embodiments, the PL portion of the second FPGA is of modular design, as shown in figure 4.

wherein ：

and the netlist configuration module is used for configuring the first FPGA netlist.

And the FLASH read-write module is used for performing operations such as read-write and erase on the FLASH.

And the SD card reading module is used for reading data in the SD.

And the menu sending module is used for sending the menu drawn by the PS to the first FPGA to carry out data superposition processing. The menu sending module sends the menu image data to the data superposition module in the first FPGA. The data superimposing module superimposes the menu image data on the full-screen image acquired from the front-end HDMI receiving data processing module, for example, to achieve the effect of a picture-in-picture or a computer menu.

And the starting picture sending module is used for sending the starting picture data stored in the FLASH to the first FPGA.

The DDR read-write module is a module for reading and writing DDR and caching data. Is an intermediary between other modules within the PL and the DDR particles.

In some embodiments, as shown in fig. 4, in the first FPGA:

and the data superposition module is used for superposing the menu image data sent by the menu sending module into a full-screen image to generate, for example, a picture-in-picture or a computer menu.

And the data selection module is used for selecting which path of data is transmitted to the following transmission module according to the requirement. And selecting whether the data come from a starting picture sending module or a data superposition module in the second FPGA.

In the first functional mode shown in fig. 4, that is, in the data processing functional module in the first FPGA, the module in the working state includes a data superimposing module and a data selecting module.

Similarly, in the second functional mode in fig. 8, that is, in the data processing functional module in the first FPGA at this time, the module in the working state includes an image quality processing module and a data superimposing module.

In some embodiments, when the entire system needs to be upgraded, see fig. 5, comprising the steps of:

501. Outputting a user interface, acquiring a user instruction through the user interface, and setting the system to be in an SD card upgrading mode in response to the user instruction;

502. powering up the system;

503. the second FPGA automatically loads a netlist program from the SD card;

504. and the second FPGA enters a working state. The PL needs to configure a netlist file, and the PS needs to load menus and control programs.

505. And the FLASH read-write module erases the original data in the FLASH.

506. And the SD card reading module reads the data to be upgraded of the FLASH from the SD card.

507. And the FLASH read-write module is used for writing the data to be upgraded into the FLASH.

508. And finishing updating and upgrading of the data version in the FLASH.

In some embodiments, the following description is given with respect to a startup procedure of the display system provided in the embodiments of the present application:

the chip size of the first FPGA is relatively large due to the amount of data that needs to be processed at 8K. Correspondingly, with the strong internal functions of the first FPGA, the netlist file of the first FPGA is also increasing. The size of the first FPGA netlist file is a main factor affecting the start-up speed of the display system provided in the embodiments of the present application. When the internal functions of the first FPGA are simple, the generated netlist file is reduced, and conversely, when the internal functions of the FPGA are complex, the netlist file is enlarged. The complex image processing function consumes most of the resources in the FPGA. Based on this, the technical scheme provided in the embodiment of the present application generates two sets of netlists according to the difference of main functional modes inside the FPGA:

The first netlist corresponds to the first FPGA functional mode I, at the moment, the internal processing of the first FPGA is simple, the scale of the first netlist is smaller, and the configuration speed is higher.

The second netlist corresponds to the second functional mode of the first FPGA, at the moment, the internal processing of the first FPGA comprises a complex image processing function, the size of the second netlist is large, and the netlist needs to be loaded for a longer time.

In order to shorten the starting time, when the first FPGA is started, the first FPGA is set to enter a first functional mode, and the time corresponding to the first FPGA configuration netlist is reduced. The time for the corresponding first FPGA to enter the working state is shortened, the time for the whole system to enter the working state is shorter, and the whole starting-up process is also accelerated.

As shown in fig. 6, the system power-on process (when the first FPGA is in the functional mode one) includes the following steps:

601. outputting a user interface, receiving a user instruction through the user interface, and switching the whole system to a FLASH starting mode in response to the user instruction;

602. powering up the system;

603. the second FPGA automatically loads a netlist program from the FLASH;

604. PL and PS in the second FPGA enter a working state.

605. And the FLASH read-write module reads the first netlist of the first FPGA from the FLASH.

606. And the netlist configuration module configures a first netlist for the first FPGA.

607. Completing configuration of a first FPGA;

608. and the FLASH read-write module reads the starting picture data from the FLASH.

609. And the writing module in the DDR reading and writing module writes the starting picture into the DDR for caching.

610. Reading a starting picture by a reading module in the DDR reading and writing module;

611. the starting picture sending module sends the starting picture to the data selecting module.

612. The data selection module selects the starting picture to be sent to the rear-end display screen for display.

613. And finishing the power-on display process.

Because the menu design occupies larger internal resources of the FPGA, in order to save the internal resources of the FPGA and increase the design flexibility, the menu design part is placed in the PS part of the second FPGA to finish the design. And sending the menu data to the first FPGA for superposition through a menu sending module in the second FPGA.

In some embodiments, as shown in fig. 7, the first FPGA enters the flow of the functional mode one, for example, including:

701. the first FPGA completes configuration of a first netlist;

702. ending the starting picture;

703. the menu transmitting module transmits the menu image data to the data superimposing module.

704. The HDMI received data processing module analyzes the data received by the front end.

705. The data superposition module superimposes the menu image data on the image data output by the front-end HDMI received data processing module.

706. The data selecting module selects the image data after data superposition and sends the image data to the sending module.

707. The sending module sends the data with the menu image data superimposed on the front end to the rear end display screen for output display;

708. the first FPGA enters a functional mode one state. The user can see the image input by the front-end input device, switch the channel mode by the menu button, etc., and can select the input channel through the menu. For example, an 8k image from 1 HDMI 2.1 may be selected for display, or an image from 4 HDMI 2.0 may be selected for display.

The function mode one can provide the user with the function of a common display screen. The reference monitor function needs to be switched to the functional mode two state when a professional display function is required.

In some embodiments, the display system structure in the second functional mode is shown in fig. 8, and it can be seen that the difference between the display system structure in the second functional mode and the first functional mode is that, in the data processing functional modules in the first FPGA, the modules in the working state include an image quality processing module and a data superimposing module.

In some embodiments, as shown in fig. 9, the process of entering the functional mode two includes:

901. and when the starting-up picture is displayed, outputting a user interface, receiving a user instruction through the user interface, and setting the first FPGA to enter a second working mode in response to the user instruction.

902. A FLASH read-write module in the second FPGA reads a second netlist and configuration parameters of the first FPGA from the FLASH;

903. and the DDR read-write module writes the second netlist and the configuration parameters of the first FPGA into the DDR. The first FPGA is ready for entering the second functional mode in advance.

904. And sending an instruction for switching from the first functional mode to the second functional mode to the first FPGA through the menu sending module.

905. The DDR read-write module reads a second netlist of the first FPGA from the DDR.

906. The second netlist is configured to the first FPGA by a netlist configuration module.

907. The first FPGA completes the configuration of the second netlist.

908. The DDR read-write module reads the configuration parameters from the DDR.

909. And sending the configuration parameters to a parameter configuration module in the first FPGA. Specifically, the DDR read-write module reads parameters from the DDR and sends the parameters to a PS (ARM) terminal. The PS end sends the parameters to the parameter configuration module through SPI transmission protocol.

910. The parameter configuration module completes the parameter configuration of the image quality processing module.

911. The data overlaying module overlays the menu into the front-end image.

912. And the sending module sends the superimposed data to a rear-end display screen for display.

913. The first FPGA enters functional mode two.

In some embodiments, the delay requirements for the signal are very stringent, especially when relaying programs for sporting events, electronic athletic games, and the like, which are high-speed sports. When the multi-channel HDMI signals are input, the multi-channel signals are synchronous and asynchronous, for example, when the 4-channel HDMI signals jointly transmit the 8K signals, the 4-channel HDMI signals are transmitted to the FPGA by the same device, and the 4-channel HDMI signals can be considered to be signals with synchronous frame start. When the 4 HDMI signals are respectively from different devices, then the frame start positions of the 4 HDMI signals can be considered to be unsynchronized. Therefore, in order to reduce the delay of the video signal, the embodiment of the application also proposes a scheme of dynamically adjusting the input delay.

Case one: when the frame start signals of the 4-way HDMI signals are synchronized, for example, when the 8K signals are transmitted using the 4-way SDI line, there are two basic data combination manners according to the SDI protocol: a 2SI format as shown in fig. 10, and a SQD format as shown in fig. 11.

When 4 HDMI signals are transmitted in the 2SI format, each signal transmits 2 pixels, and as shown in fig. 10, the signals are arranged according to a certain rule. At this time, the input image data can be combined in real time to form an 8K image, and the 4 HDMI signals form a complete 8K image output, which is delayed by only a few clocks, so that it can be represented by a delay of 0 frame, as shown in fig. 12.

When 4 HDMI signals are transmitted according to the SQD format, each signal transmits a complete 1/4 part of 8K signals, and the signals are arranged according to a 'field' shape. To complete the stitching of 8K images in a "left to right, top to bottom" manner. The input 4-way HDMI signal needs to be buffered for 0.5 frame and then displayed as shown in fig. 13.

And a second case: when the frame start signals of the 4 HDMI signals are asynchronous, for example, each signal is connected to a different playback device, and the four areas on the screen are displayed independently.

In the case shown in fig. 15, the frame start signals of the 4 HDMI signals are not synchronized, and in order to reduce the delay of data combination, the frame start relative positions of each signal are first sorted. As shown in fig. 14, the relative position of the signal of hdmi_1 is behind hdmi_2, and the relative positions of hdmi_1 and hdmi_2 are interchanged by the relative position adjustment. All signal start positions are arranged in a back-and-forth order.

Then the 4 signals at this time constitute the complete 8K signal data.

Referring to fig. 15, the maximum delay of the hdmi_2 signal=0.5 frame+hdmi_1 and hdmi_2 relative position difference;

hdmi_1 signal delay = 0.5 frame;

hdmi_3, hdmi_4 signal delay <0.5 frame;

since the relative positions of hdmi_1 and hdmi_2 are interchanged, the display relative positions at the screen end are also interchanged, as shown in fig. 16.

Fig. 17 is a block diagram of the dynamic adjustment input delay scheme of the HDMI received data processing module. After being analyzed by the HDMI analysis module, the 4 paths of HDMI signals are sent to the phase comparison detection module, and the relative positions of frame start signals of all data are detected. And according to the relative positions and the processing types of the signals, carrying out data buffering delay on the signals through the data buffering module. And in the data alignment and splicing module, the 8K images are completely spliced from left to right and from top to bottom and are output to the back-end data processing functional module.

The conventional design is shown in fig. 18 corresponding to the concatenation of data. All input data is buffered for 1 frame time and then image stitching is performed. The method has the advantage of simple design. But the data delay is larger and occupies larger data buffering space. By means of the scheme, dynamic input adjustment is carried out on different signals through signal classification, and instantaneity of display signals is guaranteed to the greatest extent.

When the 4-way HDMI signal is displayed independently on the display screen, in some embodiments, different processing is required in different signal areas. As shown in fig. 19, picture 1 calls a gamma2.2 curve, picture 2 calls a gamma2.4 curve, picture 4 calls a gamma 2.6 curve, and picture 4 calls a gamma2.2 curve.

In some embodiments, image processing is performed in the form of coordinate region division. As shown in fig. 20, the data processing module receives an 8K image signal input. And positioning the coordinates of the image according to the relative positions of the vertical pixel parameter and the horizontal pixel parameter of the display image. Each rectangular area consists of 4 coordinates. For example, in the screen 1 of fig. 19, a rectangular region may be defined by four vertices (a, b), (a, c), (d, b), (d, c). Wherein, a and d represent row numbers of the vertex pixels in the coordinates, and b and c represent column numbers of the pixel points.

Fig. 20 is a block diagram of the zoning process. The 8k image signal is input to the data processing function module. The coordinate allocation module receives settings from outside, including, for example: the screen 1 implements the gamma2.2 function, and the rectangular area vertex coordinate positions of the screen area 1 are (a, b), (a, c), (d, b), (d, c), respectively. Then when the pixel position of the 8K image signal is detected to satisfy the condition: when (d > =row number > =a)/(c > =column number > =b), the parameter calling module calls the Gamma2.2 parameter in the parameter storage module to perform data configuration, so that the image of the picture area 1 displays the Gamma2.2 effect.

FIG. 21 is a diagram of a conventional split-region processing method that calls a data processing module once for one data path. And then, splicing and combining the data through a data superposition module. The method consumes larger resources and has higher cost. Compared with the conventional method, the scheme provided by the embodiment of the application saves a large amount of logic resources, and can save the resource consumption by about 75%.

In summary, referring to fig. 22, a display system provided in an embodiment of the present application includes:

the signal switching board 11 is configured to receive video data sent by the input device, convert the video data from a digital component serial interface SDI signal to a high-definition multimedia interface HDMI signal, and send the converted video data to the first FPGA;

the first FPGA 12 is configured to receive the HDMI video signal sent by the signal adapter board, parse the HDMI video signal into a digital signal, perform image processing on the digital signal, and send the digital signal to a display screen for display;

FLASH 13, which is used for storing the netlist program of the second FPGA, the first netlist required to be configured by the first FPGA under a preset functional mode, and the second netlist required to be configured by the first FPGA under a preset functional mode II; wherein the data size of the first netlist is smaller than the data size of the second netlist; when the computer is started, the first FPGA enters the first functional mode;

The second FPGA 14 is configured to enter a working state by loading the netlist program after the system is switched to a FLASH start mode and the system is powered on; and in the functional mode, the first netlist is configured for the first FPGA, and in the functional mode II, the second netlist is configured for the first FPGA.

The reference monitor provided by the embodiment of the application comprises the display system.

Therefore, in the existing 4K reference monitor, the SOC chip needs a lot of time to complete the loading initialization of the software program to start normal operation, which restricts the starting picture speed of starting display, and no special 8K monitor SOC chip exists in the market. Compared with the existing 4K reference monitor, the embodiment of the application has the following beneficial effects:

the second FPGA with higher data processing speed is used for replacing the SOC chip, so that the system is simplified, and the data processing speed is also increased;

on the loading design of the FPGA netlist, an active configuration mode is adopted, and when the FPGA netlist is started, a smaller netlist (a first netlist) is adopted to accelerate the starting speed, so that the starting time is shortened;

in the aspect of starting-up picture display, the second FPGA internal hardware logic (PL part) is directly used for carrying data, so that a complex 8K image can be rapidly displayed. The speed is faster than the way the SOC uses software to handle data to display the boot-up picture.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims

1. A display system, the system comprising:

The second FPGA is used for switching the system to a FLASH starting mode, and entering a working state by loading the netlist program after the system is powered on; in the second functional mode, the second netlist is configured for the first FPGA;

wherein, the first FPGA includes:

the HDMI receiving data processing module is used for converting the serial HDMI video signals input by the signal adapter plate into parallel digital signals;

the data processing function module is used for carrying out image processing on the digital signals;

the transmitting module is used for converting the parallel digital signals processed by the data processing functional module into serial video signals and transmitting the serial video signals to the display screen for display;

the parameter configuration module is used for configuring parameters for the data processing function module under the control of the second FPGA;

the data processing functional module comprises: the system comprises a data superposition module, a data selection module and an image quality processing module; wherein,

in the functional mode, the data superposition module performs superposition processing on menu image data from the second FPGA and the digital signal output by the HDMI receiving data processing module to obtain superposed image data; the data selection module selects and outputs the starting picture from the second FPGA or the image data output by the data superposition module to the transmission module;

In the second functional mode, the image quality processing module performs image quality processing on the digital signal output by the HDMI received data processing module; and the data superposition module is used for superposing the menu image data from the second FPGA and the image data output by the image quality processing module to obtain superposed image data.

2. The system of claim 1, wherein the second FPGA comprises:

the logic function module is used for switching the system to a FLASH starting mode, and entering a working state by loading the netlist program after the system is powered on; in the second functional mode, the second netlist is configured for the first FPGA;

and the processor system module is used for drawing the menu image data.

3. The system of claim 2, wherein the system further comprises:

the SD card is used for storing data required by system upgrading;

DDR, is used for buffering the data;

the logic function module comprises:

the netlist configuration module is used for configuring the first netlist for the first FPGA in the functional mode, and configuring the second netlist for the first FPGA in the functional mode II;

The FLASH read-write module is used for performing read-write and erase operations on the FLASH;

the SD card reading module is used for reading data in the SD card;

the menu sending module is used for sending the menu image data drawn by the processor system module to the first FPGA, and the first FPGA carries out image data superposition processing on the menu image data;

the starting-up picture sending module is used for sending the starting-up picture stored in the FLASH to the first FPGA;

and the DDR read-write module is used for performing data read-write operation on the DDR.

4. The system of claim 3, wherein when the system is switched to a FLASH start mode, after the system is powered on, the second FPGA enters a working state:

the FLASH read-write module reads the first netlist from the FLASH;

the netlist configuration module configures a first netlist for a first FPGA;

the FLASH read-write module reads the starting picture from the FLASH;

the DDR read-write module writes the starting picture into the DDR for caching; and reading a starting picture from the DDR and sending the starting picture to the sending module;

the sending module sends the starting picture to the data selecting module;

And the data selection module selects to send the starting picture to the display screen for display.

5. The system of claim 3, wherein when the display screen displays a boot-up picture, the FLASH read-write module reads the second netlist and configuration parameters from the FLASH; the DDR read-write module writes the second netlist and the configuration parameters into the DDR;

the menu sending module is further used for sending an instruction for switching from the first functional mode to the second functional mode to the first FPGA;

the DDR read-write module reads the second netlist from the DDR;

the netlist configuration module configures the second netlist to the first FPGA;

the DDR read-write module reads configuration parameters from the DDR and sends the configuration parameters to a parameter configuration module in the first FPGA;

the parameter configuration module is used for completing parameter configuration of the image quality processing module according to the configuration parameters;

the data superposition module is used for superposing menu image data into the image processed and output by the image quality processing module;

and the sending module sends the superimposed image data to the display screen for display.

6. A system according to claim 3, wherein when the system requires an upgrade:

the second FPGA enters a working state by loading a netlist program from the SD card;

the FLASH read-write module erases the original data in the FLASH;

the SD card reading module reads the data which needs to be upgraded of the FLASH from the SD card;

and the FLASH read-write module writes the data which needs to be updated in the FLASH into the FLASH to finish the updating and upgrading of the data version in the FLASH.

7. The system of claim 1 wherein the signal patch panel comprises 4 SDI-to-HDMI chips, each of the chips supporting 4 SDI signal inputs, the 4 chips outputting a total of 4 HDMI signals to the first FPGA;

the HDMI signal output by the chip is an HDMI 2.0 signal, and the interface between the first FPGA and the signal adapter plate is an HDMI 2.0 signal interface;

the first FPGA further includes an HDMI2.1 signal interface for receiving an HDMI2.1 signal input by the input device.

8. The system of claim 1, wherein the HDMI received data processing module comprises: the device comprises an HDMI analysis module, a phase comparison detection module, a data buffer module and a data alignment splicing module; wherein,

The HDMI analysis module analyzes the input multi-path HDMI signals, sends the multi-path HDMI signals into the phase comparison detection module, detects the relative position of the frame starting signals of all paths of HDMI signals, carries out data buffering delay on all paths of HDMI signals through the data buffering module according to the relative position and the processing type, and splices complete images according to a preset rule at the data alignment splicing module and outputs the complete images to the data processing functional module.

9. The system of claim 1, wherein the first FPGA further comprises: the system comprises a coordinate distribution module, a parameter calling module and a parameter storage module; wherein,

when an image signal is input into the data processing functional module, the coordinate distribution module receives setting information from the outside, wherein the setting information comprises an effect to be displayed of a picture and a vertex coordinate position of a rectangular area of the picture;

when the pixel position of the image signal input into the data processing function module is determined to be in the rectangular area according to the vertex coordinate position of the rectangular area of the picture, the parameter calling module calls parameters corresponding to the effect in the parameter storage module to perform data configuration, and the effect is displayed by the image in the rectangular area of the picture.

10. A reference monitor comprising a display system as claimed in any one of claims 1 to 9.