CN116016943A - Data decoding method and device, electronic equipment and storage medium - Google Patents
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Abstract
The disclosure provides a data decoding method, a data decoding device, electronic equipment and a storage medium, and relates to the technical field of computers. The method comprises the steps of analyzing appointed encoded data to obtain decoding information, wherein the decoding information comprises effective data and effective data length; writing the decoding information into a first-level cache; writing the effective data in the first-level cache into the second-level cache according to the length of the effective data stored in the first-level cache; and outputting the decoded data corresponding to the appointed encoded data through the secondary buffer memory. According to the embodiment of the disclosure, the data instantaneity problem caused by the fact that the length of the decoding result is not fixed and unpredictable is improved by inserting the first-level buffer memory and the second-level buffer memory in the decoding process.
Description
Technical Field
The disclosure relates to the field of computer technology, and in particular, to a data decoding method, a data decoding device, electronic equipment and a storage medium.
Background
In the compression method of still images and moving videos, improvement of the encoding and decoding efficiency is urgent due to large information amount and high speed. The most common coding scheme is Variable-Length Code (VLC) based coding, such as Huffman coding. The decoding of the variable length code is more complex than the fixed length code. The real-time performance of the method not only needs to improve the clock frequency, but also needs to be improved from the angles of algorithm and hardware optimization, and can cause larger hardware cost and development difficulty.
Disclosure of Invention
In view of this, the present disclosure provides a data decoding method, apparatus, electronic device, and storage medium.
In a first aspect, a data decoding method is provided, including: analyzing the appointed encoded data to obtain decoding information, wherein the decoding information comprises effective data and effective data length; writing the decoding information into a first-level cache; writing the effective data in the first-level cache into the second-level cache according to the length of the effective data stored in the first-level cache; and outputting the decoded data corresponding to the appointed encoded data through the secondary buffer memory.
In some embodiments, parsing the specified encoded data to obtain decoding information includes: analyzing the encoded data based on at least one decoding block to obtain at least one analysis result, wherein the number of the decoding blocks is smaller than or equal to the minimum encoding unit of the designated encoded data; and splicing at least one analysis result to obtain decoding information.
In some embodiments, writing the decoded information to the first level cache includes: writing the effective data into a first-level cache; an information head is added for writing the effective data of the first-level cache, and the information head is used for storing the effective data length.
In some embodiments, writing valid data in the primary cache to the secondary cache according to the length of valid data stored in the primary cache comprises: if the first-level cache is in a non-empty state, reading the effective data length in the information head; and writing the effective data in the first-level cache into the second-level cache according to the effective data length and the preset decoding data bit width.
In some embodiments, writing the valid data in the primary cache into the secondary cache according to the valid data length and the preset decoded data bit width comprises: and if the effective data length is greater than or equal to the decoding data bit width, writing the effective data with the length equal to the decoding data bit width in the first-level buffer memory into the second-level buffer memory.
In some embodiments, writing the valid data in the primary cache into the secondary cache according to the valid data length and the preset decoded data bit width comprises: and if the effective data length is smaller than the decoding data bit width, waiting for writing new decoding information into the first-level buffer memory until the sum of all the effective data lengths stored in the information head is greater than or equal to the decoding data bit width, and writing the effective data with the length equal to the decoding data bit width into the second-level buffer memory.
In some embodiments, writing the valid data in the primary cache into the secondary cache according to the valid data length and the preset decoded data bit width comprises: if the effective data is the last effective data obtained by analyzing the appointed coded data, filling the effective data so that the effective data length is the same as the decoding data bit width; and writing the filled effective data into a secondary cache.
In a second aspect, there is provided a data decoding apparatus comprising: the analysis module is used for analyzing the appointed encoded data to obtain decoding information, wherein the decoding information comprises effective data and effective data length; the first writing module is used for writing the decoding information into the first-level cache; the second writing module is used for writing the effective data in the first-level cache into the second-level cache according to the length of the effective data stored in the first-level cache; and the output module is used for outputting the decoded data corresponding to the appointed encoded data through the secondary buffer memory.
In a third aspect, there is provided an electronic device comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the method of the first aspect described above via execution of executable instructions.
In a fourth aspect, a computer readable storage medium is provided, on which a computer program is stored which, when executed by a processor, implements the method of the first aspect described above.
According to the data decoding method provided by the embodiment of the disclosure, decoding information is obtained by analyzing specified encoded data, the decoding information comprises effective data and effective data length, and then the decoding information is written into the first-level buffer
And storing, writing the effective data in the first-level buffer into a second-level buffer 5 according to the length of the effective data stored in the first-level buffer, and outputting the decoded data corresponding to the appointed encoded data through the second-level buffer. According to the embodiment of the disclosure, the data instantaneity problem caused by the fact that the length of the decoding result is not fixed and unpredictable is improved by inserting the first-level buffer memory and the second-level buffer memory in the decoding process.
Drawings
Fig. 1 is a schematic diagram of a system architecture of a data decoding method according to an embodiment of the disclosure.
Fig. 2 is a flow chart illustrating a data decoding method according to an embodiment of the disclosure.
Fig. 3 is a schematic diagram illustrating a structure of a data decoding apparatus in an embodiment of the present disclosure.
Fig. 4 shows a schematic structural diagram of an electronic device in an embodiment of the disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiment 5 may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals as those of 0 denote the same or similar parts in the drawings, and thus a repetitive description thereof will be omitted. Drawings
Some of the block diagrams shown in (a) are functional entities, not necessarily corresponding to physically or logically separate entities. These functional entities may be implemented in software or in one or more hardware modules or integrated circuits or in different networks and/or processor devices and/or microcontroller devices.
For ease of understanding, the several terms involved in this disclosure are first explained as follows:
encoding is the process of converting information from one form or format to another, encoding alphanumeric or other objects into numbers by a pre-specified method, or converting information, data into specified electrical pulse signals.
The variable length coding refers to a coding scheme in which the original information amount included in the coded information of the same length is not fixed or predictable.
Decoding is a process of restoring a digital code to what it represents or converting an electric pulse signal, an optical signal, a radio wave, etc. to information, data, etc. that it represents by a specific method, corresponding to the encoding process.
A first-in first-out (First In First Out, FIFO) buffer refers to a first-out data buffer, which has no external read-write address interface, and therefore can only sequentially write data and sequentially read data.
Fig. 1 shows an exemplary system architecture diagram of a data decoding method or data decoding apparatus that may be applied to embodiments of the present disclosure.
As shown in fig. 1, the system architecture includes a data allocation module 101, a decoding block 102, a data combining module 103, a write-level buffer module 104, a level-one buffer 105, a read-level buffer-write-level buffer module 106, and a level-two buffer 107, which are sequentially connected.
Specifically, the data distribution module 101 is configured to receive input encoded data and distribute the encoded data to each decoding block 102 according to a minimum coding unit, where, let the minimum coding unit be u, the encoded data width be m (m% u= 0), and the parallelism be n (i.e., n is the number of decoding blocks 102), and the data distribution module 101 provided in the embodiment of the present disclosure can be compatible with two cases of n < u and n= = u at the same time.
The decoding block 102 is configured to parse according to the encoding rule and output a decoding result.
The data combination module 103 is configured to combine the data according to the decoding results output by the decoding blocks 102, obtain decoding information, and fill the decoding information into the data register of the write-level buffer module 104. The decoding information includes effective data and effective data length, the width of the data register of the write-level buffer module 104 is larger than the effective data length, and the filling position of the decoding information is determined by the position of the decoding information in the original encoded data and the effective data length.
The write level one buffer module 104 is configured to determine whether to write the decoding information into the level one buffer according to the effective data length and the data capacity in the level one buffer. When the decoding information is written into the first-level buffer, the effective data is directly written into the first-level buffer, and the effective data length is added to the information header of the effective data. In addition, the header of the valid data may further include a data end flag indicating whether the valid data corresponds to the last data in the encoded data.
The first level buffer 105, which is implemented by a FIFO buffer, sets an almost full (all_full) flag so that the write first level buffer module 104 can write the decoded information into the first level buffer using the timing logic, thereby enabling the whole system to have better timing convergence.
And the reading first-level cache writing second-level cache module 106 is configured to read the first-level cache when the first-level cache 105 is not empty, and write the effective data in the first-level cache into the second-level cache according to the effective data length stored in the first-level cache.
The second level buffer 107, which is the same as the first level buffer 105, is implemented by FIFO buffers, and will not be described in detail in this disclosure.
The present exemplary embodiment will be described in detail below with reference to the accompanying drawings and examples.
First, in an embodiment of the present disclosure, a data decoding method is provided, which may be performed by any electronic device having computing processing capability.
Fig. 2 is a schematic flow chart of a data decoding method according to an embodiment of the disclosure, and as shown in fig. 2, the data decoding method provided in the embodiment of the disclosure includes the following steps.
S201, analyzing the appointed encoded data to obtain decoding information, wherein the decoding information comprises effective data and effective data length.
It should be noted that, in the embodiment of the present disclosure, the specified encoded data may be variable-length encoded data, and accordingly, the effective data is effective data obtained by parsing the variable-length encoded data, and for variable-length encoding, the effective data lengths of the effective data may be the same or different.
Illustratively, at least one parsing result may be obtained by parsing the encoded data based on at least one decoding block. And splicing at least one analysis result to obtain decoding information. The number of the decoding blocks is smaller than or equal to the minimum coding unit of the appointed coding data, so that the parallelism of the analysis process can be flexibly configured according to the hardware overhead requirement, and the waste of resources is avoided.
Specifically, the decoding result includes sub-valid data and sub-valid data length, and the valid data and valid data length in the decoding information can be obtained by sequentially splicing at least one sub-valid data according to the sequence of the sub-valid data in the appointed encoded data and accumulating the sub-valid data length.
S202, the decoding information is written into the first-level cache.
Illustratively, valid data may be written directly to the primary cache. Meanwhile, an information head can be added for writing the effective data of the first-level cache, and the information head is used for storing the effective data length. In addition, the header of the valid data may further include a data end flag indicating whether the valid data corresponds to the last data in the encoded data.
S203, writing the effective data in the first-level cache into the second-level cache according to the length of the effective data stored in the first-level cache.
In some embodiments, if the level one cache is not empty, the valid data length in the information header is read. And then writing the effective data in the first-level cache into the second-level cache according to the effective data length and the preset decoding data bit width. The decoding data bit width is the data length which can be output by the method provided by the embodiment of the disclosure in each clock cycle.
Specifically, S203 can be divided into the following cases:
and if the effective data length is greater than or equal to the decoding data bit width, writing the effective data with the length equal to the decoding data bit width in the first-level buffer memory into the second-level buffer memory. When the effective data length is greater than the bit width of the decoded data, after the effective data is written into the second-level cache data, the effective data in the first-level cache still remains, and when the size relation between the effective data length and the bit width of the decoded data is judged next time, the effective data length is the total length of all the effective data in the first-level cache, namely the sum of the length of the remaining effective data and the new effective data length.
And if the effective data length is smaller than the decoding data bit width, waiting for writing new decoding information into the first-level buffer memory until the sum of all the effective data lengths stored in the information head is greater than or equal to the decoding data bit width, and writing the effective data with the length equal to the decoding data bit width into the second-level buffer memory.
And if the effective data is the last effective data obtained by analyzing the appointed encoded data, filling the effective data so that the effective data length is the same as the bit width of the decoded data, and then writing the filled effective data into a secondary cache. The filling mode is to perform zero padding operation in the effective data. In addition, according to the data end mark, it can be judged that the effective data is the last effective data obtained by analyzing the specified encoded data.
S204, outputting the decoded data corresponding to the appointed encoded data through the secondary buffer.
It should be noted that the decoded data may be valid data. Specifically, the second level buffer may sequentially output valid data having a length equal to a preset bit width of the decoded data.
According to the data decoding method provided by the embodiment of the disclosure, decoding information is obtained by analyzing the appointed encoded data, the decoding information comprises effective data and effective data length, then the decoding information is written into the first-level buffer memory, the effective data in the first-level buffer memory is written into the second-level buffer memory according to the effective data length stored in the first-level buffer memory, and further the decoding data corresponding to the appointed encoded data can be output through the second-level buffer memory. According to the embodiment of the disclosure, through inserting the first-level buffer memory and the second-level buffer memory in the decoding process, the problem of data instantaneity caused by the fact that the length of a decoding result is not fixed and is unpredictable is solved, and the decoding efficiency is improved.
Based on the same inventive concept, a data decoding apparatus is also provided in the embodiments of the present disclosure, as described in the following embodiments. Since the principle of solving the problem of the embodiment of the device is similar to that of the embodiment of the method, the implementation of the embodiment of the device can be referred to the implementation of the embodiment of the method, and the repetition is omitted.
Fig. 3 is a schematic structural diagram of a data decoding apparatus according to an embodiment of the present disclosure, and as shown in fig. 3, the data decoding apparatus 300 includes: the device comprises a parsing module 301, a first writing module 302, a second writing module 303 and an output module 304.
Specifically, the parsing module 301 is configured to parse the specified encoded data to obtain decoding information, where the decoding information includes valid data and valid data length. A first writing module 302, configured to write the decoded information into the first level cache. And the second writing module 303 is configured to write the valid data in the first level cache into the second level cache according to the valid data length stored in the first level cache. And an output module 304, configured to output the decoded data corresponding to the specified encoded data through the secondary buffer.
In some embodiments, the parsing module 301 is further configured to parse the encoded data based on at least one decoding block to obtain at least one parsing result, where the number of decoding blocks is less than or equal to a minimum coding unit of the specified encoded data; and splicing at least one analysis result to obtain decoding information.
In some embodiments, the first writing module 302 is further configured to write valid data into the first level cache; an information head is added for writing the effective data of the first-level cache, and the information head is used for storing the effective data length.
In some embodiments, the second writing module 303 is further configured to read the valid data length in the information header if the first level cache is in a non-empty state; and writing the effective data in the first-level cache into the second-level cache according to the effective data length and the preset decoding data bit width.
In some embodiments, the second writing module 303 is further configured to write the valid data with the length equal to the bit width of the decoded data in the first level buffer into the second level buffer if the valid data length is greater than or equal to the bit width of the decoded data.
In some embodiments, the second writing module 303 is further configured to wait for writing new decoded information in the first level buffer if the effective data length is less than the decoded data bit width until the effective data with the length equal to the decoded data bit width in the first level buffer is written into the second level buffer when the sum of all the effective data lengths stored in the information header is greater than or equal to the decoded data bit width.
In some embodiments, the second writing module 303 is further configured to, if the valid data is the last valid data obtained by parsing the specified encoded data, pad the valid data so that the valid data length is the same as the decoded data bit width; and writing the filled effective data into a secondary cache.
It should be noted that, when the data decoding device provided in the foregoing embodiment is used for decoding data, only the division of the foregoing functional modules is used for illustration, in practical application, the foregoing functional allocation may be performed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to perform all or part of the functions described above. In addition, the data decoding device and the data decoding method provided in the foregoing embodiments belong to the same concept, and specific implementation processes thereof are detailed in the method embodiments and are not described herein again.
Those skilled in the art will appreciate that the various aspects of the present disclosure may be implemented as a system, method, or program product. Accordingly, various aspects of the disclosure may be embodied in the following forms, namely: an entirely hardware embodiment, an entirely software embodiment (including firmware, micro-code, etc.) or an embodiment combining hardware and software aspects may be referred to herein as a "circuit," module "or" system.
An electronic device 400 according to such an embodiment of the present disclosure is described below with reference to fig. 4. The electronic device 400 shown in fig. 4 is merely an example and should not be construed as limiting the functionality and scope of application of the embodiments of the present disclosure.
As shown in fig. 4, the electronic device 400 is embodied in the form of a general purpose computing device. The components of electronic device 400 may include, but are not limited to: the at least one processing unit 410, the at least one memory unit 420, and a bus 430 connecting the various system components, including the memory unit 420 and the processing unit 410.
Wherein the storage unit stores program code that is executable by the processing unit 410 such that the processing unit 410 performs steps according to various exemplary embodiments of the present disclosure described in the above-described "exemplary methods" section of the present specification.
In some embodiments, the processing unit 410 may perform the following steps of the method embodiments described above: analyzing the appointed encoded data to obtain decoding information, wherein the decoding information comprises effective data and effective data length; writing the decoding information into a first-level cache; writing the effective data in the first-level cache into the second-level cache according to the length of the effective data stored in the first-level cache; and outputting the decoded data corresponding to the appointed encoded data through the secondary buffer memory.
The storage unit 420 may include readable media in the form of volatile storage units, such as Random Access Memory (RAM) 4201 and/or cache memory 4202, and may further include Read Only Memory (ROM) 4203.
The storage unit 420 may also include a program/utility 4204 having a set (at least one) of program modules 4205, such program modules 4205 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment.
The electronic device 400 may also communicate with one or more external devices 440 (e.g., keyboard, pointing device, bluetooth device, etc.), one or more devices that enable a user to interact with the electronic device 400, and/or any device (e.g., router, modem, etc.) that enables the electronic device 400 to communicate with one or more other computing devices. Such communication may occur through an input/output (I/O) interface 450. Also, electronic device 400 may communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the Internet, through network adapter 460. As shown in fig. 4, the network adapter 460 communicates with other modules of the electronic device 400 over the bus 430. It should be appreciated that although not shown, other hardware and/or software modules may be used in connection with electronic device 400, including, but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.
From the above description of embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or may be implemented in software in combination with the necessary hardware. Thus, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a U-disk, a mobile hard disk, etc.) or on a network, including several instructions to cause a computing device (may be a personal computer, a server, a terminal device, or a network device, etc.) to perform the method according to the embodiments of the present disclosure.
In an exemplary embodiment of the present disclosure, a computer-readable storage medium, which may be a readable signal medium or a readable storage medium, is also provided. On which a program product is stored which enables the implementation of the method described above of the present disclosure. In some possible implementations, various aspects of the disclosure may also be implemented in the form of a program product comprising program code for causing a terminal device to carry out the steps according to the various exemplary embodiments of the disclosure as described in the "exemplary methods" section of this specification, when the program product is run on the terminal device.
More specific examples of the computer readable storage medium in the present disclosure may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
In this disclosure, a computer readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, with readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Alternatively, the program code embodied on a computer readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
In particular implementations, the program code for carrying out operations of the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server. In the case of remote computing devices, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., connected via the Internet using an Internet service provider).
It should be noted that although in the above detailed description several modules or units of a device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit in accordance with embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into a plurality of modules or units to be embodied.
Furthermore, although the steps of the methods in the present disclosure are depicted in a particular order in the drawings, this does not require or imply that the steps must be performed in that particular order or that all illustrated steps be performed in order to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform, etc.
From the description of the above embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or may be implemented in software in combination with the necessary hardware. Thus, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a U-disk, a mobile hard disk, etc.) or on a network, including several instructions to cause a computing device (may be a personal computer, a server, a mobile terminal, or a network device, etc.) to perform the method according to the embodiments of the present disclosure.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any adaptations, uses, or adaptations of the disclosure following the general principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (10)
1. A method of decoding data, comprising:
analyzing the appointed encoded data to obtain decoding information, wherein the decoding information comprises effective data and effective data length;
writing the decoding information into a first-level cache;
writing the effective data in the first-level cache into a second-level cache according to the effective data length stored in the first-level cache;
and outputting the decoded data corresponding to the appointed encoded data through the secondary cache.
2. The method of claim 1, wherein parsing the specified encoded data to obtain decoded information comprises:
analyzing the encoded data based on at least one decoding block to obtain at least one analysis result, wherein the number of the decoding blocks is smaller than or equal to the minimum encoding unit of the appointed encoded data;
and splicing the at least one analysis result to obtain the decoding information.
3. The method of claim 1, wherein writing the decoded information to a level one cache comprises:
writing the effective data into the first-level cache;
and adding an information head for writing the effective data of the primary cache, wherein the information head is used for storing the effective data length.
4. The method of claim 3, wherein the writing the valid data in the primary cache to a secondary cache based on the valid data length stored in the primary cache comprises:
if the first-level cache is in a non-empty state, reading the effective data length in the information head;
and writing the effective data in the first-level cache into a second-level cache according to the effective data length and the preset decoding data bit width.
5. The method of claim 4, wherein writing the valid data in the primary cache to a secondary cache based on the valid data length and a preset decoded data bit width comprises:
and if the effective data length is greater than or equal to the decoding data bit width, writing the effective data with the length equal to the decoding data bit width in the first-level cache into the second-level cache.
6. The method of claim 4, wherein writing the valid data in the primary cache to a secondary cache based on the valid data length and a preset decoded data bit width comprises:
and if the effective data length is smaller than the decoding data bit width, waiting for writing new decoding information into the first-level cache until the sum of all the effective data lengths stored in the information head is greater than or equal to the decoding data bit width, and writing the effective data with the length equal to the decoding data bit width into the second-level cache.
7. The method of claim 4, wherein writing the valid data in the primary cache to a secondary cache based on the valid data length and a preset decoded data bit width comprises:
if the effective data is the last effective data obtained by analyzing the appointed coded data, filling the effective data so that the effective data length is the same as the bit width of the decoded data;
and writing the filled effective data into a secondary cache.
8. A data decoding apparatus, comprising:
the analysis module is used for analyzing the appointed encoded data to obtain decoding information, wherein the decoding information comprises effective data and effective data length;
the first writing module is used for writing the decoding information into the first-level cache;
the second writing module is used for writing the effective data in the first-level cache into a second-level cache according to the effective data length stored in the first-level cache;
and the output module is used for outputting the decoded data corresponding to the appointed encoded data through the secondary cache.
9. An electronic device, comprising:
a processor; and
a memory for storing executable instructions of the processor;
wherein the processor is configured to perform the method of any one of claims 1 to 7 via execution of the executable instructions.
10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the method of any of claims 1 to 7.
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