CN116016570A - Message processing method, device and system - Google Patents
Message processing method, device and system Download PDFInfo
- Publication number
- CN116016570A CN116016570A CN202211701573.8A CN202211701573A CN116016570A CN 116016570 A CN116016570 A CN 116016570A CN 202211701573 A CN202211701573 A CN 202211701573A CN 116016570 A CN116016570 A CN 116016570A
- Authority
- CN
- China
- Prior art keywords
- address
- memory
- message
- qpc
- cqc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Abstract
The application relates to a message processing method, device and system. The device comprises: the RDMA device is used for receiving and analyzing the command request, determining the QPC address of the command request according to the analysis result, reading the QPC from the first memory if the QPC of the command request is determined not to exist in the cache of the RDMA device, reading the MTT from the first memory if the MTT of the command request is determined not to exist in the cache of the RDMA device according to the index address when the type of the message to be sent is send, and generating the message according to the MTT. When RDMA equipment processes a message, when corresponding MTT, QPC and CQC are not in a cache, the message is read from the first memory, so that the service unloading of a target host is realized, the occupation of PCIE bandwidth is reduced, and the delay of command processing is reduced.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a method, an apparatus, and a system for processing a message.
Background
With the development of computer technology, a technology of processing a message by using an RDMA device, where the RDMA device can be applied to a DPU, and the DPU is used as a data processing unit, and the main purpose is to offload CPU traffic.
At present, in the process of processing a message by using an RDMA device, some pre-stored entries are usually required to obtain related data, and the determined data is used to perform message processing, for example, the QPC entries are used to obtain context information to obtain attribution of a message command, or the PBL entries are used to obtain a physical address corresponding to an access command, so as to realize access of a memory.
However, in the current technology of processing a message command by an RDMA device, the entries are usually stored in a host-side memory, so when the message command processing is performed by using the entries, the RDMA device is required to read the corresponding entries from the host memory through PCIE. Therefore, the current technology of performing packet command processing by the RDMA device may occupy PCIE bandwidth, and increase delay of command processing.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a message processing method, apparatus, and system that can reduce the latency of command processing.
The first aspect of the present invention provides a message processing apparatus, where the message processing apparatus communicates with a target host apparatus through a PCIE bus, the message processing apparatus includes a processor, an RDMA device, and a first memory, where,
the processor is used for communicating with a target host in the target host device and establishing MTT and QPC in the first memory;
the first memory is used for storing the MTT and the QPC;
the RDMA device is used for receiving and analyzing a command request of a sending message, determining a QPC address of the command request according to an analysis result, and if the QPC of the command request is determined to not exist in a cache of the RDMA device according to the QPC address, reading the QPC from the first memory according to the QPC address to obtain a base address of SQ;
the RDMA device is further configured to read and parse an SQ WQE from a second memory in the target host device based on the base address of the SQ, obtain a type of a message to be sent, a virtual address of a payload, and an index address of an MTT, and when the type of the message to be sent is a send message, if the MTT of the command request is determined not to be in a cache of the RDMA device according to the index address, read the MTT from the first memory, obtain a base address of a PBL, obtain a PBL according to the base address of the PBL, obtain a physical address of the payload according to the virtual address of the payload and the PBL, read the payload from the physical address, generate a message according to the payload, and send the message.
Preferably, the processor is further configured to establish a CQC in the first memory;
the first memory is also used for storing the CQC;
the RDMA device is further configured to receive and parse an ACK message, determine a CQC address of the command request according to the parsing result, and generate a CQE, and if it is determined that the CQC of the command request does not exist in the cache of the RDMA device according to the CQC address, read the CQC from the first memory according to the CQC address, obtain an address of the CQE, and write the CQE into the address of the CQE.
The second aspect of the present invention provides a message processing method, applied to a message processing apparatus, where the message processing apparatus communicates with a target host apparatus through a PCIE bus, and the message processing apparatus includes a processor, an RDMA device, and a first memory, where the method includes:
the processor communicates with a target host in the target host device and establishes an MTT and a QPC in the first memory;
the first memory stores the MTT and the QPC;
the RDMA equipment receives and analyzes a command request of a sending message, determines a QPC address of the command request according to an analysis result, and reads the QPC from the first memory according to the QPC address if the QPC of the command request is determined not to exist in a cache of the RDMA equipment according to the QPC address, so as to obtain a base address of SQ;
the RDMA device further reads and analyzes SQ WQE from a second memory in the target host device based on the base address of the SQ, obtains a type of a message to be sent, a virtual address of a payload and an index address of an MTT, when the type of the message to be sent is a send message, if the MTT of the command request is determined not to be in a cache of the RDMA device according to the index address, reads the MTT from the first memory, obtains a base address of a PBL, obtains a PBL according to the base address of the PBL, obtains a physical address of the payload according to the virtual address of the payload and the PBL, reads the payload from the physical address, generates a message according to the payload, and sends the message.
Preferably, the method further comprises:
the processor establishes a CQC in the first memory;
the first memory stores the CQC;
and the RDMA device receives and analyzes the ACK message, determines the CQC address of the command request and generates a CQE according to the analysis result, and reads the CQC from the first memory according to the CQC address to obtain the address of the CQE and writes the CQE into the address of the CQE if the CQC of the command request is determined not to be in the cache of the RDMA device according to the CQC address.
A third aspect of the present invention provides a message processing apparatus, the message processing apparatus communicating with a target host apparatus via a PCIE bus, the message processing apparatus including a processor, an RDMA device, and a first memory, wherein,
the processor is used for communicating with a target host in the target host device and establishing a QPC and an MTT in the first memory;
the first memory is used for storing the QPC and the MTT;
the RDMA device is used for receiving and analyzing a message to obtain a message type, a payload and a QPC address of the message, and when the message type is a send message, if the QPC of the message is determined to not exist in the cache of the RDMA device according to the QPC address, the QPC is read from the first memory to obtain a base address of RQ;
the RDMA device is further configured to read and parse an RQ WQE from a second memory in the target host device based on the base address of the RQ, obtain a virtual address of the payload and an index address of the MTT, and if it is determined that the MTT of the packet does not exist in the cache of the RDMA device according to the index address, read the MTT from the first memory, obtain a base address of a PBL, obtain a PBL of the packet according to the base address of the PBL, obtain a physical address of the payload according to the virtual address of the payload and the PBL, and write the payload to the physical address.
Preferably, the method comprises the steps of,
the processor is further configured to communicate with a target host in the target host device and establish a CQC in the first memory;
the RDMA device is further configured to receive and parse an ACK message, determine an address of a CQC according to the parsing result, and generate a CQE, and if it is determined that the CQC of the message is not in the cache of the RDMA device according to the address of the CQC, read the CQC from the first memory according to the address of the CQC, obtain the address of the CQE, and write the CQE into the second memory according to the address of the CQE.
A fourth aspect of the present invention provides a message processing method, where the message processing apparatus communicates with a target host apparatus through a PCIE bus, the message processing apparatus includes a processor, an RDMA device, and a first memory, where,
the processor is used for communicating with a target host in the target host device and establishing a QPC and an MTT in the first memory;
the RDMA device is used for receiving and analyzing a message to obtain a message type, a payload and a QPC address of the message, and when the message type is a send message, if the QPC of the message is determined to not exist in the cache of the RDMA device according to the QPC address, the QPC is read from the first memory to obtain a base address of RQ;
the RDMA device is further configured to read and parse an RQ WQE from a second memory in the target host device based on the base address of the RQ, obtain a virtual address of the payload and an index address of the MTT, and if it is determined that the MTT of the packet does not exist in the cache of the RDMA device according to the index address, read the MTT from the first memory, obtain a base address of a PBL, obtain a PBL of the packet according to the base address of the PBL, obtain a physical address of the payload according to the virtual address of the payload and the PBL, and write the payload to the physical address.
Preferably, the method further comprises:
the processor communicates with a target host in the target host device and establishes a CQC in the first memory;
and the RDMA device receives and analyzes the ACK message, determines the address of the CQC according to the analysis result and generates a CQE, and if the CQC of the message is determined not to be in the cache of the RDMA device according to the address of the CQC, reads the CQC from the first memory according to the address of the CQC, obtains the address of the CQE, and writes the CQE into the second memory according to the address of the CQE.
A fifth aspect of the present invention provides a message processing system comprising a target host device and a message processing device as described above.
A sixth aspect of the present invention provides a message processing system, comprising a target host device and a 5-message processing device as described above
The beneficial effects are that: by storing the MTT, QPC and CQC associated with MR registration in the first memory of the message processing apparatus, when the RDMA device processes the message, the corresponding MTT, QPC and CQC are not in the cache, only need to be read from the first memory, and can be read from the host memory without PCIE
The corresponding table entry is read, so that the occupation of PCIE0 bandwidth can be reduced and the delay of command processing is reduced while the target host CPU service is unloaded.
Drawings
FIG. 1 is a schematic diagram of a message processing apparatus according to an embodiment;
FIG. 2 is a schematic diagram of a message processing apparatus according to an embodiment;
FIG. 3 is a flow chart of a message processing method in one embodiment;
FIG. 4 is a flow chart of a message processing method in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples of embodiment 0. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
In a first embodiment of the present invention, as shown in fig. 1, a message processing apparatus 2 communicates with a target host apparatus 1 through a PCIE bus, the target host apparatus is located at a server side, and the message is sent to the target host apparatus
The processing apparatus is located at a device side, where the packet processing apparatus 2 includes a processor 21, a first memory 22 and a 5RDMA device 23, where the processor 21 is configured to communicate with a target host 11 in the target host apparatus 1 and establish a QPC and an MTT in the first memory 22, where the first memory 22 is configured to store the QPC and the MTT, where the RDMA device is configured to receive and parse a command request for sending a packet, determine a QPC address of the command request according to a parse result, determine that the QPC address of the command request does not exist in a buffer of the RDMA device 23 according to the QPC address, read the QPC from the first memory 22 according to the QPC address, obtain a base address of the SQ, read and parse the SQ WQE from a second memory 12 in the target host apparatus based on the base address, obtain a virtual address of a packet to be sent, and an index of the MTT, determine a virtual address of the packet to be sent, and obtain a pbload from the physical address of the pbload, and obtain the base address of the packet according to the pbload when the type of the packet to be sent is the pbload, and obtain the base address of the physical address from the pbload.
Specifically, the target host device 1 includes a target host 11 and a second memory 12, where the target host 11 is a CPU on the server side, and the second memory 12 may be a DDR. The message processing apparatus may be DPU (Data Processing Unit), where the processor 21 is a CPU or other processor core, and the first memory 22 may be a DDR.
The RDMA device 23 and the target host 11 communicate through a Queue Pair (QP), where one QP includes a Send Queue (SQ) and a Receive Queue (RQ). When the user needs to send a request, the request is split into one Work Queue Element (WQE) and sent into SQ. According to the IB protocol, QP is a virtual interface between hardware and software, QP is a queue structure that stores tasks (WQEs) issued by software to hardware in order. QPC (Queue Pair Context) is used to store QP related attributes.
When the Memory Region is performed, the access authority of the Memory needs to be specified when the Memory is registered, and the access authority information is stored in Memory Protection Tables (MPT for short) for authority verification when the user requests.
Since DMA is only accessible from physical addresses, a virtual to physical memory mapping table (PBL) of the target memory region needs to be maintained, which is stored in Memory Translation Table (MTT).
Payload: the part of data recorded with information is usually transmitted in batches to make the data transmission more reliable, and certain auxiliary information is added to the head and tail of each batch of data, so as to form a basic transmission unit in a transmission channel.
As shown in fig. 2, a target Host (i.e., host-side CPU) in the target Host device establishes communication with a processor (device-side CPU) in the message processing device, and the target Host registers a memory in a second memory (Host-side memory) (Memory Registeration). The device-side CPU is configured to establish, in a first memory (i.e., a device-side memory), an MTT and an MPT corresponding to the memory registration. The RDMA device establishes connection with a Host side CPU and a device side CPU, and the Host side CPU establishes QPC and CQC in a device side memory. Note that QPC is used to store, but not limited to, PI/CI pointers to SQ/RQ and base addresses to SQ/RQ, and CQC is used to store, but not limited to, PI/CI pointers to CQ and base addresses to CQ. And the target Host writes the SQ WQE into the memory at the Host side. The CPU at the Host side issues a dorbell to the RDMA equipment, the RDMA equipment is informed to prepare to send a message, the RDMA equipment receives the command request and analyzes the command request, the RDMA equipment obtains a QPC address corresponding to the command request according to the analysis result, whether the QPC of the command request is in a cache of the RDMA equipment or not is determined according to the QPC address, if the QPC corresponding to the command request is in the cache of the RDMA equipment, the QPC is read from the cache of the RDMA equipment, if the QPC is not in the cache of the RDMA equipment, the RDMA equipment obtains the QPC from a memory at the equipment side according to the address of the QPC, and the QPC is read to obtain the base address of the SQ and the PI/CI pointer. The RDMA device also reads the SQ WQE from the second memory according to the base address of the SQ and the PI/CI pointer, and analyzes the read SQ WQE to obtain the message type of the message to be sent, the virtual address of the payload, the index address of the MPT and the index address of the MTT. When the type of the message to be sent is send message, determining whether the MPT of the command request is in the cache of the RDMA device according to the index address of the MPT, if not, reading the MPT from the memory of the device side, determining whether the access right exists according to the MPT, when the access right exists, if the MTT of the command request is determined not to be in the cache of the RDMA device according to the index address, reading the MTT from the memory of the device side, obtaining the base address of the PBL, obtaining the PBL according to the base address of the PBL, obtaining the physical address of the payload according to the virtual address of the payload and the PBL, reading the payload from the physical address, thereby generating the message to be sent, and sending the message.
Specifically, the RDMA device analyzes the command request, obtains QPN (Queue Pair Number) and function ID corresponding to the command request, and determines the QPC address corresponding to the command request according to the QPN and function ID. The RDMA device determines whether the QPC is in a cache of the RDMA device according to the QPC address, if the QPC is in the cache of the RDMA device, the RDMA device directly reads the QPC from the cache, if the QPC is not in the cache of the RDMA device, the QPC is read from the first memory, after the QPC is read, a base address and a PI/CI pointer of the SQ can be obtained, the SQ WQE is read from the second memory according to the base address and the PI/CI pointer of the SQ, the SGE is carried in the SQ WQE, the virtual address and the key of the packet in the SGE are contained in the virtual address and the type of the packet to be transmitted, the RDMA device analyzes the SQ WQE, obtains the type of the packet to be transmitted, the virtual address and the key of the packet to be transmitted, the data for checking whether the user has access permission or not in the key, when the type of the packet to be transmitted is the sender message, the MPT is the MPT according to the index address of the MPT, if the packet is not contained in the PBO, the packet is not contained in the first memory, the base address of the packet is obtained from the PBO, the packet is obtained from the base address and the PBO is obtained according to the access permission, and if the data is not contained in the base address of the packet to be obtained from the physical address, and the base address is obtained from the physical device, and if the access permission is obtained from the base address is obtained from the physical device.
In a specific embodiment, the processor is further configured to establish a CQC in a first memory, where the first memory is further configured to store the CQC, and the RDMA device is further configured to receive an ACK message sent by a message receiver (i.e., an opposite end), parse the ACK message, determine a CQC address of the command request according to the parsing result, generate a CQE, determine that the CQC of the command request is not in a cache of the RDMA device according to the CQC address, read the CQC from the first memory according to the CQC address, obtain the CQE address, and write the CQE to the address of CQE (Completion Queue Element).
According to the IB protocol, the opposite terminal returns an ACK message to the local terminal when receiving the send message, and the ACK message is used for indicating whether the send message is executed or not.
According to the message processing device in the embodiment of the invention, MTT, MPT, QPC and CQC related to MR registration are stored in the first memory of the message processing device, when RDMA equipment processes a message, and when corresponding MTT, MPT, QPC and CQC are not in a cache, only the corresponding items are read from the first memory, and the corresponding items can be read from the host memory without PCIE, so that the purpose of unloading the target host CPU service is achieved, the occupation of PCIE bandwidth can be reduced, and the delay of command processing is further reduced.
Based on the first embodiment of the present invention, a second embodiment of the present invention provides a message processing method, as shown in fig. 3, including the following steps:
s11, the processor is used for communicating with a target host in the target host device and establishing MTT and QPC in the first memory;
s12, the RDMA device receives and analyzes a command request, determines a QPC address of the command request according to an analysis result, reads a QPC table from the first memory according to the QPC address if the QPC to be used is determined not to exist in the RDMA cache according to the QPC address, obtains a base address of a sending queue, reads and analyzes SQ WQE from the base address in the second memory of the target host device, obtains a type of a message to be sent, a virtual address of a payload and an index address of an MPT, reads the virtual address of the payload from the physical payload according to the virtual address of the payload and the physical payload of the PBL table, and sends the message according to the physical payload if the MPT table to be used is determined not to exist in the RDMA cache of the RDMA device according to the index address, and obtains a base address of a PBL table according to the PBL.
In a specific embodiment, the processor further communicates with a target host in the target host device, establishes a CQC table in a first memory, further receives and parses a CQE, determines an address of the CQC according to the parsing result, and if it is determined that a CQC to be used is not in the buffer of the RDMA device according to the address of the CQC, reads the CQC table from the address of the CQC in the first memory, obtains the address of the CQE, and writes the CQE into the second memory according to the address of the CQE.
According to the message processing method in the embodiment of the invention, MTT, MPT, QPC and CQC related to MR registration are stored in the first memory of the message processing device, when the RDMA device processes the message, when the corresponding MTT, MPT, QPC and CQC are not in the cache of the RDMA device, the corresponding table entry is only required to be read from the first memory, and the corresponding table entry can be read from the host memory without PCIE, so that the purpose of unloading the target host CPU service is realized, the occupation of PCIE bandwidth can be reduced, and the delay of command processing is reduced.
In a third embodiment of the present invention, as shown in fig. 1, the packet processing device communicates with a target host device through a PCIE bus, where the packet processing device includes a processor, an RDMA device, and a first memory, where the processor is configured to communicate with the target host in the target host device, and establish a QPC and an MTT in the first memory, where the RDMA device is configured to receive and parse a packet, obtain a packet type, a payload, and a QPC address of the packet, when the packet type is a send packet, if it is determined according to the QPC address that the QPC of the packet does not exist in a buffer of the RDMA device, the QPC is read from the first memory, a base address of the RQ is obtained, and where the RDMA device is further configured to read and parse a wgqe from a second memory in the target host device based on the base address of the RQ, obtain a virtual address of the payload and an index of the MTT, and if it is determined according to the QPC address that the QPC address does not exist in the first memory, obtain a pbol from the base address of the RDMA device, and obtain the physical address from the pbol according to the pbol.
The following description refers to fig. 2. The method comprises the steps that a target Host (namely a Host side CPU) in a target Host device communicates with a processor (namely a device side CPU) in a message processing device, the Host side CPU carries out MR registration in a second memory (namely the Host side memory), the device side CPU establishes MPT and MTT in a first memory (the device side memory), the Host side CPU writes RQ WQE into the device side memory, the RDMA device receives a message sent by an opposite-end RDMA device and analyzes the received message, a payload of the message, a type of the message and QPN (quick response) are obtained, when the type of the message is a send message, whether the QPC of the message is in a cache of the RDMA device is determined according to the QPC address, if the QPC is not in the cache of the RDMA device, the QPC is obtained from the device side memory, the address of the MPT and the MPT is included in the SEG, the address of the SEG is used for identity verification, the PBO is determined according to the PBO address of the PBO, if the PBO is not in the read, and if the PBO is not in the read from the read address, and if the PBO is not in the read address is not in the read from the read side, and if the PBO is not in the read from the base address, and if the PBO is not in the read from the read side.
In a specific embodiment, the RDMA device receives and parses an ACK packet, determines an address of a CQC according to the parsing result, and generates a CQE, and if it is determined that the CQC of the packet is not in the buffer of the RDMA device according to the address of the CQC, reads the CQC from the first memory according to the address of the CQC, obtains the address of the CQE, and writes the CQE into the second memory according to the address of the CQE.
Based on the third embodiment of the present invention, a fourth embodiment of the present invention provides a method for processing a message, as shown in fig. 4, where the method includes the following steps:
s21, the processor is used for communicating with a target host in the target host device and establishing a QPC and an MTT in the first memory;
s22, the RDMA device is used for receiving and analyzing a message to obtain a message type, a payload and a QPC address of the message, when the message type is a send message, if the QPC of the message is determined to not exist in a cache of the RDMA device according to the QPC address, the QPC is read from the first memory to obtain a base address of the RQ, the RDMA device is also used for reading and analyzing the RQ WQE from a second memory in the target host device based on the base address of the RQ to obtain a virtual address of the payload and an index address of the MTT, if the MTT of the message is determined to not exist in the cache of the RDMA device according to the index address, the MTT is read from the first memory to obtain a base address of the PBL, the PBL of the message is obtained according to the base address of the PBL, the virtual address of the payload and the physical payload is obtained according to the PBL, and the physical payload is written to the physical address.
In one embodiment, the processor communicates with a target host in the target host device and establishes a CQC in the first memory;
the first memory stores the CQC;
and the RDMA device receives and analyzes the ACK, determines the address of the CQC according to the analysis result and generates a CQE, and if the CQC of the message is determined not to be in the cache of the RDMA device according to the address of the CQC, reads the CQC from the first memory according to the address of the CQC, obtains the base address of the CQ, reads the CQC table from the first memory according to the base address of the CQ, obtains the base address of the CQE, and writes the CQE into the second memory according to the base address of the CQE.
According to the message processing method in the embodiment of the invention, MTT, MPT, QPC and CQC related to MR registration are stored in the first memory of the message processing device, when the RDMA equipment processes the message, when the corresponding MTT, MPT, QPC and CQC are not in the cache, only the corresponding table entry is read from the first memory, and the corresponding table entry can be read from the host memory without PCIE, so that the target host CPU service is unloaded, the occupation of PCIE bandwidth can be reduced, and the delay of command processing is reduced.
Based on the first embodiment of the present invention, a fifth embodiment of the present invention provides a message processing system, which includes: target host device and message processing device as described in example one.
The target host device is the target host device in the first embodiment, and thus will not be described herein.
Based on the third embodiment of the present invention, a sixth embodiment of the present invention provides a message processing system, which includes: target host device and message processing device as described in example three.
The target host device is the target host device in the third embodiment, and thus will not be described herein.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the present application. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application shall be subject to the appended claims.
Claims (10)
1. A message processing apparatus is characterized in that the message processing apparatus communicates with a target host apparatus through a PCIE bus, the message processing apparatus comprises a processor, an RDMA device and a first memory, wherein,
the processor is used for communicating with a target host in the target host device and establishing MTT and QPC in the first memory;
the first memory is used for storing the MTT and the QPC;
the RDMA device is used for receiving and analyzing a command request of a sending message, determining a QPC address of the command request according to an analysis result, and if the QPC of the command request is determined to not exist in a cache of the RDMA device according to the QPC address, reading the QPC from the first memory according to the QPC address to obtain a base address of SQ;
the RDMA device is further configured to read and parse an SQ WQE from a second memory in the target host device based on the base address of the SQ, obtain a type of a message to be sent, a virtual address of a payload, and an index address of an MTT, and when the type of the message to be sent is a send message, if the MTT of the command request is determined not to be in a cache of the RDMA device according to the index address, read the MTT from the first memory, obtain a base address of a PBL, obtain a PBL according to the base address of the PBL, obtain a physical address of the payload according to the virtual address of the payload and the PBL, read the payload from the physical address, generate a message according to the payload, and send the message.
2. The apparatus according to claim 1, wherein:
the processor is further configured to establish a CQC in the first memory;
the first memory is also used for storing the CQC;
the RDMA device is further configured to receive and parse an ACK message, determine a CQC address of the command request according to the parsing result, and generate a CQE, and if it is determined that the CQC of the command request does not exist in the cache of the RDMA device according to the CQC address, read the CQC from the first memory according to the CQC address, obtain an address of the CQE, and write the CQE into the address of the CQE.
3. The message processing method is characterized by being applied to a message processing device, wherein the message processing device is communicated with a target host device through a PCIE bus, the message processing device comprises a processor, an RDMA device and a first memory, and the method comprises the following steps:
the processor communicates with a target host in the target host device and establishes an MTT and a QPC in the first memory;
the first memory stores the MTT and the QPC;
the RDMA equipment receives and analyzes a command request of a sending message, determines a QPC address of the command request according to an analysis result, and reads the QPC from the first memory according to the QPC address if the QPC of the command request is determined not to exist in a cache of the RDMA equipment according to the QPC address, so as to obtain a base address of SQ;
the RDMA device further reads and analyzes SQ WQE from a second memory in the target host device based on the base address of the SQ, obtains a type of a message to be sent, a virtual address of a payload and an index address of an MTT, when the type of the message to be sent is a send message, if the MTT of the command request is determined not to be in a cache of the RDMA device according to the index address, reads the MTT from the first memory, obtains a base address of a PBL, obtains a PBL according to the base address of the PBL, obtains a physical address of the payload according to the virtual address of the payload and the PBL, reads the payload from the physical address, generates a message according to the payload, and sends the message.
4. A method according to claim 3, characterized in that the method further comprises:
the processor establishes a CQC in the first memory;
the first memory stores the CQC;
and the RDMA device receives and analyzes the ACK message, determines the CQC address of the command request and generates a CQE according to the analysis result, and reads the CQC from the first memory according to the CQC address to obtain the address of the CQE and writes the CQE into the address of the CQE if the CQC of the command request is determined not to be in the cache of the RDMA device according to the CQC address.
5. A message processing apparatus is characterized in that the message processing apparatus communicates with a target host apparatus through a PCIE bus, the message processing apparatus comprises a processor, an RDMA device and a first memory, wherein,
the processor is used for communicating with a target host in the target host device and establishing a QPC and an MTT in the first memory;
the first memory is used for storing the QPC and the MTT;
the RDMA device is used for receiving and analyzing a message to obtain a message type, a payload and a QPC address of the message, and when the message type is a send message, if the QPC of the message is determined to not exist in the cache of the RDMA device according to the QPC address, the QPC is read from the first memory to obtain a base address of RQ;
the RDMA device is further configured to read and parse an RQ WQE from a second memory in the target host device based on the base address of the RQ, obtain a virtual address of the payload and an index address of the MTT, and if it is determined that the MTT of the packet does not exist in the cache of the RDMA device according to the index address, read the MTT from the first memory, obtain a base address of a PBL, obtain a PBL of the packet according to the base address of the PBL, obtain a physical address of the payload according to the virtual address of the payload and the PBL, and write the payload to the physical address.
6. The apparatus according to claim 5, wherein:
the processor is further configured to communicate with a target host in the target host device and establish a CQC in the first memory;
the RDMA device is further configured to receive and parse an ACK message, determine an address of a CQC according to the parsing result, and generate a CQE, and if it is determined that the CQC of the message is not in the cache of the RDMA device according to the address of the CQC, read the CQC from the first memory according to the address of the CQC, obtain the address of the CQE, and write the CQE into the second memory according to the address of the CQE.
7. A message processing method is characterized in that the message processing device is communicated with a target host device through a PCIE bus, the message processing device comprises a processor, RDMA equipment and a first memory, wherein,
the processor is used for communicating with a target host in the target host device and establishing a QPC and an MTT in the first memory;
the RDMA device is used for receiving and analyzing a message to obtain a message type, a payload and a QPC address of the message, and when the message type is a send message, if the QPC of the message is determined to not exist in the cache of the RDMA device according to the QPC address, the QPC is read from the first memory to obtain a base address of RQ;
the RDMA device is further configured to read and parse an RQ WQE from a second memory in the target host device based on the base address of the RQ, obtain a virtual address of the payload and an index address of the MTT, and if it is determined that the MTT of the packet does not exist in the cache of the RDMA device according to the index address, read the MTT from the first memory, obtain a base address of a PBL, obtain a PBL of the packet according to the base address of the PBL, obtain a physical address of the payload according to the virtual address of the payload and the PBL, and write the payload to the physical address.
8. The method of claim 7, wherein the method further comprises:
the processor communicates with a target host in the target host device and establishes a CQC in the first memory;
and the RDMA device receives and analyzes the ACK message, determines the address of the CQC according to the analysis result and generates a CQE, and if the CQC of the message is determined not to be in the cache of the RDMA device according to the address of the CQC, reads the CQC from the first memory according to the address of the CQC, obtains the address of the CQE, and writes the CQE into the second memory according to the address of the CQE.
9. A message processing system comprising a target host device and a message processing device according to any of claims 1-2.
10. A message processing system comprising a target host device and a message processing device as claimed in any one of claims 5 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211701573.8A CN116016570A (en) | 2022-12-29 | 2022-12-29 | Message processing method, device and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211701573.8A CN116016570A (en) | 2022-12-29 | 2022-12-29 | Message processing method, device and system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116016570A true CN116016570A (en) | 2023-04-25 |
Family
ID=86020453
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211701573.8A Pending CN116016570A (en) | 2022-12-29 | 2022-12-29 | Message processing method, device and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116016570A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116303173A (en) * | 2023-05-19 | 2023-06-23 | 深圳云豹智能有限公司 | Method, device and system for reducing RDMA engine on-chip cache and chip |
-
2022
- 2022-12-29 CN CN202211701573.8A patent/CN116016570A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116303173A (en) * | 2023-05-19 | 2023-06-23 | 深圳云豹智能有限公司 | Method, device and system for reducing RDMA engine on-chip cache and chip |
| CN116303173B (en) * | 2023-05-19 | 2023-08-08 | 深圳云豹智能有限公司 | Method, device and system for reducing RDMA engine on-chip cache and chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7930437B2 (en) | Network adapter with shared database for message context information | |
| US11755513B2 (en) | Data processing and writing method based on virtual machine memory identification field and devise | |
| CN111221758A (en) | Method and computer equipment for processing remote direct memory access request | |
| CN111064680B (en) | Communication device and data processing method | |
| US20230267022A1 (en) | Network interface card, storage apparatus, and packet receiving method and sending method | |
| CN111641566B (en) | Data processing method, network card and server | |
| CN116016570A (en) | Message processing method, device and system | |
| CN115964319A (en) | Data processing method for remote direct memory access and related product | |
| CN114089920A (en) | Data storage method and device, readable medium and electronic equipment | |
| CN115639947A (en) | Data writing method, data reading method, device, equipment, system and medium | |
| CN109478171B (en) | Improving throughput in openfabics environment | |
| CN109857553B (en) | Memory management method and device | |
| US10489350B2 (en) | Data compression with inline compression metadata | |
| CN115827549A (en) | Network interface card, message sending method and storage device | |
| CN116303173B (en) | Method, device and system for reducing RDMA engine on-chip cache and chip | |
| US9769093B2 (en) | Apparatus and method for performing InfiniBand communication between user programs in different apparatuses | |
| US20200341653A1 (en) | Method, network adapter and computer program product for processing data | |
| EP3913488B1 (en) | Data processing method and device | |
| CN113326151A (en) | Inter-process communication method, device, equipment, system and storage medium | |
| CN116303195A (en) | PCIE communication | |
| CN117242763A (en) | Network interface card for caching file system internal structure | |
| CN116601616A (en) | Data processing device, method and related equipment | |
| CN114116243A (en) | Multi-core-based data processing method and device | |
| CN116868178A (en) | Remote direct memory access communication method in network and corresponding controller | |
| CN114079675A (en) | Message processing method and device, terminal equipment and mobile broadband internet access equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |