CN116016072B - Zero intermediate frequency structure low-complexity MSK quadrature demodulation device and demodulation method thereof - Google Patents

Zero intermediate frequency structure low-complexity MSK quadrature demodulation device and demodulation method thereof Download PDF

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CN116016072B
CN116016072B CN202310280199.7A CN202310280199A CN116016072B CN 116016072 B CN116016072 B CN 116016072B CN 202310280199 A CN202310280199 A CN 202310280199A CN 116016072 B CN116016072 B CN 116016072B
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phase
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CN116016072A (en
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王仁智
韩杰
张令军
段玉龙
文佳伟
张春泽
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Zhenjiang Xunlian Technology Co.,Ltd.
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Tianjin Xunlian Technology Co ltd
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Abstract

The invention provides a low-complexity MSK orthogonal demodulation device with a zero intermediate frequency structure and a demodulation method thereof, wherein the low-complexity MSK orthogonal demodulation device comprises an orthogonal down-conversion module, a complex square module, a phase-locked loop module, a conjugate multiplication module, an orthogonal demodulation module, an integral zero clearing pulse generation module, a first integral module, a second integral module, a first judgment module, a second judgment module, an exclusive OR module and a code synchronization module. The invention has the beneficial effects that: compared with the traditional incoherent demodulation method, the method has a lower demodulation threshold; the quadrature demodulation method adopting the zero intermediate frequency structure avoids the use of a band-pass filter, innovatively converts multiplication operation of a complex domain into phase addition and subtraction operation, and does not need an additional complex code synchronization loop circuit in the implementation process; the method effectively reduces the volume of hardware and the resource consumption of the FPGA, and simultaneously has very high carrier capturing speed and phase tracking precision under the condition of reducing the resource consumption and facilitating the hardware realization, and is particularly suitable for remote high-code-rate telemetry receivers.

Description

Zero intermediate frequency structure low-complexity MSK quadrature demodulation device and demodulation method thereof
Technical Field
The invention belongs to the technical field of aerospace telemetry, and particularly relates to a low-complexity MSK quadrature demodulation device with a zero intermediate frequency structure and a demodulation method thereof.
Background
FSK modulation has the characteristics of small influence by the tail flame of an aircraft, strong phase noise resistance and the like, and is the most widely used telemetry modulation system in the aerospace field. Minimum Shift Keying (MSK) is used as a special FSK, has the characteristics of constant envelope, continuous phase, minimum bandwidth and strict orthogonality, and gradually becomes one research direction of advanced telemetry.
Minimum Shift Keying (MSK) demodulation methods are classified into coherent demodulation and incoherent demodulation, and the incoherent demodulation method does not require a process of extracting a carrier wave by taking the carrier wave of a received signal as a reference. The commonly used incoherent demodulation algorithm mainly comprises a zero-crossing detection method, an envelope detection method and a differential detection method. Although these methods are relatively simple to implement, they are generally resistant to noise. Under the condition of low signal-to-noise ratio, coherent demodulation has obvious performance advantages, and can realize telemetry communication with longer distance and higher bandwidth.
Aiming at the defects of high resource consumption and complex structure of the traditional coherent demodulation algorithm, the algorithm is applicable to a zero intermediate frequency structure receiver, has a simple structure, can realize small-volume design, and reduces FPGA resource consumption by optimizing the algorithm.
Disclosure of Invention
In view of this, the present invention aims to provide a low-complexity MSK quadrature demodulation device with zero intermediate frequency structure and a demodulation method thereof, so as to solve the disadvantages of high resource consumption and complex structure of the existing coherent demodulation algorithm.
In order to achieve the above purpose, the technical scheme of the invention is realized as follows:
the low-complexity MSK orthogonal demodulation device with the zero intermediate frequency structure comprises an orthogonal down-conversion module, a complex square module, a phase-locked loop module, a conjugate multiplication module, an orthogonal demodulation module, an integral zero clearing pulse generation module, a first integral module, a second integral module, a first judgment module, a second judgment module, an exclusive-or module and a code synchronization module, wherein the output end of the orthogonal down-conversion module is connected with the input end of the complex square module and the input end of the conjugate multiplication module in a signal mode, the output end of the complex square module is connected with the input end of the phase-locked loop module in a signal mode, the output end of the phase-locked loop module is connected with the input end of the conjugate multiplication module and the input end of the orthogonal demodulation module in a signal mode, the output end of the conjugate multiplication module is connected with the input end of the orthogonal demodulation module in a signal mode, the output end of the orthogonal demodulation module is connected with the input end of the first integral zero clearing pulse generation module in a signal mode, the output end of the orthogonal demodulation module in a signal mode, the output end of the integral zero clearing pulse generation module in a signal mode is connected with the input end of the first integral module, the second integral module in a signal mode, and the code synchronization module in a signal mode, the output end of the integral zero intermediate frequency structure is connected with the input end of the first integral zero intermediate frequency structure.
Further, the phase-locked loop module comprises an F1 frequency phase-locked loop unit, an F0 frequency phase-locked loop unit, a 2bit first right shift unit, a 2bit second right shift unit, an adding unit, a subtracting unit, a first CORDIC unit and a second CORDIC unit, wherein the input end of the F1 frequency phase-locked loop unit and the input end of the F0 frequency phase-locked loop unit are connected with the output end of the complex square module, the output end of the F1 frequency phase-locked loop unit is connected to the input end of the 2bit first right shift unit, the output end of the F0 frequency phase-locked loop unit is connected to the input end of the 2bit second right shift unit, the output end of the 2bit first right shift unit is connected with the input end of the adding unit and the input end of the subtracting unit, the output end of the adding unit is connected with the input end of the first CORDIC unit, and the output end of the subtracting unit is connected with the output end of the second CORDIC unit.
Further, the F1 frequency phase-locked loop unit comprises a complex multiplier, a CORDIC phase detector, a low-pass filter, an accumulator and a DDS generator, wherein the input end of the complex multiplier is in signal connection with the output end of the complex squaring module, the output end of the complex multiplier is connected to the input end of the DDS generator through the CORDIC phase detector, the low-pass filter and the accumulator in sequence, and the output end of the DDS generator is in signal connection with the input end of the complex multiplier.
Further, the demodulation method of the low-complexity MSK orthogonal demodulation device with the zero intermediate frequency structure comprises the following steps:
s1, starting a low-complexity MSK quadrature demodulation device with a zero intermediate frequency structure, transmitting an MSK modulation signal to an input end of a quadrature down-conversion module, processing the MSK modulation signal received by the input end of the quadrature down-conversion module to obtain a down-conversion signal, and transmitting the down-conversion signal to a complex square module and a conjugate multiplication module respectively;
s2, the down-conversion signal is processed by a complex squaring module to obtain a complex signal, the complex signal is transmitted to a phase-locked loop module, the phase-locked loop module processes the complex signal to generate a frequency offset compensation DDS and a demodulation synchronization DDS, the frequency offset compensation DDS is transmitted to a conjugate multiplication module, and the demodulation synchronization DDS is respectively transmitted to a quadrature demodulation module and an integral zero clearing pulse generation module;
s3, the conjugate multiplication module processes the frequency offset compensation DDS and the down-conversion signal in the step S1 to obtain a frequency offset compensation signal, and transmits the frequency offset compensation signal to the orthogonal demodulation module, and the orthogonal demodulation module processes the frequency offset compensation signal and the demodulation synchronization DDS to obtain an orthogonal demodulation signal, and transmits the real part of the orthogonal demodulation signal to the first integration module, and the imaginary part of the orthogonal demodulation signal to the second integration module;
the module for generating integral zero clearing pulse processes the demodulation synchronization DDS to obtain a pulse signal, the pulse signal is transmitted to the code synchronization module, the real part of the pulse signal is transmitted to the first integral module, and the imaginary part of the pulse signal is transmitted to the second integral module;
s4, the first integrating module processes the real part of the quadrature demodulation signal and the real part of the pulse signal to obtain a real part integrated signal, and the real part integrated signal is transmitted to the first judging module;
the second integrating module processes the imaginary part of the orthogonal demodulation signal and the imaginary part of the pulse signal to obtain an imaginary part integrated signal, and the imaginary part integrated signal is transmitted to the second judging module;
s5, the first judgment module outputs a real part judgment signal to the exclusive-or module after finishing binarization operation on the real part integral signal;
the second judgment module outputs an imaginary part judgment signal to the exclusive-or module after binarization operation is completed on the imaginary part integral signal;
s6, the exclusive-or module performs exclusive-or operation on the real part judgment signal and the imaginary part judgment signal, and then outputs an exclusive-or signal, and the exclusive-or signal is transmitted to the code synchronization module;
and S7, after the code synchronization module performs code synchronization on the pulse signal and the exclusive-or signal, outputting demodulation data.
Further, the expression of the MSK modulated signal in step S1 is:
Figure SMS_1
wherein->
Figure SMS_2
Representing MSK modulated signal, ">
Figure SMS_3
Is radio frequency point->
Figure SMS_4
For a single symbol time, +.>
Figure SMS_5
Is modulation information;
the expression of the down-converted signal in step S1 is:
Figure SMS_6
wherein, the method comprises the steps of, wherein,
Figure SMS_7
representing the down-converted signal, ">
Figure SMS_8
For modulating information +.>
Figure SMS_9
For a single symbol time, +.>
Figure SMS_10
Indicating the frequency deviation of telemetry transmitter and telemetry receiver, < >>
Figure SMS_11
To represent the phase offset of the telemetry transmitter and telemetry receiver.
Further, the expression of the complex signal in step S2 is:
Figure SMS_12
wherein->
Figure SMS_13
Representing a complex signal->
Figure SMS_14
For modulating information +.>
Figure SMS_15
For a single symbol time, +.>
Figure SMS_16
Indicating the frequency deviation of telemetry transmitter and telemetry receiver, < >>
Figure SMS_17
To represent the phase offset of the telemetry transmitter and telemetry receiver.
Further, the expression of the frequency offset compensation DDS in step S2 is:
Figure SMS_18
wherein->
Figure SMS_19
Representing frequency offset compensation DDS>
Figure SMS_20
Indicating the frequency deviation of telemetry transmitter and telemetry receiver, < >>
Figure SMS_21
To represent the phase offset of the telemetry transmitter and telemetry receiver.
Further, the expression of the demodulation synchronization DDS in step S2 is:
Figure SMS_22
wherein->
Figure SMS_23
Represents demodulation synchronization DDS, < >>
Figure SMS_24
Is a single symbol time.
Further, the expression of the frequency offset compensation signal in step S3 is:
Figure SMS_25
wherein->
Figure SMS_26
Representing the frequency offset compensation signal, ">
Figure SMS_27
For modulating information +.>
Figure SMS_28
Is a single symbol time.
Further, the real part expression of the pulse signal in step S3 is:
Figure SMS_29
wherein->
Figure SMS_30
Representing the real part,/-of the pulse signal>
Figure SMS_31
For a single symbol time, +.>
Figure SMS_32
Represents an integer>
Figure SMS_33
Representing a set of integers in a set;
the imaginary part of the pulse signal is:
Figure SMS_34
wherein->
Figure SMS_35
Representing the imaginary part,/-of the pulse signal>
Figure SMS_36
For a single symbol time, +.>
Figure SMS_37
Represents an integer>
Figure SMS_38
Representing a set of integers in a set.
Further, the expression of the real part integrated signal in step S4 is:
Figure SMS_39
wherein->
Figure SMS_40
Wherein->
Figure SMS_41
Representing the real integral signal,/->
Figure SMS_42
Representing the real part of the quadrature demodulated signal, < >>
Figure SMS_43
Represents an integer>
Figure SMS_44
Representing a set of integers in a set;
the expression of the imaginary integrated signal in step S4 is:
Figure SMS_45
wherein
Figure SMS_46
Wherein->
Figure SMS_47
Representing the imaginary integral signal>
Figure SMS_48
Representing the imaginary part of the quadrature demodulated signal, < >>
Figure SMS_49
Represents an integer>
Figure SMS_50
Representing a set of integers in a set.
Further, the expression of the real part decision signal in step S5 is:
Figure SMS_51
the method comprises the steps of carrying out a first treatment on the surface of the Wherein (1)>
Figure SMS_52
Representing the real part decision signal, sign () function is a signed function, +.>
Figure SMS_53
Representing the real integral signal;
the expression of the imaginary decision signal in step S5 is:
Figure SMS_54
the method comprises the steps of carrying out a first treatment on the surface of the Wherein (1)>
Figure SMS_55
Representing the imaginary decision signal, < >>
Figure SMS_56
Representing the imaginary integrated signal, the sign () function is a signed function.
Further, the expression of the exclusive-or signal in step S6 is:
Figure SMS_57
wherein->
Figure SMS_58
Representing exclusive or signal,/->
Figure SMS_59
Representing the real part decision signal,/->
Figure SMS_60
Representing the imaginary decision signal.
Further, the down-conversion signal in step S2 is processed by a complex squaring module to obtain a complex signal, the complex signal is transmitted to a phase-locked loop module, and the phase-locked loop module processes the complex signal to generate a frequency offset compensation DDS and a demodulation synchronization DDS, which specifically includes the following steps:
s21, the complex signals are respectively processed by an F1 frequency phase-locked loop unit and an F0 frequency phase-locked loop unit, wherein the locking frequency of the F1 frequency phase-locked loop unit is that
Figure SMS_61
Wherein->
Figure SMS_62
The F1 frequency phase-locked loop unit outputs the phase value of the current DDS to represent the code rate>
Figure SMS_63
And the phase value of the current DDS is +.>
Figure SMS_64
Transmitting to a 2bit first right shift unit;
wherein the locking frequency of the F0 frequency phase-locked loop unit is
Figure SMS_65
Wherein->
Figure SMS_66
The F0 frequency phase-locked loop unit outputs the phase value of the current DDS to represent the code rate>
Figure SMS_67
And the phase value of the current DDS is +.>
Figure SMS_68
Transmitting to a No. 2bit right shift unit;
s22, the phase value of the current DDS
Figure SMS_69
After entering a 2bit one-number right shift unit, the operation of dividing 4 is performed, and the expression of an output signal is +.>
Figure SMS_70
And output signal +>
Figure SMS_71
Transmitting to an adding unit and a subtracting unit;
phase value of current DDS
Figure SMS_72
After entering a No. 2bit right shift unit, the operation of dividing 4 is performed, and the expression of the output signal is +.>
Figure SMS_73
And output signal +>
Figure SMS_74
Transmitting to an adding unit and a subtracting unit;
s23, output signal
Figure SMS_75
And output signal +.>
Figure SMS_76
The adding unit performs an adding operation, and the output signal is
Figure SMS_77
And output signal +>
Figure SMS_78
Transmitting to a first CORDIC unit;
output signal
Figure SMS_79
And output signal +.>
Figure SMS_80
The subtraction unit performs subtraction operation, and the output signal is
Figure SMS_81
And output signal +>
Figure SMS_82
Transmitting to a second CORDIC unit;
s24, a CORDIC unit pair outputs signals
Figure SMS_83
Performing complex domain conversion and outputting a frequency offset compensation DDS;
output signal of CORDIC unit pair number two
Figure SMS_84
And performing complex domain conversion and outputting demodulation synchronization DDS.
Further, in the step S21, the complex signals are processed by the F1 frequency phase-locked loop unit and the F0 frequency phase-locked loop unit respectively, the complex signals are synchronously processed by the F1 frequency phase-locked loop unit and the F0 frequency phase-locked loop unit, and the complex signals are processed by the F1 frequency phase-locked loop unit, which specifically includes the following steps:
s211, performing complex frequency adjustment on the complex signal and the DDS signal output by the DDS generator in a complex multiplier to obtain a complex multiplication signal, and transmitting the complex multiplication signal to a CORDIC phase discriminator;
s212, after the phase of the complex multiplication signal is identified by the CORDIC phase discriminator, the CORDIC phase discriminator is obtained, and the CORDIC phase discriminator is transmitted to the low-pass filter;
s213, the low-pass filter carries out low-pass filtering on the CORDIC phase demodulation signals to obtain low-pass filtering signals, and the low-pass filtering signals are transmitted to the accumulator;
s214, step value of accumulator to low-pass filtering signal and F1 frequency
Figure SMS_85
After the bit accumulation generation, the phase value +.>
Figure SMS_86
And the phase value of the current DDS is +.>
Figure SMS_87
Transmitting the digital signal to a DDS generator and a 2bit first right shifting unit;
S215、DDSphase value of generator to current DDS
Figure SMS_88
After processing, the DDS signal is output to a complex multiplier.
Compared with the prior art, the zero intermediate frequency structure low-complexity MSK quadrature demodulation device and the demodulation method thereof have the following advantages:
compared with the traditional incoherent demodulation method, the zero intermediate frequency structure low-complexity MSK quadrature demodulation device and the demodulation method thereof have lower demodulation threshold, the zero intermediate frequency structure quadrature demodulation method adopted by the invention avoids the use of a band-pass filter, innovatively converts multiplication operation of a complex domain into phase addition and subtraction operation, does not need an additional complex code synchronization loop circuit in the implementation process, effectively reduces the hardware volume and the resource consumption of an FPGA, and simultaneously has very high carrier capturing speed and phase tracking precision under the condition of reducing the resource consumption and facilitating the hardware implementation, and is particularly suitable for a remote high-code rate telemetry receiver.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention. In the drawings:
FIG. 1 is a schematic flow chart of an overall method according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a frequency spectrum of a code rate according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a phase-locked loop module according to an embodiment of the invention;
FIG. 4 is a schematic diagram of an F1 frequency PLL unit according to an embodiment of the present invention;
fig. 5 is a waveform diagram of a quadrature demodulation signal according to an embodiment of the present invention;
fig. 6 is a schematic diagram illustrating a locking situation of a pll module according to embodiment 1 of the present invention.
Reference numerals illustrate:
1. a quadrature down-conversion module; 2. a complex squaring module; 3. a phase-locked loop module; 31. f1 frequency phase locked loop unit; 311. a complex multiplier; 312. a CORDIC phase detector; 313. a low pass filter; 314. an accumulator; 315. a DDS generator; 32. f0 frequency phase locked loop unit; 33. a 2bit one number right shift unit; 34. a 2bit No. two right shift unit; 35. an adding unit; 36. a subtraction unit; 37. a CORDIC unit number one; 38. a CORDIC unit No. two; 4. a conjugate multiplication module; 5. a quadrature demodulation module; 6. generating an integral zero clearing pulse module; 7. a first integration module; 8. a second integration module; 9. a first decision module; 10. a second decision module; 11. an exclusive or module; 12. and a code synchronization module.
Detailed Description
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art in a specific case.
The invention will be described in detail below with reference to the drawings in connection with embodiments.
As shown in fig. 1 to 6, the input signal of the zero intermediate frequency structure low complexity MSK quadrature demodulation device and the demodulation method thereof is an MSK modulation signal, the received MSK modulation signal passes through a quadrature down-conversion module 1 to complete the frequency spectrum shifting from a radio frequency signal to a baseband signal, the output signal is divided into two paths, one path passes through a complex squaring module 2 and then passes through a phase-locked loop module 3 to generate a frequency offset compensation DDS and a demodulation synchronization DDS, wherein the frequency offset compensation DDS is multiplied by a signal output by the conjugate multiplication module 4 and the quadrature down-conversion module 1 to complete the frequency offset compensation, the demodulation synchronization DDS and the output result of the conjugate multiplication module 4 complete quadrature demodulation at the quadrature demodulation module 5, the demodulation synchronization DDS enters a pulse signal of a product after generating an integral zero clearing pulse module 6 to respectively act on a first integral module 7 and a second integral module 8 to complete the integral zero clearing function, and act on a code synchronization module 12 to complete the bit synchronization operation. The first integrating module 7 performs integral operation on the in-phase component output by the quadrature demodulation module 5 according to the pulse generated by the integral zero clearing pulse generation module 6, the second integrating module 8 performs integral operation on the quadrature component output by the quadrature demodulation module 5 according to the pulse generated by the integral zero clearing pulse generation module 6, the output results of the first integrating module 7 and the second integrating module 8 respectively complete binarization operation through the first judging module 9 and the second judging module 10, the output of the first judging module 9 and the second judging module 10 complete parallel-serial conversion of demodulation data through the exclusive OR module 11, and then the data enters the code synchronization module 12 to complete synchronization operation in combination with the pulse generated by the integral zero clearing pulse generation module 6, so that demodulation data are recovered. The algorithm block diagram of the method is shown in fig. 1.
The input signal of the algorithm is an MSK modulated signal, and the expression is:
Figure SMS_89
wherein->
Figure SMS_90
Representing MSK modulated signal, ">
Figure SMS_91
Is radio frequency point->
Figure SMS_92
For a single symbol time, +.>
Figure SMS_93
For modulating information.
Signal signal
Figure SMS_94
The signal output after passing through the quadrature down-conversion module 1 is in a complex form, and the expression is as follows:
Figure SMS_95
wherein->
Figure SMS_96
For modulating information +.>
Figure SMS_97
For a single symbol time, +.>
Figure SMS_98
Indicating the frequency deviation of telemetry transmitter and telemetry receiver, < >>
Figure SMS_99
To represent the phase offset of the telemetry transmitter and telemetry receiver.
Signal signal
Figure SMS_102
The signal expression after the complex squaring module 2 is +.>
Figure SMS_103
Wherein->
Figure SMS_107
For modulating information +.>
Figure SMS_101
For a single symbol time, +.>
Figure SMS_104
Indicating the frequency deviation of telemetry transmitter and telemetry receiver, < >>
Figure SMS_106
To represent the phase offset of the telemetry transmitter and telemetry receiver. The frequency spectrum at this time is shown in FIG. 2, where the two sinusoidal components are +.>
Figure SMS_108
，/>
Figure SMS_100
Wherein->
Figure SMS_105
Representing the code rate.
Signal signal
Figure SMS_110
Extracting frequencies of +.about.respectively through phase-locked loop module 3>
Figure SMS_113
，/>
Figure SMS_116
Of (2) sinusoidal signals, wherein->
Figure SMS_109
Representing the code rate and thus calculating the frequency offset of the telemetry transmitter and telemetry receiver>
Figure SMS_112
And phase deviation->
Figure SMS_115
The signal expression outputted at this time is +.>
Figure SMS_117
The signal enters a conjugate multiplication module 4 to complete complex conjugate multiplication operation for carrier synchronization. At the same time, a demodulation signal is outputted from the phase-locked loop module 3 for performing quadrature demodulation, the expression of the signal is +.>
Figure SMS_111
Wherein->
Figure SMS_114
For a single symbol time, the signal is coupled to both the quadrature demodulation block 5 and the block 6 that generates the integral clear pulse. This part is an important element and main innovation point of the present invention, and the composition of the phase-locked loop module 3 part is described here, as shown in detail in fig. 3.
Signal signal
Figure SMS_118
Through an F1 frequency phase-locked loop unit 31 and an F0 frequency phase-locked loop unit 32, respectively, wherein the F1 frequency phase-locked loop unit 31 locks the frequency +.>
Figure SMS_119
The output is the phase value of the current DDS +.>
Figure SMS_120
. Wherein the F0 frequency phase locked loop unit 32 locks the frequency +.>
Figure SMS_121
The output is the phase value of the current DDS +.>
Figure SMS_122
。
The structure of the F1 frequency pll unit 31 is shown in fig. 4.
Signal signal
Figure SMS_123
The signal output by the DDS generator 315 completes the complex frequency adjustment function in the complex multiplier 311, and the signal output by the complex multiplier 311 enters the CORDIC phase detector 312 to completeThe phase qualification function, the output of the CORDIC phase detector 312 is sent to a low pass filter 313 to perform the low pass filtering function, resulting in a more stable phase error. The error is added to the step>
Figure SMS_124
The accumulation of the phases is completed in accumulator 314 generating an output phase signal +.>
Figure SMS_125
，/>
Figure SMS_126
The output is also provided to a DDS generator 315 for generating a DDS signal.
The structure of the F0 frequency pll unit 32 is the same as that of the F1 frequency pll unit 31, except that the step value entering the accumulator 314 is different, and is the step value corresponding to the F0 frequency
Figure SMS_127
。
Signal signal
Figure SMS_128
After entering the 2bit one right shift unit 33, a divide-by-4 operation is performed, which corresponds to a divide-by-4 in frequency. Its output expression is +.>
Figure SMS_129
。
Signal signal
Figure SMS_130
After entering the 2bit second right shift unit 34, the divide-by-4 operation is performed, which corresponds to a divide-by-4 operation in frequency. Its output expression is +.>
Figure SMS_131
。
Signal signal
Figure SMS_132
Sum signal->
Figure SMS_133
In the phaseThe adding unit 35 performs an addition operation, which corresponds to a complex-domain multiplication operation, where one complex multiplication operation is replaced by one data addition, saving a lot of hardware resources. Its output is
Figure SMS_134
。
Signal signal
Figure SMS_135
Sum signal->
Figure SMS_136
The subtraction operation is performed in the subtraction unit 36, which corresponds to a complex-domain conjugate multiplication operation, where a complex multiplication operation is replaced by a data addition, which also saves a lot of hardware resources. Its output is
Figure SMS_137
。
Signal signal
Figure SMS_138
And->
Figure SMS_139
And the two signals are respectively sent to a first CORDIC unit 37 and a second CORDIC unit 38 to carry out complex domain conversion and output corresponding DDS signals for the subsequent modules to use.
Signal signal
Figure SMS_140
And signal->
Figure SMS_141
The output expression of the compensation conjugate multiplication module 4 that completes the frequency deviation and phase deviation of the telemetry transmitter and telemetry receiver at the conjugate multiplication module 4 is: />
Figure SMS_142
Wherein->
Figure SMS_143
For modulating information +.>
Figure SMS_144
Is a single symbol time.
Signal signal
Figure SMS_145
And signal->
Figure SMS_146
The quadrature demodulation module 5 performs complex multiplication to complete quadrature demodulation output signal as
Figure SMS_147
. The real part of the output signal is output to the first integration module 7 for integration operation, and the imaginary part of the output signal is output to the second integration module 8 for integration operation. The waveform of this signal is shown in fig. 5.
Signal signal
Figure SMS_149
The integrated clear signal for the first integration module 7 and the second integration module 8 is generated by generating an integrated clear pulse module 6 by means of the signal +.>
Figure SMS_151
Zero crossing point detection is respectively carried out on the real part and the imaginary part of the pulse, an integral zero clearing pulse is generated at the position of the zero crossing point, and the rest time is 0. The real part of the output signal is:
Figure SMS_154
wherein->
Figure SMS_150
Represents an integer>
Figure SMS_152
Representing the integer set in the set, the signal is fed to the first integration module 7 to be used as an integral zero clearing signal, and the imaginary part of the output signal is: />
Figure SMS_153
Wherein, the method comprises the steps of, wherein,
Figure SMS_155
represents an integer>
Figure SMS_148
Representing the set of integers in the set, the signal is fed to the second integration module 8 for use as an integration clear signal.
The function of the first integration module 7 is to use the signal
Figure SMS_156
As integral zero clearing sign for signal +.>
Figure SMS_157
Is integrated with the real part signal of the demodulation performance by accumulating energy and has an output expression of +.>
Figure SMS_158
Wherein->
Figure SMS_159
，/>
Figure SMS_160
Represents an integer>
Figure SMS_161
Representing a set of integers in a set.
The function of the second integration module 8 is to use the signal
Figure SMS_162
As integral zero clearing sign for signal +.>
Figure SMS_163
Is integrated with the imaginary signal of (a) and the demodulation performance is improved by accumulating energy, the output expression is +.>
Figure SMS_164
Wherein
Figure SMS_165
，/>
Figure SMS_166
Represents an integer>
Figure SMS_167
Representing a set of integers in a set.
The first decision module 9 is for the input signal
Figure SMS_168
Performing symbol extraction to complete signal hard decision of the branch to realize binarization processing, and the output result can be expressed as +.>
Figure SMS_169
The method comprises the steps of carrying out a first treatment on the surface of the The sign () function is a signed function.
The second decision module 10 is for the input signal
Figure SMS_170
Performing symbol extraction to complete signal hard decision of the branch to realize binarization processing, and the output result can be expressed as +.>
Figure SMS_171
The method comprises the steps of carrying out a first treatment on the surface of the The sign () function is a signed function.
Exclusive or module 11 inputs signals
Figure SMS_172
And->
Figure SMS_173
Performing exclusive OR operation to complete parallel-serial conversion of demodulation data, and outputting the result of +.>
Figure SMS_174
。
The code synchronization module 12 uses the signal
Figure SMS_175
And->
Figure SMS_176
Completion of the signal as a synchronization signal>
Figure SMS_177
The code synchronization function of (2) is completed by the MSK demodulation. And recovering the demodulated data.
The purpose of the invention is that:
the method is suitable for a zero intermediate frequency receiver, and can effectively reduce the volume, the quality and the power consumption of the receiver. The algorithm optimizes the band-pass filter which consumes very resources, reduces the number of multipliers and reduces the resource consumption. The demodulation algorithm can realize code synchronization without a complex code synchronization control loop.
Example 1
The sampling rate is 110Msa/s, the symbol rate of the information is 13.75Msa/s, the step of the F1 frequency phase-locked loop
Figure SMS_180
Step of F0 frequency phase locked loop>
Figure SMS_181
The Z-domain expression of the low-pass filter 313 system in the F1 frequency phase-locked loop unit 31 is: />
Figure SMS_184
Wherein->
Figure SMS_179
，/>
Figure SMS_182
The Z-domain expression of the low-pass filter 313 system in the F0 frequency phase-locked loop unit 32 is also: />
Figure SMS_183
Wherein->
Figure SMS_185
，/>
Figure SMS_178
. The value can reduce the resource consumption of the FPGA. The locking of the phase locked loop is shown in fig. 6.
The invention realizes the MSK orthogonal demodulation method with low complexity suitable for the zero intermediate frequency structure, and the method has a lower demodulation threshold compared with the traditional incoherent demodulation method. The quadrature demodulation method adopting the zero intermediate frequency structure avoids the use of a band-pass filter, innovatively converts multiplication operation of a complex domain into phase addition and subtraction operation, does not need an extra complex code synchronization loop circuit in the implementation process, effectively reduces the hardware volume and the resource consumption of the FPGA, and simultaneously, according to the embodiment 1, the demodulation algorithm has high carrier capturing speed and phase tracking precision under the condition of reducing the resource consumption and facilitating the hardware implementation, and is particularly suitable for a remote-distance high-code-rate telemetry receiver.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the invention.

Claims (8)

1. The demodulation method of the low-complexity MSK quadrature demodulation device with the zero intermediate frequency structure is characterized by comprising the following steps of: the demodulation device comprises a demodulation device, the demodulation device comprises an orthogonal down-conversion module (1), a complex square module (2), a phase-locked loop module (3), a conjugate multiplication module (4), an orthogonal demodulation module (5), an integral zero clearing pulse generation module (6), a first integral module (7), a second integral module (8), a first judgment module (9), a second judgment module (10), an exclusive OR module (11) and a code synchronization module (12), wherein the output end of the orthogonal down-conversion module (1) is respectively connected with the input end of the complex square module (2) and the input end of the conjugate multiplication module (4), the output end of the complex square module (2) is respectively connected with the input end of the phase-locked loop module (3), the output end of the phase-locked loop module (3) is respectively connected with the input end of the conjugate multiplication module (4), the input end of the orthogonal demodulation module (5) and the input end of the integral zero clearing pulse generation module (6), the output end of the orthogonal demodulation module (4) is respectively connected with the input end of the orthogonal demodulation module (5), the output end of the orthogonal demodulation module (5) is respectively connected with the input end of the first integral zero clearing module (7), the output end of the integral zero clearing pulse generation module (8) and the output end of the integral zero clearing module (8) respectively, the input end of the code synchronization module (12) is in signal connection, the output end of the first integration module (7) is in signal connection with the input end of the exclusive-or module (11) through the first judgment module (9), the input end of the second integration module (8) is in signal connection with the input end of the exclusive-or module (11) through the second judgment module (10), and the output end of the exclusive-or module (11) is in signal connection with the code synchronization module (12);
the phase-locked loop module (3) comprises an F1 frequency phase-locked loop unit (31), an F0 frequency phase-locked loop unit (32), a 2bit first right-shift unit (33), a 2bit second right-shift unit (34), an adding unit (35), a subtracting unit (36), a first CORDIC unit (37) and a second CORDIC unit (38), wherein the input end of the F1 frequency phase-locked loop unit (31) and the input end of the F0 frequency phase-locked loop unit (32) are respectively connected with the output end of the complex squaring module (2), the output end of the F1 frequency phase-locked loop unit (31) is connected to the input end of the 2bit first right-shift unit (33), the output end of the F0 frequency phase-locked loop unit (32) is connected to the input end of the 2bit second right-shift unit (34), the output end of the 2bit first right-shift unit (33) is respectively connected with the input end of the adding unit (35) and the input end of the subtracting unit (36), and the output end of the 2bit second right-shift unit (34) is respectively connected with the input end of the adding unit (35) and the signal of the subtracting unit (36);
the F1 frequency phase-locked loop unit (31) comprises a complex multiplier (311), a CORDIC phase detector (312), a low-pass filter (313), an accumulator (314) and a DDS generator (315), wherein the input end of the complex multiplier (311) is in signal connection with the output end of the complex squaring module (2), the output end of the complex multiplier (311) is in signal connection with the input end of the DDS generator (315) through the CORDIC phase detector (312), the low-pass filter (313) and the accumulator (314) in sequence, and the output end of the DDS generator (315) is in signal connection with the input end of the complex multiplier (311);
a demodulation method comprising the steps of:
s1, starting a low-complexity MSK orthogonal demodulation device with a zero intermediate frequency structure, transmitting an MSK modulation signal to the input end of an orthogonal down-conversion module (1), processing the MSK modulation signal received by the input end of the orthogonal down-conversion module (1) to obtain a down-conversion signal, and transmitting the down-conversion signal to a complex squaring module (2) and a conjugate multiplying module (4) respectively;
s2, the down-conversion signals are processed by a complex squaring module (2) to obtain complex signals, the complex signals are transmitted to a phase-locked loop module (3), the phase-locked loop module (3) processes the complex signals to generate frequency offset compensation DDS and demodulation synchronous DDS, the frequency offset compensation DDS is transmitted to a conjugate multiplying module (4), and the demodulation synchronous DDS is respectively transmitted to a quadrature demodulating module (5) and a quadrature zero clearing pulse generating module (6);
s3, the conjugate multiplication module (4) processes the frequency offset compensation DDS and the down-conversion signal in the step S1 to obtain a frequency offset compensation signal, and transmits the frequency offset compensation signal to the orthogonal demodulation module (5), and the orthogonal demodulation module (5) processes the frequency offset compensation signal and the demodulation synchronization DDS to obtain an orthogonal demodulation signal, and transmits the real part of the orthogonal demodulation signal to the first integration module (7), and the imaginary part of the orthogonal demodulation signal to the second integration module (8);
the module (6) for generating integral zero clearing pulse processes the demodulation synchronous DDS to obtain a pulse signal, the pulse signal is transmitted to the code synchronous module (12), the real part of the pulse signal is transmitted to the first integral module (7), and the imaginary part of the pulse signal is transmitted to the second integral module (8);
s4, the first integrating module (7) processes the real part of the quadrature demodulation signal and the real part of the pulse signal to obtain a real part integrated signal, and the real part integrated signal is transmitted to the first judging module (9);
the second integrating module (8) processes the imaginary part of the orthogonal demodulation signal and the imaginary part of the pulse signal to obtain an imaginary part integrated signal, and the imaginary part integrated signal is transmitted to the second judging module (10);
s5, the first judgment module (9) outputs a real part judgment signal to the exclusive-or module (11) after finishing binarization operation on the real part integral signal;
the second judgment module (10) outputs an imaginary part judgment signal to the exclusive-or module (11) after the binarization operation is finished on the imaginary part integral signal;
s6, the exclusive-or module (11) performs exclusive-or operation on the real part judgment signal and the imaginary part judgment signal, then outputs an exclusive-or signal, and transmits the exclusive-or signal to the code synchronization module (12);
s7, a code synchronization module (12) performs code synchronization on the pulse signal and the exclusive-or signal and outputs demodulation data.
2. The demodulation method of the zero intermediate frequency structure low complexity MSK quadrature demodulation apparatus according to claim 1, wherein: the expression of the MSK modulated signal in step S1 is:
Figure FDA0004231834860000031
wherein r is 1 (t) represents MSK modulated signal, f c Is radio frequency point, T b A is a single symbol time n Is modulation information;
the expression of the down-converted signal in step S1 is:
Figure FDA0004231834860000032
wherein r is 2 (t) represents a down-converted signal, a n In order to modulate the information it is possible, Tb for a single symbol time Δf represents the frequency offset of the telemetry transmitter and telemetry receiver, +.>
Figure FDA0004231834860000033
To represent the phase offset of the telemetry transmitter and telemetry receiver.
3. The demodulation method of the zero intermediate frequency structure low complexity MSK quadrature demodulation apparatus according to claim 2, wherein: the expression of the complex signal in step S2 is:
Figure FDA0004231834860000041
wherein r is 3 (t) represents a complex signal, a n To modulate information, T b For a single symbol time Δf represents the frequency offset of the telemetry transmitter and telemetry receiver, +.>
Figure FDA0004231834860000042
To represent the phase offset of the telemetry transmitter and telemetry receiver;
the expression of the frequency offset compensation DDS in step S2 is:
Figure FDA0004231834860000043
wherein x is 1 (t) represents a frequency offset compensation DDS, Δf represents a frequency offset of a telemetry transmitter and a telemetry receiver, +.>
Figure FDA0004231834860000044
To represent the phase offset of the telemetry transmitter and telemetry receiver;
the expression of the demodulation synchronization DDS in step S2 is:
Figure FDA0004231834860000045
wherein x is 2 (T) represents demodulation synchronization DDS, T b Is a single symbol time.
4. The demodulation method of the zero intermediate frequency structure low complexity MSK quadrature demodulation apparatus according to claim 2, wherein: the expression of the frequency offset compensation signal in step S3 is:
Figure FDA0004231834860000046
wherein r is 4 (t) represents a frequency offset compensation signal, a n To modulate information, T b For a single symbol time of time,
the real part expression of the pulse signal in step S3 is:
Figure FDA0004231834860000047
wherein p is a (T) represents the real part of the pulse signal, T b For a single symbol time, n represents an integer, and Z represents a set of integers in the set;
the imaginary part of the pulse signal is:
Figure FDA0004231834860000051
wherein p is b (T) represents the imaginary part of the pulse signal, T b For a single symbol time, n represents an integer and Z represents a set of integers in the set.
5. The demodulation method of the zero intermediate frequency structure low complexity MSK quadrature demodulation apparatus according to claim 2, wherein: the expression of the real part integrated signal in step S4 is:
Figure FDA0004231834860000052
wherein n.epsilon.Z, where r 6real (t) represents the real integral signal, r 5real (t) represents a real part of the quadrature demodulation signal, n represents an integer, and Z represents a set of integers in the set;
the expression of the imaginary integrated signal in step S4 is:
Figure FDA0004231834860000053
wherein n.epsilon.Z, where r 6imag (t) represents the imaginary integral signal, r 5imag (t) represents an imaginary part of the quadrature demodulation signal, n represents an integer, and Z represents a set of integers in the set.
6. The demodulation method of the zero intermediate frequency structure low complexity MSK quadrature demodulation apparatus according to claim 2, wherein: the expression of the real part decision signal in step S5 is: r is (r) 7real (t)＝sign(r 6real (t)); wherein r is 7real (t) represents the real part decision signal, sign () function is a sign taking function, r 6real (t) represents a real integral signal;
the expression of the imaginary decision signal in step S5 is: r is (r) 7imag (t)＝sign(r 6imag (t)); wherein r is 7imag (t) represents the imaginary decision signal, r 6imag (t) represents the imaginary integral signal, the sign () function being a signed function; the expression of the exclusive or signal in step S6 is: r is (r) 8 (t)＝r 7real (t)^r 7imag (t) wherein r 8 (t) represents an exclusive OR signal, r 7real (t) represents the real part decision signal, r 7imag And (t) represents the imaginary decision signal.
7. The demodulation method of the zero intermediate frequency structure low complexity MSK quadrature demodulation apparatus according to claim 2, wherein: the down-conversion signal in the step S2 is processed by a complex square module (2) to obtain a complex signal, the complex signal is transmitted to a phase-locked loop module (3), and the phase-locked loop module (3) processes the complex signal to generate a frequency offset compensation DDS and a demodulation synchronization DDS, and the method specifically comprises the following steps:
s21, the complex signals are respectively processed by an F1 frequency phase-locked loop unit (31) and an F0 frequency phase-locked loop unit (32), wherein the F1 frequency phase-locked loop unit (31) locks the frequency as
Figure FDA0004231834860000061
Wherein F is b The F1 frequency phase-locked loop unit (31) outputs the phase value +.>
Figure FDA0004231834860000062
And the phase value of the current DDS +.>
Figure FDA0004231834860000063
Transmitting to a 2bit one-number right shift unit (33);
wherein the F0 frequency phase-locked loop unit (32) locks the frequency to
Figure FDA0004231834860000064
Wherein F is b The F0 frequency phase-locked loop unit (32) outputs the phase value +.>
Figure FDA0004231834860000065
And the phase value of the current DDS +.>
Figure FDA0004231834860000066
Transmitting to a No. 2bit right shift unit (34);
s22, the phase value of the current DDS
Figure FDA0004231834860000067
After entering a 2bit one right shift unit (33), the operation of removing 4 is performed, and the expression of the output signal is +.>
Figure FDA0004231834860000071
And will output signal +>
Figure FDA0004231834860000072
Transmitting to an adding unit (35) and a subtracting unit (36);
phase value of current DDS
Figure FDA0004231834860000073
After entering a No. 2bit right shifting unit (34), the output signal is divided by 4, and the expression of the output signal is +.>
Figure FDA0004231834860000074
And will output signal +>
Figure FDA0004231834860000075
Transmitting to an adding unit (35) and a subtracting unit (36);
s23, output signal
Figure FDA0004231834860000076
And output signal +.>
Figure FDA0004231834860000077
An addition operation is performed in an addition unit (35), and an output signal is
Figure FDA0004231834860000078
And will output signal +>
Figure FDA0004231834860000079
Transmitting to a CORDIC unit number one (37);
output signal
Figure FDA00042318348600000710
And output signal +.>
Figure FDA00042318348600000711
The subtraction unit (36) performs subtraction operation, and the output signal is
Figure FDA00042318348600000712
And will output signal +>
Figure FDA00042318348600000713
Transmitting to a CORDIC unit No. two (38);
s24, a CORDIC unit (37) outputs signals
Figure FDA00042318348600000714
Performing complex domain conversion and outputting a frequency offset compensation DDS;
the second CORDIC unit (38) outputs a signal
Figure FDA00042318348600000715
And performing complex domain conversion and outputting demodulation synchronization DDS.
8. The demodulation method of the zero intermediate frequency structure low complexity MSK quadrature demodulation apparatus according to claim 7, wherein: in the step S21, the complex signals are processed by the F1 frequency phase-locked loop unit (31) and the F0 frequency phase-locked loop unit (32) synchronously, and the complex signals are processed by the F1 frequency phase-locked loop unit (31), which specifically comprises the following steps:
s211, performing complex frequency adjustment on the complex signal and the DDS signal output by the DDS generator (315) in the complex multiplier (311) to obtain a complex multiplied signal, and transmitting the complex multiplied signal to the CORDIC phase detector (312);
s212, after the phase identification of the complex multiplication signal is carried out by the CORDIC phase discriminator (312), CORDIC phase discrimination is obtained, and the CORDIC phase discrimination is transmitted to the low-pass filter (313);
s213, a low-pass filter (313) carries out low-pass filtering on the CORDIC phase-demodulation signals to obtain low-pass filtering signals, and the low-pass filtering signals are transmitted to an accumulator (314);
s214, step value of accumulator (314) for low-pass filtered signal, F1 frequency
Figure FDA0004231834860000081
After the bit accumulation generation, the phase value +.>
Figure FDA0004231834860000082
And the phase value of the current DDS +.>
Figure FDA0004231834860000083
Transmitting to a DDS generator (315), a 2bit first right shift unit (33);
s215, the phase value of the DDS generator (315) to the current DDS
Figure FDA0004231834860000084
After processing, the DDS signal is output to a complex multiplier (311).
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