CN116015298A

CN116015298A - ADC digital controller

Info

Publication number: CN116015298A
Application number: CN202211715679.3A
Authority: CN
Inventors: 胡景斌; 董军波; 徐国柱; 徐向阳; 李彦哲; 吴家辉; 贺裕华; 褚跃钢; 沈阳靖; 马德
Original assignee: Hangzhou Lingxin Microelectronics Co ltd
Current assignee: Hangzhou Lingxin Microelectronics Co ltd
Priority date: 2022-12-29
Filing date: 2022-12-29
Publication date: 2023-04-25

Abstract

The invention discloses an ADC digital controller, which comprises an ADC control module, a task scheduling module, a single sampling conversion task module, a mapping module, a bus interface module and a data register, wherein the single sampling conversion task module is configured with the trigger of each single sampling conversion task, an ADC analog-to-digital conversion channel and a priority when initialized, and the corresponding single sampling conversion task is transmitted to the task scheduling module after the trigger is received; and forming a task sequence according to the priority in the task scheduling module, sequentially sending the single sampling conversion tasks to the ADC control module, controlling an ADC analog-to-digital converter connected with the outside to carry out analog-to-digital conversion by the ADC control module, and informing the outside DMA to indirectly carry data through the bus access mapping module by the mapping module. The invention can realize the number of sequences with no number in theory, the sequences can be randomly interrupted and inserted, and the sequences with no number can realize the injection requirements of various complex conditions.

Description

ADC digital controller

Technical Field

The application belongs to the technical field of analog-to-digital conversion, and particularly relates to an ADC digital controller.

Background

ADC (Analog to Digital Converter) analog-to-digital converter is a type of converter for converting an analog signal to a digital signal. The ADC digital controller is a control device for controlling the ADC to perform analog-to-digital conversion and outputting the converted digital signal.

Various technical solutions exist in the aspects of sequential logic, channel injection, and data storage and DMA (Direct Memory Access) handling of conventional ADC digital controllers. For example, in terms of sequential logic, it is first assumed that the ADC shares n different external channels, and the user selects i channels (i < =n) to be used among the n channels, and the digital controller automatically composes a sequence of the i channels in order from small to large or from large to small. However, this scheme can only occur once per external channel in the sequence, and the order of the external channels is fixed, determined by the number size of the external channels, and cannot be changed. The other scheme is that the user needs to configure a section of sequence with the length of i, then select one of n different external channels at the 1 position of the section of sequence, and configure the sequence in sequence until the i position configuration is completed, i positions are totally used, namely the sequence length is i. However, although two or even four sequences can be configured in the scheme, no matter how many sequences are configured, the total length of all the sequences which can be configured is usually n number of external channels, the upper limit of the allocation of each sequence length can be fixed (n/number of sequences), and a plurality of sequences are in fixed sequence.

For another example, in the case of channel injection, one approach is to configure an injection sequence, and then insert the injection sequence into the normal sequence according to the injection location when triggered to begin injection. This solution has fixed injection positions, is not flexible enough, and has only one injection sequence, which cannot cope with more complex multi-injection situations.

In the aspects of data storage and DMA (direct memory access) carrying, when the prior art scheme adopts a plurality of registers, the scheme for flexibly carrying data by the DMA is not processed at present, and the data can be carried simply according to the increment and decrement of the address without change.

Disclosure of Invention

The purpose of the present application is to provide an ADC digital controller, which is used for overcoming the problem of relatively dead plates in sequential logic, injection logic and storage logic in the prior art, and is not widely applicable, so as to improve the flexibility of ADC conversion.

In order to achieve the above purpose, the technical scheme of the application is as follows:

an ADC digital controller, the ADC digital controller comprising: the system comprises an ADC control module, a task scheduling module, a single sampling conversion task module, a mapping module, a bus interface module and a data register, wherein:

the bus interface module is connected with an external bus, receives configuration information and transmits the configuration information to each module so as to finish initialization of each module;

the single sampling conversion task module transmits the single sampling conversion task corresponding to the trigger to the task scheduling module after receiving the trigger;

the task scheduling module forms a task sequence according to the priority of the single sampling conversion task after receiving the single sampling conversion task, and sequentially sends the single sampling conversion task to the ADC control module according to the arrangement sequence;

after receiving the single sampling conversion task, the ADC control module analyzes the single sampling conversion task and controls an ADC analog-to-digital converter connected with the outside to perform analog-to-digital conversion and then stores the converted digital signal into a data register;

the mapping module is used for judging whether the carried flag bit of the data register is enabled in the initialization stage, setting the carried flag bit corresponding to the data register to be carried if the carried flag bit is enabled in the initialization stage, and notifying an external DMA to indirectly carry data through the bus access mapping module when the DMA request position of the data register is set.

Further, the initialization of the single sampling conversion task module includes:

and configuring the triggering of the single-sampling conversion tasks, the ADC analog-to-digital conversion channels and the priorities one by one until the total number of the single-sampling conversion tasks to be configured is reached.

Further, the initializing of the mapping module includes:

configuring whether the DMA carried flag bit of each data register is enabled or not;

the DMA request bit of the last data register in the data to be handled is configured.

Further, the task scheduling module is further configured to, after receiving the single-sample conversion task, inject the received single-sample conversion task into the original existing task sequence according to the priority of the single-sample conversion task.

Further, the ADC digital controller also comprises a hardware trigger module, wherein the hardware trigger module is connected with the single-sampling conversion task module, receives an external hardware trigger signal and activates a single-sampling conversion task corresponding to the hardware trigger signal.

The ADC digital controller provided by the application is characterized in that the sequence is formed by single sampling conversion tasks, and the single sampling conversion tasks configured on the same trigger automatically form a sequence according to the priority. Each single sample conversion task may select an external channel individually. Therefore, the method not only can keep the advantages of the existing sequence logic (the external channels can be arranged at any position of the sequence any times), but also can overcome the problem that the number of the sequences is limited and the number of the channels in the sequences is limited. And the number of sequences with theoretical countless can be realized by matching with software triggering. The sequences generated by the ADC digital controller only have priority relation, and are not strictly controlled by logic in other designs. Therefore, the sequences can be randomly interrupted and inserted, the injection function is realized, and the injection requirements of various complex conditions can be realized by the sequence with unlimited numbers. For the mode of storing data in the multiple data registers, the digital controller has a data mapping module which can flexibly control which data in the data registers are carried when being matched with DMA data carrying. According to the technical scheme, compared with the existing ADC controller on the market, the effect is more flexible and efficient, and the hardware automation processing of more complex scenes is achieved.

Drawings

Fig. 1 is a schematic structural diagram of an ADC digital controller according to the present application.

Fig. 2 is a logic configuration diagram of the sequence of the present application.

FIG. 3 is a schematic diagram of the data storage logic of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.

The application provides an ADC digital controller, as shown in fig. 1, including: the system comprises an ADC control module, a task scheduling module, a single sampling conversion task module, a mapping module, a bus interface module and a data register, wherein:

Specifically, the ADC digital controller is configured to control the ADC analog-to-digital conversion module to perform analog-to-digital conversion, and provide the converted digital signal to a host device provided with the ADC digital controller. The host device will have a processor and a DMA module (Direct Memory Access), the user's software program is typically executed by the host device's processor, the configuration of the ADC digital controller is initiated by the processor, the ADC digital controller is accessed via the bus, and the bus interface module is read and written. And the bus interface module submits information configured by the processor to other modules to complete initialization of configuration.

The initialization of each module involved is described as follows:

for the initialization of the single-sample conversion task module, each single-sample conversion task to be configured in the single-sample conversion task module is mainly configured, for example, m single-sample conversion tasks in the single-sample conversion task module can be configured, and only n single-sample conversion tasks are needed in the application environment of a user, the initialization of the single-sample conversion task module is to configure n single-sample conversion tasks, including:

As shown in fig. 2, the task sequence of the ADC digital controller is formed by three layers, the top layer is a trigger, the middle layer is a single sampling conversion task, and the bottom layer is an external channel (i.e. ADC analog-digital conversion channel). The user wants to complete the generation of the task sequence requires configuration of the correspondence between each layer.

In the ADC digital controller, n single-sampling conversion tasks need to be configured, one of the tasks to be configured is selected as i, then the bottom layer information of the single-sampling conversion task i is configured for the single-sampling conversion task i, namely one of a plurality of external channels, and then the top layer information of the single-sampling conversion task i is configured for the single-sampling conversion task i, namely one of a plurality of triggers. In this embodiment, the serial number of the task is converted by single sampling as the priority, and the external channel which is preferentially processed corresponds to the task with the small serial number when configured, and the priority with the small serial number is large. After completing the configuration of n single sampling conversion tasks, all the single sampling conversion tasks corresponding to the trigger can be obtained, and a task sequence can be formed according to the priority of each single sampling conversion task.

For example, in fig. 2, the single-sample conversion task corresponding to the trigger 1 includes single-sample conversion tasks 3, 4, 5, 6, and 7, and if the sequence number of the single-sample conversion task corresponds to its priority, the task sequence is the single-sample conversion task 3, 4, 5, 6, and 7, and the priority with the small sequence number is large. Each single-sample conversion task has its corresponding external channel, for example, the external channel of the single-sample conversion task 3 is the external channel 3, which is not described in detail herein.

Similarly, the single sampling conversion task corresponding to the trigger 3 comprises single sampling conversion tasks 1 and 2, and a task sequence is formed.

It should be noted that the sequence in the prior art is a queue in which one or more external channels are arranged in a certain order. When the ADC starts to operate, the voltage values on the external channels are sampled and converted in the sequence order. The application introduces a single sampling conversion task as a middle layer, and corresponds to different external channels or triggers respectively, so that various task sequences corresponding to different triggers can be generated, and various task sequences can be selectively executed according to the triggers.

It can be seen that this multi-sequence logic consisting of multiple single sample conversion tasks not only retains the advantages of the existing scheme, but also has unique advantages: the upper limit of the sequence is determined by the trigger number, and can be flexibly configured according to requirements when the hardware is realized. An unlimited number of software sequences can theoretically be implemented if software triggers are used in conjunction. The single sampling conversion task that can be used by all sequences is flexibly configured according to the requirements in hardware implementation. And the number of single-sampling conversion tasks (i.e. the sequence length) in each sequence is not limited additionally, so that the single-sampling conversion tasks can be flexibly distributed.

In addition, in the initialization stage, an ADC control module is also configured, wherein the ADC control module comprises a power-on flow required by the ADC analog-to-digital conversion module, the working time length of each stage can be adjusted during working, and other information for controlling the state of the ADC analog-to-digital conversion module is provided, which belongs to a mature technology in the technical field and is not repeated herein.

For the initialization of the mapping module, the configuration of the flag bit of each data register mainly includes: configuring whether the DMA carried flag bit of each data register is enabled or not; the DMA request bit of the last data register in the data to be handled is configured.

In a specific embodiment, the ADC digital controller further includes a hardware trigger module, where the hardware trigger module is connected to the single-sampling conversion task module, receives an external hardware trigger signal, and activates a single-sampling conversion task corresponding to the hardware trigger signal.

Besides hardware triggering, software triggering is also possible. The hardware triggering is initiated by other hardware, and is processed by the hardware triggering module and then fed into the single sampling conversion task module; the software trigger is initiated by the processor and transmitted to the single sampling conversion task module through the bus interface module by the bus. The triggering corresponding to the single sampling conversion task can be software triggering from a processor or hardware triggering from a hardware triggering module, the application is not limited to a specific triggering mode, and the single sampling conversion task corresponding to the triggering signal is activated and sent to the task scheduling module after the triggering is received in any triggering mode.

After the single sampling conversion task module receives the trigger, all the single sampling conversion tasks configured as the trigger are added into the task scheduler module. The task scheduler module sequentially processes all the added single sampling conversion tasks according to the priority order of the single sampling conversion tasks to form a task sequence.

Specifically, the task scheduling module processes the tasks in sequence according to the priorities after taking the tasks, and the tasks are arranged into a sequence according to the priorities after taking N tasks after one-time triggering. If a new task is found during the sequence of processing, the injection function is implemented, and the order is reordered according to priority. And finally, the task scheduling module gives one task with the highest priority to the ADC control module to work according to the sequencing result, and deletes the task with the highest priority and reorders the rest tasks. After the ADC control module takes the task, analyzing the specific information of the task and controlling the ADC analog-to-digital conversion module to formally start working, informing the task scheduling module to send the next task after executing one task, and if the task does not work, entering into idle. Each time the ADC module completes sampling conversion, a voltage value is generated and stored in a corresponding data register.

In general applications, in order to improve the efficiency of the processor executing the program, the data generated by the ADC is processed by the DMA. The ADC digital controller communicates with the DMA through a separate request and response line, and then the DMA completes the handling of the data through a bus, namely the DMA directly handles the data in the data register.

The application provides a mapping module, which is used for indirectly carrying data in a data register. When the mapping module is initialized, a user configures whether the DMA carried flag bit of each data register is enabled or not through a bus, and then configures the DMA request bit of the last data register in the data to be carried. The configuration information is initiated by the processor when running the program, and is stored in the bus interface module after passing through the bus. The mapping module may be operative to obtain such configuration information directly from the bus interface module.

It should be noted that, whether the DMA carried flag bit of each data register is enabled, that is, whether the DMA carried flag bit configuring the data register is in an enabled state or in an disabled state, if in the enabled state, the DMA carried flag bit may be set later, that is, the DMA carried flag bit may be set later to 1, otherwise, the DMA carried flag bit may not be set. And the DMA request bit of the last data register in the data to be handled is set to 1, indicating that this is the last data register in the data to be handled.

The ADC digital controller completes the initialization flow and starts working after waiting for triggering; the hardware trigger module receives the hardware trigger and activates N single sampling conversion tasks. The tasks are transferred to the task scheduling module to form a task sequence, and the task sequence is distributed to the ADC control module and starts to work. After the ADC module completes the single sampling conversion task, the voltage value of the corresponding external channel is generated, and the data is put into a data register corresponding to the single sampling conversion task. At this time, the mapping module determines whether the DMA carried flag enable bit of the data register is enabled in the initialization stage, if so, the DMA carried flag bit corresponding to the data register is set, for example, to 1, to indicate that the data in the data register needs to be carried.

The mapping module also initiates a handling request to the DMA through the DMA request and the response line, informs the DMA to indirectly remove the data through the bus access mapping module, and the DMA responds to the request to read access the mapping module to remove the data. At this time, the mapping module will put the data of all the data registers with carried flag bit in order of priority to the mapping module and the bus interface in turn to wait for DMA read access.

Specific operations are shown in fig. 3, the ADC digital controller waits for receiving a hardware trigger or a user software trigger and starts working, and the ADC analog-to-digital conversion module completes the work of the single sampling conversion task i and generates data i, and stores the data i in the corresponding data register i.

And then the mapping module starts to judge whether the data register i is enabled by the carrying flag bit, if so, the next step is carried out, and if not, the next step is carried out, otherwise, the next step is carried out, and the next step is carried out to continue to finish other single sampling conversion tasks in the task sequence.

Under the condition that the data register i is enabled by the handling flag bit, the mapping module sets the data register i by the handling flag bit, then judges whether a DMA request bit of the data register i is set, if so, the data register i indicates that the task sequence is completed, and if not, the data register i is the last data, otherwise, the data register i returns to continuously complete other single sampling conversion tasks in the task sequence. When the DMA request bit of the data register is set, this is the last data register, so that the mapping module issues a request to the DMA module informing that the DMA can indirectly handle data through the bus access mapping module. And responding to the DMA module, and carrying data by reading access to the mapping module. The mapping module traverses all the data registers, and the data of the data register i set by all the carried flag bits are sequentially put on the mapping module and the bus interface according to the priority order to wait for DMA read access, and after the data is read, the carried flag bits corresponding to the data registers are cleared.

According to the method and the device, the data is flexibly carried by independently marking each data register, and only the data related to the current task sequence can be carried. The data mapping module is used for matching with DMA work, so that any data to be carried can be specified without the limitation of continuous addresses and the like.

In another specific embodiment, the task scheduling module is further configured to, after receiving the single-sample conversion task, inject the received single-sample conversion task into the original existing task sequence according to the priority of the single-sample conversion task.

Specifically, the single sample conversion task module may configure a plurality of sequences, with single sample conversion tasks within each sequence being fixed. When a sequence of single sample conversion tasks is operating within the task scheduler module, a trigger for an injection sequence arrives, at which point an injection is formed. The injected logic is formed by each single sample conversion task itself in terms of priority.

For example, the following three cases:

1. the real-time performance of the injection sequence is high, and the injection sequence needs to be processed by a vertical horse. Then the single sampling conversion task in the injection sequence is higher in priority than the normal sequence, and the task scheduler can switch to the injection sequence in time no matter where the normal sequence is processed when the injection condition occurs.

2. The injection sequence needs to be sampled and converted after the sampling of a specific point is finished, and then the highest priority of the single sampling conversion task in the injection sequence is placed at the priority of the specific point, so that the injection arrangement of the specific point is realized.

3. The real-time performance of the common sequence is high, and the common sequence needs to be processed periodically. Then the single sample conversion task in the injection sequence is lower in priority than the normal sequence, and when the injection condition occurs, no matter where the normal sequence is processed, the task scheduler processes all the single sample conversion tasks in the normal sequence before processing the injection sequence.

That is, work is allocated using the task scheduler module, and work allocation processing can be performed at only the task level, leaving the sequence level. Because of work distribution at the task level, the technical scheme of the application does not limit the number of sequences on the sequence level; the sequence properties on the sequence level are not limited, namely each sequence can be a common sequence or an injection sequence; because of the work distribution at the task level, each injection behavior is influenced by the fixed task priority and the trigger sequence, and the non-periodic or sporadic situation can be flexibly processed except the periodic injection situation.

The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims

1. An ADC digital controller, the ADC digital controller comprising: the system comprises an ADC control module, a task scheduling module, a single sampling conversion task module, a mapping module, a bus interface module and a data register, wherein:

2. The ADC digital controller of claim 1, wherein the initialization of the single sample conversion task module comprises:

3. The ADC digital controller according to claim 1, wherein the initialization of the mapping module comprises:

4. The ADC digital controller according to claim 1, wherein the task scheduling module is further configured to inject the received single sample conversion task into the original existing task sequence according to the priority of the single sample conversion task after receiving the single sample conversion task.

5. The ADC digital controller according to claim 1, further comprising a hardware trigger module, wherein the hardware trigger module is connected to the single sample conversion task module, receives an external hardware trigger signal, and activates a single sample conversion task corresponding to the hardware trigger signal.