CN116015022A

CN116015022A - Driving circuit, related control chip circuit, power adapter and electronic equipment

Info

Publication number: CN116015022A
Application number: CN202210109729.7A
Authority: CN
Inventors: 江力
Original assignee: Shenzhen Injoinic Technology Co Ltd
Current assignee: Shenzhen Injoinic Technology Co Ltd
Priority date: 2021-10-22
Filing date: 2021-10-22
Publication date: 2023-04-25
Also published as: CN113676025B; CN113676025A; WO2023065829A1

Abstract

The application provides a drive circuit and relevant control chip circuit, power adapter and electronic equipment, this drive circuit includes: the LDO negative feedback system comprises an operational amplifier circuit, a comparator, a first NMOS tube, a second NMOS tube, a third NMOS tube, a first PMOS tube, a second PMOS tube, a first drive control module and a second drive control module, wherein the first resistor, the second resistor and the first NMOS tube are used for forming the LDO negative feedback system. By adopting the embodiment of the application, the problem of EMI caused by the GaN power tube in charging application can be solved, and the precision requirement of the GaN power tube driving voltage can be met.

Description

Driving circuit, related control chip circuit, power adapter and electronic equipment

Technical Field

The application relates to the technical field of electronics, in particular to a driving circuit, a related control chip circuit, a power adapter and electronic equipment.

Background

As the process advances and defect rates continue to decrease, the advantages of gallium nitride (GaN) in electronic power supplies that convert ac-dc power, change voltage levels, and ensure reliable power supply as a function of a certain number become more and more evident.

Furthermore, in practical applications, gaN is considered to be used as a material of the GaN power tube, but during charging, since GaN operates at a higher frequency, there is a larger di/dt, and serious electromagnetic interference (electromagnetic interference, EMI) is caused, so how to solve the EMI problem caused by the GaN power tube in charging applications is needed.

Disclosure of Invention

The embodiment of the application provides a driving circuit, a related control chip circuit, a power adapter and electronic equipment, which can solve the problem of EMI caused by a GaN power tube in charging application and meet the precision requirement of the driving voltage of the GaN power tube.

In a first aspect, embodiments of the present application provide a driving circuit, including: the operational amplifier circuit, the comparator, the first NMOS tube, the second NMOS tube, the third NMOS tube, the first PMOS tube, the second PMOS tube, the first driving control module and the second driving control module, wherein,

the non-inverting input end of the operational amplifier circuit is connected with a first power supply, the output end of the operational amplifier circuit is connected with the first end of the first NMOS tube, the third end of the first NMOS tube is connected with a second power supply, the second end of the first MOS tube is connected with one end of a first resistor, and the other end of the first resistor is connected with the inverting input end of the operational amplifier circuit and is grounded through a second resistor;

the non-inverting input end of the comparator is connected with a third power supply, the output end of the comparator is connected with the first input end of the OR gate circuit, the second input end of the OR gate circuit is used for being connected with a driving signal, and the driving signal is also input into the first end of the first driving control module;

the output end of the OR gate circuit is connected with the first end of the second drive control module, and the second end of the second drive control module is connected with the first end of the second PMOS tube; the second end of the second PMOS tube is connected with the second end of the first PMOS tube and the second end of the second NMOS end, the third end of the second PMOS tube is connected with a driving port, and the driving port is used for driving the GaN power tube; the third end of the second NMOS tube is also connected with one end of a third resistor, and the other end of the third resistor is connected with one end of a fourth resistor and the inverting input end of the comparator;

the first end of the second NMOS tube is connected with one end of a fifth resistor, and the other end of the fifth resistor is connected with the first end of the first NMOS tube and grounded through a first capacitor; the third end of the second NMOS tube is connected with the second power supply;

the second end of the first drive control module is connected with the first end of the first PMOS tube, the third end of the first drive control module is connected with the first end of the third NMOS tube and the third end of the second drive control module, the third NMOS tube is connected with the third end of the second PMOS tube, and the second end of the third NMOS tube is grounded.

In a second aspect, embodiments of the present application provide a control chip circuit comprising a drive circuit as described in the first aspect above.

In a third aspect, embodiments of the present application provide a power adapter comprising a driving circuit as described in the first aspect, or a control chip circuit as described in the second aspect.

In a fourth aspect, embodiments of the present application provide an electronic device comprising a driving circuit as described in the first aspect, or a control chip circuit as described in the second aspect, or a power adapter as described in the third aspect.

By implementing the embodiment of the application, the following beneficial effects are achieved:

it can be seen that the driving circuit, the chip control circuit, the power adapter and the electronic device described in the embodiments of the present application, wherein the driving circuit includes: the operational amplifier comprises an operational amplifier circuit, a comparator, a first NMOS tube, a second NMOS tube, a third NMOS tube, a first PMOS tube, a second PMOS tube, a first drive control module and a second drive control module, wherein the in-phase input end of the operational amplifier circuit is connected with a first power supply, the output end of the operational amplifier circuit is connected with the first end of the first NMOS tube, the third end of the first NMOS tube is connected with a second power supply, the second end of the first MOS tube is connected with one end of a first resistor, and the other end of the first resistor is connected with the inverting input end of the operational amplifier circuit and is grounded through the second resistor; the non-inverting input end of the comparator is connected with a third power supply, the output end of the comparator is connected with the first input end of the OR gate circuit, the second input end of the OR gate circuit is used for accessing a driving signal, the driving signal is also input into the first end of the first driving control module, the output end of the OR gate circuit is connected with the first end of the second driving control module, and the second end of the second driving control module is connected with the first end of the second PMOS tube; the second end of the second PMOS tube is connected with the second end of the first PMOS tube and the second end of the second NMOS end, the third end of the second PMOS tube is connected with a driving port, and the driving port is used for driving the GaN power tube; the third end of the second NMOS tube is also connected with one end of a third resistor, the other end of the third resistor is connected with one end of a fourth resistor and the inverting input end of the comparator, the first end of the second NMOS tube is connected with one end of a fifth resistor, and the other end of the fifth resistor is connected with the first end of the first NMOS tube and grounded through a first capacitor; the third end of the second NMOS tube is connected with a second power supply, the second end of the first drive control module is connected with the first end of the first PMOS tube, the third end of the first drive control module is connected with the first end of the third NMOS tube and the third end of the second drive control module, the third NMOS tube is connected with the third end of the second PMOS tube, the second end of the third NMOS tube is grounded, and the control method of the upper limit of the output drive voltage of the LDO operational amplifier clamping can be adopted according to the drive requirement of the GaN device, so that the upper limit of the output drive voltage is ensured to be strictly clamped at about 6V. Meanwhile, the EMI effect is improved by adopting a method of detecting the 2-section driving of the output driving voltage.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of an NMOS transistor according to an embodiment of the present application;

FIG. 2 is a schematic structural diagram of a PMOS tube according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a driving circuit according to an embodiment of the present application;

fig. 4 is another schematic structural diagram of a driving circuit according to an embodiment of the present application;

fig. 5 is another schematic structural diagram of a driving circuit according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a driving control circuit according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of another driving control circuit according to the embodiment of the present application;

fig. 8 is a schematic waveform diagram of signals based on the driving circuit of fig. 5 according to an embodiment of the present application.

Detailed Description

For better understanding of the technical solutions of the present application by those skilled in the art, the technical solutions of the embodiments of the present application are clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art without the exercise of inventive faculty, are intended to be within the scope of protection of the present application based on the description of the embodiments herein.

The terms first, second and the like in the description and in the claims of the present application and in the above-described figures, are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, software, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

Embodiments of the present application will be described with reference to the accompanying drawings, in which the crossing points of intersecting conductors have dots to indicate that the conductors are connected, and the non-dots at the crossing points indicate that the conductors are not connected.

For a better understanding of aspects of embodiments of the present application, related terms and concepts that may be related to embodiments of the present application are described below.

GaN device: the low-on-resistance high-frequency high-voltage power supply has low on-resistance and high working frequency, and can meet the requirements of next-generation electronic equipment on higher power, higher frequency, smaller volume and more severe high-temperature operation of power devices. GaN power devices have better overall performance, can be epitaxially grown on silicon substrates, and have the potential to be more cost-effective than silicon carbide devices in terms of area and overall cost, and therefore are also used in high power, high frequency semiconductor devices.

As the process advances and defect rates continue to decrease, the advantages of GaN in electronic power supplies that convert ac-dc power, change voltage levels, and ensure reliable power supply as a function of a certain number become more and more evident. Power supply designers are re-thinking about circuit designs in an attempt to create power supply systems that fully exploit the potential of entirely new GaN transistors while avoiding negative effects. The general idea when considering this type of problem is to find the solution in the existing assembly-GaN switches, si switch drivers, high speed switch controllers, and components in the overall design of power inductors, transformers and capacitors. Integrated Circuit (IC) manufacturers producing power supply products can greatly increase power supply design possibilities if they can provide system-level solutions with commonly designed devices, even with multiple chips integrated in a module package.

Compared to silicon Si-based power electronics, gaN-based power electronics have 3 advantages:

1. high efficiency and energy saving: due to the unique polarization characteristics of GaN materials, there is a very strong polarization effect between AlGaN/GaN heterojunctions, forming a high concentration two-dimensional electron gas (2 DEG) with mobility up to 2000 and areal density up to the order of magnitude. The GaN-based power switching device HFET works by utilizing AlGaN/GaN heterojunction 2DEG, and the device has the advantages of small on-resistance and high switching speed, so that the on-state loss and switching of the device are greatly reduced.

2. The power electronic device can be miniaturized, light and low-cost: the GaN material has a larger forbidden bandwidth than Si, so that the GaN device can work in a higher temperature environment, and therefore, the heat dissipation device can be simplified or even omitted. In addition, the GaN device has high switching frequency, so that the volume of the capacitance and inductance of the passive device of the system is greatly reduced. These all enable the power electronic device of GaN base to be miniaturized and lightened, greatly reduce the manufacturing cost of the system.

3. The output power density is high, and the driving force is strong: because of the characteristics of wide forbidden band and the like, the critical breakdown electric field of the GaN material is as high as 3.4MV/cm and 10 times of that of the Si material, so that the GaN device has higher voltage-withstanding capability. Meanwhile, the GaN-based device works by using the 2DEG to obtain low on-resistance and high current density, so that the GaN device can obtain higher power density.

Gallium nitride based field effect transistors (GaN) operate much faster at lower gate threshold voltages than silicon MOSFETs. Furthermore, the internal gate resistance for GaN FETs is lower and the reverse recovery characteristics of body diodes are far superior to silicon MOSFETs. The GaNFET has some output capacitance, but it is significantly lower than silicon. In practice, gaN transistors have a low resistance (RDS (ON)) and gate charge QG. More importantly, gaN transistors are not affected by strong negative temperature coefficients like MOSFETs. Therefore, the drive requirement for GaN FETs, whether normal or off, will be quite different from silicon MOSFETs.

Compared with the traditional Si driving, the GaN driving circuit has higher driving switching frequency, lower required driving voltage and higher efficiency. For power supply designers, driving GaN devices requires consideration:

(1) Low threshold voltage

The threshold voltage of a GaN FET is typically below 1.5V, with a minimum of as low as 0.7V, which is low compared to many MOSFETs, but it varies almost smoothly with temperature.

(2) The upper limit of the gate source voltage is strict: VGS (MAX) =6v. On the one hand, VGS must be set below 5.5V to reserve a safety margin of 0.5V. ON the other hand, as seen from the Rds (ON) versus VGS curves, rds (ON) can reach a minimum at vgs=4.5-5.5V, meaning that conduction losses are reduced. Comprehensively, VGS is set at 5V. Problems caused by the design requirement of the gate-source voltage: the gate-source voltage must be tightly controlled to avoid damaging the GaN FET power transistor gate and the normal bias suitable for MOSFETs driving cannot be used directly.

(3) Problems of EMI

Since GaN can operate at higher frequencies, there is a greater dV/dt. This would cause serious EMI problems.

In addition, in the embodiment of the present application, as shown in fig. 1, for the NMOS transistor, the first end of the NMOS transistor is a gate, the second end is a source, the third end is a drain, the fourth end is a substrate, and the fourth end is grounded; as shown in fig. 2, for the PMOS transistor, the first end of the PMOS transistor is a gate, the second end is a source, the third end is a drain, the fourth end is a substrate, and the fourth end is used for accessing a power supply, such as VDD; for the drive control module, the first end is DR, the second end is DU, and the third end is DW.

In the related art, as shown in fig. 3, fig. 3 is a driving control circuit of a conventional driving, in which a driving module is driven step by step through an inverter chain. The output voltage drives an external MOS power transistor. The external MOS power transistor has a non-negligible capacitance between the gate and source. In order to rapidly turn on or off the drain current, a large current is required to drive the gate voltage up or down. The driving adopts a section of control mode, and when the Drive signal is 0, the grid voltage position of the NMOS tube N1 is high. Simultaneously, N1 is opened to output a large current, and the instant GATE voltage becomes high; similarly, when the Drive signal is 1, the NMOS transistors N2 and N3 are turned on, and the GATE voltage is instantaneously pulled down.

Among them, the driving circuit based on fig. 1 has a disadvantage that the driving adopts a one-stage control method, and di/dt existing in the switching process is changed greatly, resulting in poor EMI effect. Meanwhile, the output voltage is limited by the VCC voltage, which is VCC-VGS at the highest, and varies with the variation of VCC, which is disadvantageous for the GaN driving tube. To use this drive, additional circuitry is required to control the VCC, thereby increasing cost.

Further, fig. 4 is a schematic diagram of a resonant driving circuit, and the core idea is to add an LC resonant circuit into the driving circuit, and utilize parasitic capacitance inside the switching tube to resonate with external inductance to realize driving of the switching tube, and effectively recover energy stored in the resonant inductance, thereby reducing driving loss. However, the control circuit is complex, an additional circuit is required to control VCC, and the resonance type driving can only exert its advantages in the ultra-high frequency. Is not applicable to flyback structures.

Further, based on the above-described drawbacks of the related art, embodiments of the present application provide a driving circuit, a chip control circuit, a power adapter, and an electronic device for solving the above-described drawbacks.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a driving circuit according to an embodiment of the present application, where the driving circuit includes: the operational amplifier OP1, the comparator CMP1, the first NMOS tube MN1, the second NMOS tube MN2, the third NMOS tube MN3, the first PMOS tube MP1, the second PMOS tube MP2, the first drive control module CTRL1 and the second drive control module CTR2, wherein,

the non-inverting input end (+) of the operational amplifier circuit OP1 is connected with a first power supply S1, the output end of the operational amplifier circuit OP1 is connected with the first end of the first NMOS tube MN1, the third end of the first NMOS tube MN2 is connected with a second power supply VDD, the second end of the first MOS tube MN1 is connected with one end of a first resistor R1, and the other end of the first resistor R1 is connected with the inverting input end (-) of the operational amplifier circuit OP1 and is grounded through a second resistor R2;

the non-inverting input end (+) of the comparator CMP1 is connected with a third power supply S2, the output end of the comparator CMP1 is connected with a first input end of an OR gate circuit, a second input end of the OR gate circuit is used for being connected with a driving signal drive_P, and the driving signal drive_P is also input into a first end of the first driving control module CTRL 1;

the output end of the OR gate circuit is connected with the first end of the second drive control module, and the second end of the second drive control module is connected with the first end of the second PMOS tube MP 2; the second end of the second PMOS transistor MP2 is connected to the second end of the first PMOS transistor MP1 and the second end of the second NMOS transistor MN2, and the third end of the second PMOS transistor MN2 is connected to a driving port GATE, where the driving port GATE is used for driving the GaN power transistor; the third end of the second NMOS tube MN2 is also connected with one end of a third resistor R3, and the other end of the third resistor R3 is connected with one end of a fourth resistor R4 and an inverting input end (-) of the comparator CMP 1;

the first end of the second NMOS MN2 is connected to one end of a fifth resistor R5, and the other end of the fifth resistor R5 is connected to the first end of the first NMOS NM1 and grounded through a first capacitor C1; the third end of the second NMOS tube MN2 is connected with the second power supply VDD;

the second end of the first drive control module CTRL1 is connected to the first end of the first PMOS MP1, the third end of the first drive control module CTRL1 is connected to the first end of the third NMOS MN3 and the third end of the second drive control module CTR2, the third NMOS MN3 is connected to the third end of the second PMOS MP2, and the second end of the third NMOS MN3 is grounded.

Wherein R1, R2 can be replaced by a variable resistor by which the ratio between R1 and R2 is adjusted. R3, R4 can also be replaced by a variable resistor by means of which the ratio between R3 and R4 is adjusted.

Optionally, the operational amplifier circuit OP1, the first resistor R1, the second resistor R2, and the first NMOS MN1 are configured to form an LDO negative feedback system;

the negative feedback system is configured to dynamically adjust the current of the first NMOS transistor MN1 through the ratio between the first resistor R1 and the second resistor R2 and the OP1, so as to obtain a first output voltage V1 at the second end of the first NMOS transistor MN 1;

when the first output voltage V1 is smaller than a first output voltage design value, the output of the operational amplifier OP1 becomes high, the current passing through the first NMOS transistor NM1 increases, and the first output voltage V1 increases;

on the contrary, when the first output voltage is greater than the first output voltage design value, the output of the operational amplifier circuit becomes low, and the first output voltage is reduced by reducing the current of the first NMOS, so as to dynamically adjust the first output voltage of the second end of the first NMOS.

The first output voltage design value may be preset or default, for example, the first output voltage design value may be a set value, i.e., an empirical value.

Optionally, an absolute value of a difference between the second output voltage V2 at the second end of the second NMOS transistor MN2 and the first output voltage V1 is smaller than a preset threshold.

Wherein, the preset threshold may be preset or default, and the preset threshold may approach 0, for example, the preset threshold is 0.01.

Optionally, the first output voltage V1 is determined by an input voltage VREF of the non-inverting input terminal (+) of the operational amplifier OP1, the first resistor R1, and the second resistor R2. The specific calculation formula is as follows:

V1＝VREF*(R1+R2)/R2

optionally, the second output voltage V2 is determined by an input voltage VREF of the non-inverting input terminal (+) of the operational amplifier OP1, the first resistor R1 and the second resistor R2, and a specific calculation formula is as follows:

V2＝VREF*(R1+R2)/R2

optionally, the driving signal drive_p is used for turning on the first PMOS transistor MP1 through the first driving control module CTRL1, turning off the third NMOS transistor MN3, dividing the voltage through the third resistor R3 and the fourth resistor R4 to obtain a third output voltage vo_adopt, using the third output voltage vo_adopt as a first input signal of the inverting input terminal (-) of the comparator CMP1, and comparing a second input signal of the non-inverting input terminal (+) of the comparator CMP1 to obtain a driving control signal; and the driving control signal and the driving signal drive_P are passed through an OR gate circuit to obtain an output signal, the second PMOS tube is started through the output signal, and the first PMOS tube MP1 and the second PMOS tube MP1 are charged simultaneously.

Optionally, the first driving control module CTRL1 includes M inverters, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a third PMOS transistor MP3, and a fourth PMOS transistor MP4, where M is an even number;

the first end of the first drive control module CTRL1 is connected to the second end of the first drive control module CTRL1 and the first end of the fifth NMOS MN5 through the M inverters; the second end of the fifth NMOS tube MN5 is grounded;

the first end of the first driving control module CTRL1 is connected to the first end of the fourth NMOS transistor MN4, the second end of the fourth NMOS transistor MN4 is grounded, the third end of the fourth NMOS transistor MN4 is connected to one end of a sixth resistor R6, the other end of the sixth resistor R6 is connected to the third end and the first end of the third PMOS transistor MP3, and the first end of the third PMOS transistor MP3 is connected to the first end of the fourth PMOS transistor MP 4; the third end of the fourth PMOS MP4 is connected to one end of a seventh resistor R7, and the other end of the seventh resistor R7 is connected to the third end of the first driving control module CTRL1 and the third end of the fifth NMOS MN 5; the second end of the third PMOS MP3 and the second end of the fourth PMOS MP4 are both connected to the second power supply VDD.

Specifically, as shown in fig. 6, m=4, that is, 4 inverters are illustrated as an example, and triangles are shown as representing the inverters. The inverter can promote driving capability on the one hand, and on the other hand can realize the time delay effect.

Optionally, the second driving control module CTRL2 includes N inverters, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a fifth PMOS transistor MP5, and a sixth PMOS transistor MP6, where N is an even number;

the first end of the second driving control module CTRL2 is connected to the second end of the second driving control module CTRL2 and the first end of the seventh NMOS MN7 through the N inverters; the second end of the seventh NMOS tube MN7 is grounded;

the first end of the second driving control module CTRL is connected to the first end of the sixth NMOS transistor MN6, the second end of the sixth NMOS transistor MN6 is grounded, the third end of the sixth NMOS transistor MN6 is connected to one end of the eighth resistor R8, the other end of the eighth resistor R8 is connected to the third end and the first end of the fifth PMOS transistor MP5, and the first end of the fifth PMOS transistor MP5 is connected to the first end of the sixth PMOS transistor MP 6; the third end of the sixth PMOS MP6 is connected to one end of a ninth resistor R9, and the other end of the ninth resistor R9 is connected to the third end of the second driving control module CTRL2 and the third end of the seventh NMOS MN 7; the second end of the fifth PMOS MP5 and the second end of the sixth PMOS MP6 are both connected to the second power supply VDD.

Specifically, as shown in fig. 7, n=4, that is, 4 inverters are illustrated as an example in fig. 7, and triangles are shown as representing the inverters. The inverter can promote driving capability on the one hand, and on the other hand can realize the time delay effect.

According to the embodiment of the application, due to the control of the OR gate circuit, the first drive control circuit and the second drive control circuit are respectively controlled to work in different periods, and further, two-section drive control is formed, and the two-section drive control and the LDO operational amplifier clamping output drive voltage upper limit technology are adopted, so that the EMI is improved, the accurate value of the chip drive voltage is improved, and the damage to a GaN device due to fluctuation of the output voltage value is avoided. Furthermore, the effect of the chip EMI can be improved on the basis of meeting the GaN driving requirement.

In a specific implementation, the operational amplifier OP1, the resistors R1 and R2 and the NMOS transistor MN1 form an LDO circuit.

Aiming at the driving circuit, the specific working principle is as follows: LDO is a negative feedback system, and the accurate value of output voltage (V1) can be realized by utilizing the ratio of R1 to R2 and the dynamic regulation of current passing through MN1 by an operational amplifier. When the output voltage V1 is smaller than the design value, the OP1 output becomes high, the current through MN1 increases, the output voltage V1 increases, and when the output voltage V1 is larger than the design value, the OP1 output becomes low, the current through MN1 decreases, and the output voltage V1 decreases. Thereby achieving that the V1 voltage output is maintained at the design value. Similarly, by connecting the first ports of MN2 and MN1 together to match as closely as possible, it is possible to achieve that the output voltage V2 is maintained at the design value, i.e. that V1 and V2 are equal or nearly equal. The capacitor C1 has the function of stabilizing the voltage of the grid stage of the MOS transistor, reducing the bandwidth of the LDO and increasing the stability of the LDO system. Meanwhile, C1 and R5 form a low-pass filter, so that the influence of the gate voltage of MN2 on the gate voltage of MN1 can be reduced.

The set value can be determined according to the driving voltage of the GAN power amplifier of the device to be driven.

In specific implementation, the two-stage driving working principle is as follows: first, the driving signal drive_p turns on MP1 and turns off MN3 by the driving control module CTRL1 (circuit shown in fig. 6), and the output voltage increases. Then, the output voltage is sampled by dividing the voltage through resistors R3 and R4. The sampled output voltage is compared with a reference voltage VREF1 by a comparator CMP1 to output a 2-segment drive control signal. And the signal drive_p is further or, PM2 is turned on by the control module CTRL2, and finally the charging is given by MP1 and MP2 at the same time. This causes the drive current to change from small to large, and there is a gradual change in the drive voltage from low to high. The di/dt spike is reduced, and the EMI effect is improved.

In the embodiment of the application, aiming at the driving requirement of a GaN device, a control method of clamping the upper limit of the output driving voltage of the LDO operational amplifier is adopted, so that the output driving voltage upper line is ensured to be clamped strictly at about 6V. Meanwhile, the EMI effect is improved by adopting a method of detecting the 2-section driving of the output driving voltage. The GaN driving requirement can be met, the output driving voltage is well maintained at 6V, the damage to GaN caused by output voltage fluctuation is avoided, and the effect of the chip EMI is improved. The driving circuit shown in fig. 5 is smaller in EMI and lower in cost compared with the driving circuit shown in fig. 3; the driving circuit shown in fig. 5 has less EMI than the driving circuit shown in fig. 4, and can be applied to a flyback structure.

The first power source and the third power source may be an AC/DC power source, a DC/DC power source, a regulated power source, a communication power source, a module power source, a variable frequency power source, an inverter power source, an AC regulated power source, a DC regulated power source, etc., which is not limited in this embodiment of the present application. The first power source and the second power source may be the same power source or different power sources.

Further, the GaN power tube is output to the electric equipment for charging the electric equipment, the electric equipment can be understood as equipment requiring the user to charge, and the user equipment can include but is not limited to: smart phones, tablet computers, smart robots, smart elevators, car devices, wearable devices, smart home devices, computing devices or other processing devices connected to wireless modems, as well as various forms of User Equipment (UE), mobile Stations (MS), terminal devices (terminals), etc.

In a specific implementation, as shown in fig. 8, in which waveforms of drive_ P, DU1, DU2 and GATE signals are shown, it can be seen that the driving current can be changed from small to large, and the driving voltage has a gradual change from low to high. The di/dt spike is reduced, and the EMI effect is improved.

Further, the driving circuit may be applied to a control chip circuit, and the control chip circuit may include at least one of the following: the AC-DC chip control circuit and the DC-DC chip control circuit are not limited herein, and the AC-DC chip control circuit may be a flyback AC-DC chip control circuit or a non-flyback AC-DC chip control circuit.

Therefore, in the specific implementation, the two-stage drive control and LDO operational amplifier clamping output drive voltage upper limit technology is adopted, so that the EMI is improved, the accurate value of the chip drive voltage is also improved, and the damage to a GaN device due to the fluctuation of the output voltage value is avoided. For example, the driving is used in a flyback ACDC control chip circuit to realize the driving of the GaN power tube.

Still further, the driving circuit and the control chip circuit may be applied to a power adapter.

Of course, the embodiment of the present application also provides an electronic device, which may include the driving circuit or the chip control circuit or the power adapter as described in fig. 5, and for example, the electronic device may be a charger or a charger.

The foregoing is a description of embodiments of the present application, and it should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principles of the embodiments of the present application, and these improvements and modifications are also considered as the protection scope of the present application.

Claims

1. A driving circuit, characterized in that the driving circuit comprises: the operational amplifier circuit, the comparator, the first NMOS tube, the second NMOS tube, the third NMOS tube, the first PMOS tube, the second PMOS tube, the first drive control circuit and the second drive control circuit, wherein,

the non-inverting input end of the operational amplifier circuit is connected with a first power supply, the output end of the operational amplifier circuit is connected with the first end of the first NMOS tube, the third end of the first NMOS tube is connected with a second power supply, and the second end of the first MOS tube is connected with the inverting input end of the operational amplifier circuit through a first resistor;

the non-inverting input end of the comparator is connected with a third power supply, the output end of the comparator is connected with the first input end of the OR gate circuit, the second input end of the OR gate circuit is used for being connected with a driving signal, and the driving signal is also input into the first end of the first driving control circuit;

the output end of the OR gate circuit is connected with the first end of the second drive control circuit, and the second end of the second drive control circuit is connected with the first end of the second PMOS tube; the second end of the second PMOS tube is connected with the second end of the first PMOS tube and the second end of the second NMOS tube, the third end of the second PMOS tube is connected with a driving port, and the driving port is used for driving the GaN power tube; the third end of the second NMOS tube is also connected with one end of a fourth resistor and the inverting input end of the comparator through a third resistor;

the first end of the second NMOS tube is connected with the first end of the first NMOS tube through one end of a fifth resistor and grounded through a first capacitor; the third end of the second NMOS tube is connected with the second power supply;

the second end of the first drive control circuit is connected with the first end of the first PMOS tube, the third end of the first drive control circuit is connected with the first end of the third NMOS tube and the third end of the second drive control circuit, the third NMOS tube is connected with the third end of the second PMOS tube, and the second end of the third NMOS tube is grounded.

2. The driving circuit of claim 1, wherein the op-amp circuit, the first resistor, the second resistor, the first NMOS transistor are configured to form an LDO negative feedback system;

the negative feedback system is used for dynamically adjusting the current of the first NMOS tube through the ratio between the first resistor and the second resistor and the operational amplifier circuit so as to obtain a first output voltage of the second end of the first NMOS tube;

when the first output voltage is smaller than a first output voltage design value, the output of the operational amplifier circuit becomes high, the current passing through the first NMOS tube is increased, and the first output voltage is increased;

conversely, when the first output voltage is greater than or equal to the first output voltage design value, the output of the operational amplifier circuit becomes low, the first output voltage is reduced through the current reduction of the first NMOS tube, and the first output voltage of the second end of the first NMOS tube is dynamically adjusted.

3. The drive circuit of claim 2, wherein an absolute value of a difference between a second output voltage of the second end of the second NMOS transistor and the first output voltage is less than a preset threshold.

4. A driving circuit according to claim 3, wherein the first output voltage is determined by an input voltage at a non-inverting input of the op-amp circuit, the first resistor and the second resistor;

and/or the second output voltage is determined by the input voltage of the non-inverting input end of the operational amplifier circuit, the first resistor and the second resistor.

5. The driving circuit according to any one of claims 1 to 4, wherein the driving signal is used for turning on the first PMOS transistor and turning off the third NMOS transistor through the first driving control circuit, dividing the voltage by the third resistor and the fourth resistor to obtain a third output voltage, using the third output voltage as a first input signal of an inverting input terminal of the comparator, and comparing a second input signal of a non-inverting input terminal of the comparator to obtain a driving control signal; and the driving control signal and the driving signal pass through an OR gate circuit to obtain an output signal, the second PMOS tube is started through the output signal, and the first PMOS tube and the second PMOS tube are charged simultaneously.

6. The drive circuit according to any one of claims 1 to 4, wherein the first drive control circuit includes M inverters, a fourth NMOS transistor, a fifth NMOS transistor, a third PMOS transistor, and a fourth PMOS transistor, M being an even number;

the first end of the first drive control circuit is connected with the second end of the first drive control circuit and the first end of the fifth NMOS tube through the M inverters; the second end of the fifth NMOS tube is grounded;

the first end of the first drive control circuit is connected with the first end of the fourth NMOS tube, the second end of the fourth NMOS tube is grounded, the third end of the fourth NMOS tube is connected with one end of a sixth resistor, the other end of the sixth resistor is connected with the third end and the first end of the third PMOS tube, and the first end of the third PMOS tube is connected with the first end of the fourth PMOS tube; the third end of the fourth PMOS tube is connected with one end of a seventh resistor, and the other end of the seventh resistor is connected with the third end of the first drive control circuit and the third end of the fifth NMOS tube; and the second end of the third PMOS tube and the second end of the fourth PMOS tube are both connected with the second power supply.

7. The drive circuit according to any one of claims 1 to 5, wherein the second drive control circuit includes N inverters, a sixth NMOS transistor, a seventh NMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor, the N being an even number;

the first end of the second drive control circuit is connected with the second end of the second drive control circuit and the first end of the seventh NMOS tube through the N inverters; the second end of the seventh NMOS tube is grounded;

the first end of the second driving control circuit is connected with the first end of the sixth NMOS tube, the second end of the sixth NMOS tube is grounded, the third end of the sixth NMOS tube is connected with one end of an eighth resistor, the other end of the eighth resistor is connected with the third end and the first end of the fifth PMOS tube, and the first end of the fifth PMOS tube is connected with the first end of the sixth PMOS tube; the third end of the sixth PMOS tube is connected with one end of a ninth resistor, and the other end of the ninth resistor is connected with the third end of the second drive control circuit and the third end of the seventh NMOS tube; and the second end of the fifth PMOS tube and the second end of the sixth PMOS tube are both connected with the second power supply.

8. A control chip circuit, characterized in that the control chip circuit comprises a drive circuit as described in any of claims 1-7.

9. A power adapter comprising a drive circuit as described in any one of claims 1-7 or a control chip circuit as described in claim 8.

10. An electronic device comprising a drive circuit as described in any of claims 1-7, or a control chip circuit as described in claim 8, or a power adapter as described in claim 9.