CN116013984A - Deep-trench super-junction DMOS device and manufacturing method thereof - Google Patents
Deep-trench super-junction DMOS device and manufacturing method thereof Download PDFInfo
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- CN116013984A CN116013984A CN202211263160.6A CN202211263160A CN116013984A CN 116013984 A CN116013984 A CN 116013984A CN 202211263160 A CN202211263160 A CN 202211263160A CN 116013984 A CN116013984 A CN 116013984A
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Abstract
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a deep-trench super-junction DMOS device and a manufacturing method thereof. The device comprises: a first conductivity type base layer comprising opposite front and back sides, the front side forming a source and the back side forming a drain; the second conduction type well region is positioned on the lower layer of the source electrode; second conductivity type buried pillars formed in the first conductivity type base layer and extending downward from a lower surface of the second conductivity type well region; the polysilicon trench structure is formed at the left side and the right side of the buried layer column of the second conductivity type, and extends downwards from the front to sequentially pass through the source electrode and the well region of the second conductivity type, and the bottom end of the polysilicon trench structure extends out of the well region of the second conductivity type; and the first conduction type injection region surrounds the bottom end of the polysilicon trench structure extending out of the second conduction type well region.
Description
Technical Field
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a deep-trench super-junction DMOS device and a manufacturing method thereof.
Background
The breakdown voltage BV and the on-resistance Ron are two key parameters of the power MOS device. In order to maintain the breakdown voltage performance of the device and reduce the on-resistance of the device, a super-junction MOS structure is formed on the basis of the traditional MOS device structure. The super-junction MOS device is characterized in that periodic special-shaped doping is led out of a drift region of a traditional MOS structure, for example, for an NMOS device, a P-type column is formed by doping in an N-type drift layer of the NMOS device, namely, a super-junction structure with P-type and N-type alternately arranged is formed, so that an electric field of the drift region is approximately uniformly distributed.
However, as the device size is continuously reduced, the distance between the adjacent polysilicon trench electrodes is continuously reduced, referring to fig. 3, which shows a schematic cross-sectional structure of a deep trench super junction DMOS device after the related art size is reduced, it can be seen from fig. 3 that the distance between the polysilicon trench electrode 310 and the P-type pillar 320 is smaller and even directly adjacent after the device size is reduced, so that after the polysilicon trench electrode 310 is applied with a voltage to make the device conduct forward, one side (a region) of the P-type pillar 320 close to the polysilicon electrode is also inverted to form a channel, thereby extending the channel, which is unfavorable for the breakdown voltage BV and the on-resistance Ron of the device.
Disclosure of Invention
The application provides a deep trench super-junction DMOS device and a manufacturing method thereof, which can solve the problem that the small-size deep trench super-junction DMOS device in the related technology is easy to have channel extension.
To solve the technical problem described in the background art, a first aspect of the present application provides a deep trench super junction DMOS device, the deep trench super junction DMOS device includes:
a first conductivity type base layer comprising opposing front and back sides, the front side forming a source and the back side forming a drain;
a second conductive type well region located at a lower layer of the source electrode;
buried layer pillars of a second conductivity type formed in the first conductivity type base layer and extending downward from a lower surface of the second conductivity type well region;
the polysilicon trench structure is formed on the left side and the right side of the second conductive type buried layer column, and extends downwards from the front surface to sequentially pass through the source electrode and the second conductive type well region, and the bottom end of the polysilicon trench structure extends out of the second conductive type well region;
and the first conduction type injection region surrounds the bottom end of the polysilicon trench structure extending out of the second conduction type well region.
Optionally, a region proximate to a bottom sidewall of the polysilicon trench structure maintains the first conductivity type.
Optionally, the first conductivity type implant region is in upward contact with a lower surface of the second conductivity type well region.
In order to solve the technical problems described in the background art, a second aspect of the present application provides a method for manufacturing a deep trench super junction DMOS device, the method for manufacturing a deep trench super junction DMOS device includes the following steps:
providing a first conductivity type base layer comprising opposing front and back sides;
forming laterally spaced polysilicon trench structures in the first conductivity type base layer, forming a first conductivity type implant region surrounding a bottom end of the polysilicon trench structures;
injecting second conductivity type impurities to enable the upper layer of the first conductivity type substrate layer to be in inversion type to form a second conductivity type well region, and enabling the bottom end of the polycrystalline silicon groove structure to extend downwards out of the second conductivity type well region;
performing first conductivity type injection, forming a source electrode on the front surface of the first conductivity type substrate layer, and forming a drain electrode on the back surface;
and implanting second conductivity type impurities, and forming second conductivity type buried columns in the intervals between two adjacent polysilicon trench structures, wherein the second conductivity type buried columns extend downwards from the lower surface of the second conductivity type well region.
Optionally, the second conductivity type impurity is implanted, a second conductivity type buried layer pillar is formed in a space between two adjacent polysilicon trench structures, the second conductivity type buried layer pillar extends downwards from the lower surface of the second conductivity type well region, the dose of the second conductivity type impurity is smaller than that of the first conductivity type impurity which is selectively implanted, and the first conductivity type impurity is implanted in the step of forming a first conductivity type implanted region surrounding the bottom end of the polysilicon trench structure.
Optionally, second conductivity type buried pillars are formed in the space between two adjacent polysilicon trench structures, and after the step of extending the second conductivity type buried pillars downward from the lower surface of the second conductivity type well region is completed, the region near the bottom sidewall of the polysilicon trench structure maintains the first conductivity type.
Optionally, the step of implanting second conductivity type impurities to form a second conductivity type well region, wherein the bottom end of the polysilicon trench structure extends downwards out of the second conductivity type well region, the implantation dosage of the second conductivity type impurities is larger than that of the step of selectively implanting first conductivity type impurities to form a first conductivity type implantation region surrounding the bottom end of the polysilicon trench structure, and the implantation dosage of the first conductivity type impurities is larger than that of the first conductivity type impurities in the step of selectively implanting the first conductivity type impurities.
Optionally, after the step of implanting the second conductivity type impurity to form the second conductivity type well region and the step of extending the bottom end of the polysilicon trench structure downward beyond the second conductivity type well region is completed, the first conductivity type implanted region is contacted with the lower surface of the second conductivity type well region upward.
The technical scheme of the application at least comprises the following advantages: the method and the device can be used for keeping the shape of the area around the bottom end of the polysilicon trench structure, and meanwhile, the formation of the trench at the side wall of the polysilicon trench structure is not affected, so that the problem that the trench is prolonged easily when a small-size deep trench super-junction DMOS device is formed is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 shows a schematic cross-sectional structure of a deep trench super-junction DMOS device according to an embodiment of the present application;
fig. 1a shows a schematic cross-sectional structure of a deep trench super junction DMOS device when the device is turned on in the forward direction;
fig. 2 shows a flowchart of a method for manufacturing a deep trench super junction DMOS device according to an embodiment of the present application;
FIG. 2a shows a schematic cross-sectional structure of the device after completion of step S22;
fig. 2b shows a schematic cross-sectional structure of the device after completion of step S24;
fig. 2c shows a schematic cross-sectional structure of the device after completion of step S25;
fig. 3 shows a schematic diagram of a partial cross-sectional structure of a deep trench super junction DMOS device after the related art has been scaled down.
Detailed Description
The following description of the embodiments of the present application will be made apparent and complete in conjunction with the accompanying drawings, in which embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
The conductivity type in the present application includes opposite first conductivity type and second conductivity type, i.e., when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductivity type is P-type, the second conductivity type is N-type.
The N-type semiconductor and the P-type semiconductor are generated according to different types of impurities doped into the semiconductor. Wherein, doping a certain element in V group of periodic table, such as arsenic or antimony donor impurity, into the semiconductor to obtain N-type semiconductor; the P-type semiconductor can be obtained by doping an acceptor impurity such as boron or indium of an element located in group iii of the periodic table into the semiconductor.
The conductivity properties of the N-type semiconductor and the P-type semiconductor are different.
Fig. 1 is a schematic cross-sectional structure of a deep trench super-junction DMOS device according to an embodiment of the present application, and the deep trench super-junction DMOS device is described below by taking a first conductivity type as an N-type and a second conductivity type as a P-type as an example.
As can be seen from fig. 1, the deep trench super junction DMOS device includes:
an N-type substrate layer 210, the N-type substrate layer 210 comprising opposing front and back sides, the front side forming a source 250 and the back side forming a drain 260.
The P-well region 240, the P-well region 240 is located under the source 250.
The P-type buried layer pillars 270 are formed in the N-type base layer 210 and extend downward from the lower surface of the P-type well region 240.
The polysilicon trench structure 220 is formed on the left and right sides of the P-type buried layer pillar 270, and the polysilicon trench structure 220 extends downward from the front surface to sequentially pass through the source 250 and the P-type well region 240, the bottom end of the polysilicon trench structure 220 extends out of the P-type well region 240, and the bottom end of the polysilicon trench structure 220 overlaps with the upper end of the P-type buried layer pillar 270.
The N-type implantation region 230 surrounds the bottom end of the polysilicon trench structure 220 extending out of the P-type well region 240, and the N-type implantation region 230 maintains the N-type region near the bottom sidewall of the polysilicon trench structure 220, i.e., after the subsequent P-type buried layer column 270 is implanted and formed, the region near the bottom sidewall of the polysilicon trench structure 220 is still the N-type implantation region 230. The N-type implant region 230 contacts the bottom surface of the P-type well region 240 upward.
Referring to fig. 1a, which shows a schematic cross-sectional structure of a deep trench super-junction DMOS device during forward conduction, when the deep trench super-junction DMOS device is turned on, a forward bias voltage is applied to the polysilicon trench structure 220, and the P-type well region 240 is inverted to form an N-type channel 280 near one side of the polysilicon trench structure 220, and the bottom end of the polysilicon trench structure 220 is already surrounded to form an N-type implanted region 230, so that the N-type implanted region 230 does not need to be inverted. The forward conduction path is: carriers pass through the N-type channel 280, the N-type injection region 230, the N-type base layer 210 and reach the drain electrode 260 in sequence from the source electrode 250 to form forward current, so that the deep trench super junction DMOS device is turned on.
The embodiment can protect the surrounding area of the bottom end of the polysilicon trench structure, and meanwhile, the channel formation at the side wall of the polysilicon trench structure is not affected, so that the problem that the small-size deep-trench super-junction DMOS device is easy to have channel extension is avoided.
Fig. 2 shows a flowchart of a method for manufacturing a deep trench super-junction DMOS device according to an embodiment of the present application, and the embodiment shown in fig. 2 is used to manufacture the deep trench super-junction DMOS device shown in fig. 1.
Referring to fig. 2, the method for manufacturing the deep trench super junction DMOS device includes the following steps, which are sequentially performed:
step S21: an N-type substrate layer is provided, the N-type substrate layer comprising opposing front and back sides.
Step S22: and forming polysilicon groove structures which are transversely spaced in the N-type substrate layer, and forming a bottom N-type injection region surrounding the polysilicon groove structures.
Referring to fig. 2a, which is a schematic cross-sectional view of the device after completion of step S22, as can be seen in fig. 2a, a plurality of polysilicon trench structures 220 are formed in the N-type substrate layer 210 at intervals in a lateral direction, the polysilicon trench structures 220 extend downward from the front surface of the N-type substrate layer 210, and an N-type implantation region 230 is formed at the bottom end of each polysilicon trench structure 220, and the N-type implantation region 230 surrounds the bottom end of the polysilicon trench structure 220.
Illustratively, this step S22 may be implemented by the following steps S221 to S223:
step S221: a trench structure pattern is defined in the front side of the N-type substrate layer 210.
Alternatively, a trench structure pattern may be defined on the front side of the N-type base layer 210 by a photolithography process.
Step S222: etching the N-type substrate layer 210 based on the trench structure pattern to form a trench extending downward from the front surface of the N-type substrate layer 210;
step S223: and performing N-type impurity implantation into the trench based on the trench structure pattern to form an N-type implantation region 230 surrounding the bottom end of the trench.
Alternatively, in performing step S223, N-type impurity implantation may be performed into the trench at a certain inclination angle, such that the implanted N-type impurity passes through the side and bottom surfaces of the trench bottom end into the N-type base layer located around the trench bottom end, thereby forming the N-type implantation region 230 surrounding the trench bottom end.
In addition, in the step S223, N-type impurity implantation may be performed into the trench at a certain inclination angle based on the trench structure pattern, so as to form an N-type implantation region 230 surrounding the bottom end of the trench.
Step S224: polysilicon is deposited into the trenches to form the polysilicon trench structure 220.
Thus, the N-type implantation region 230 formed in step S223 surrounds the bottom end of the polysilicon trench structure 220, and after the polysilicon trench structure 220 and the N-type implantation region 230 are formed, the N-type implantation region formed in step S221 needs to be removed for performing the subsequent steps.
Step S23: p-type impurities are injected, so that the upper layer of the N-type substrate layer is reversely formed into a P-type well region, and the bottom end of the polysilicon trench structure extends downwards out of the P-type well region.
The dosage of P-type impurity injected in the step S23 is larger than that of N-type impurity injected in the step S22, so that the N-type injection region surrounding the bottom end of the polysilicon trench structure is contacted with the P-type well region upwards after the step S23 is completed.
Step S24: and performing N-type injection, forming a source electrode on the front surface of the N-type substrate layer, and forming a drain electrode on the back surface.
Referring to fig. 2b, which shows a schematic cross-sectional structure of the device after completion of step S24, as can be seen from fig. 2b,
the upper layer of the N-type substrate layer 210 is inverted to form a P-type well region 240, the bottom end of the polysilicon trench structure 220 extends downward out of the P-type well region 240, the front surface of the N-type substrate layer 210 forms a source 250, and the back surface of the N-type substrate layer 210 forms a drain 260.
Step S25: p-type impurities are injected, P-type buried columns are formed in the interval between two adjacent polysilicon trench structures, and the P-type buried columns extend downwards from the lower surface of the P-type well region.
The dosage of the P-type impurity injected in the step S25 is smaller than that of the N-type impurity injected in the step S22, so that the N-type injection region near the bottom side wall of the polysilicon trench structure is not inverted after the step S25 is completed, namely, the region near the bottom side wall of the polysilicon trench structure is kept to be N-type.
After this step S25 is completed, the device structure shown in fig. 2c is formed, and as can be seen in fig. 2c, the P-type buried pillars 270 are formed in the N-type base layer 210 and extend downward from the lower surface of the P-type well region 240, and the N-type implanted region 230 near the bottom sidewall of the polysilicon trench structure 220 is not inverted, i.e., the region near the bottom sidewall of the polysilicon trench structure 220 remains N-type.
The embodiment can protect the surrounding area of the bottom end of the polysilicon trench structure, and meanwhile, the channel formation at the side wall of the polysilicon trench structure is not affected, so that the problem that the small-size deep-trench super-junction DMOS device is easy to have channel extension is avoided.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.
Claims (8)
1. A deep trench super junction DMOS device, the deep trench super junction DMOS device comprising:
a first conductivity type base layer comprising opposing front and back sides, the front side forming a source and the back side forming a drain;
a second conductive type well region located at a lower layer of the source electrode;
buried layer pillars of a second conductivity type formed in the first conductivity type base layer and extending downward from a lower surface of the second conductivity type well region;
the polysilicon trench structure is formed on the left side and the right side of the second conductive type buried layer column, and extends downwards from the front surface to sequentially pass through the source electrode and the second conductive type well region, and the bottom end of the polysilicon trench structure extends out of the second conductive type well region;
and the first conduction type injection region surrounds the bottom end of the polysilicon trench structure extending out of the second conduction type well region.
2. The deep trench superjunction DMOS device of claim 1, wherein regions near bottom sidewalls of said polysilicon trench structure remain of a first conductivity type.
3. The deep trench superjunction DMOS device of claim 1, wherein said first conductivity type implanted region is in upward contact with a lower surface of said second conductivity type well region.
4. The manufacturing method of the deep-trench super-junction DMOS device is characterized by comprising the following steps of:
providing a first conductivity type base layer comprising opposing front and back sides;
forming laterally spaced polysilicon trench structures in the first conductivity type base layer, forming a first conductivity type implant region surrounding a bottom end of the polysilicon trench structures;
injecting second conductivity type impurities to enable the upper layer of the first conductivity type substrate layer to be in inversion type to form a second conductivity type well region, and enabling the bottom end of the polycrystalline silicon groove structure to extend downwards out of the second conductivity type well region;
performing first conductivity type injection, forming a source electrode on the front surface of the first conductivity type substrate layer, and forming a drain electrode on the back surface;
and implanting second conductivity type impurities, and forming second conductivity type buried columns in the intervals between two adjacent polysilicon trench structures, wherein the second conductivity type buried columns extend downwards from the lower surface of the second conductivity type well region.
5. The method of fabricating a deep trench super junction DMOS device of claim 4, wherein said implanting a second conductivity type impurity forms a second conductivity type buried pillar in a space between two adjacent ones of said polysilicon trench structures, said second conductivity type buried pillar extending downwardly from a lower surface of said second conductivity type well region at a lower dose than said selectively implanting a first conductivity type impurity, and wherein said implanting a first conductivity type impurity forms a first conductivity type implant region surrounding a bottom end of said polysilicon trench structure at a lower dose.
6. The method of fabricating a deep trench super junction DMOS device of claim 5, wherein a buried layer of a second conductivity type is formed in the space between two adjacent polysilicon trench structures by implanting impurities of the second conductivity type, and wherein the region adjacent to the bottom sidewall of said polysilicon trench structures remains of the first conductivity type after the step of extending the buried layer of the second conductivity type downward from the lower surface of said second conductivity type well region is completed.
7. The method of manufacturing a deep trench super junction DMOS device of claim 4, wherein said implanting a second conductivity type impurity forms a second conductivity type well region, wherein in said step of forming said polysilicon trench structure with said bottom end extending downwardly beyond said second conductivity type well region, a second conductivity type impurity is implanted at a greater dose than said selectively implanting a first conductivity type impurity, and wherein in said step of forming a first conductivity type implanted region surrounding said polysilicon trench structure with said first conductivity type impurity is implanted at a dose greater than said first conductivity type impurity.
8. The method of fabricating a deep trench super junction DMOS device of claim 7, wherein said first conductivity type implanted region is in contact with a lower surface of said second conductivity type well region after said step of implanting a second conductivity type impurity to form a second conductivity type well region, said polysilicon trench structure bottom extending downwardly beyond said second conductivity type well region is completed.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211263160.6A CN116013984A (en) | 2022-10-14 | 2022-10-14 | Deep-trench super-junction DMOS device and manufacturing method thereof |
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| CN202211263160.6A CN116013984A (en) | 2022-10-14 | 2022-10-14 | Deep-trench super-junction DMOS device and manufacturing method thereof |
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